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from 1ac463fc89c RISC-V: Add tt-ascalon-d8 pipeline description new 726006cd691 RISC-V: Add support for the XAndesvbfhcvt ISA extension. new e9a7140993b RISC-V: Add support for the XAndesvsintload ISA extension.

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config.gcc | 4 +- gcc/config/riscv/andes-vector-builtins-bases.cc | 125 +++++++++++++++++++++ ...ltins-bases.h => andes-vector-builtins-bases.h} | 22 ++-- .../riscv/andes-vector-builtins-functions.def | 51 +++++++++ gcc/config/riscv/andes-vector.md | 105 +++++++++++++++++ .../riscv/{sifive_vector.h => andes_vector.h} | 12 +- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 2 +- gcc/config/riscv/riscv-vector-builtins-types.def | 30 +++++ gcc/config/riscv/riscv-vector-builtins.cc | 53 +++++++++ gcc/config/riscv/riscv-vector-builtins.def | 2 + gcc/config/riscv/riscv-vector-builtins.h | 10 ++ gcc/config/riscv/t-riscv | 15 +++ gcc/config/riscv/vector-iterators.md | 18 +++ gcc/config/riscv/vector.md | 1 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 12 ++ .../non-policy/non-overloaded/nds_vfncvtbf16s.c | 46 ++++++++ .../non-policy/non-overloaded/nds_vfwcvtsbf16.c | 26 +++++ .../non-policy/non-overloaded/nds_vln8.c | 62 ++++++++++ .../non-policy/overloaded/nds_vfncvtbf16s.c | 46 ++++++++ .../non-policy/overloaded/nds_vfwcvtsbf16.c | 26 +++++ .../xandesvector/non-policy/overloaded/nds_vln8.c | 34 ++++++ .../policy/non-overloaded/nds_vfncvtbf16s.c | 46 ++++++++ .../policy/non-overloaded/nds_vfwcvtsbf16.c | 26 +++++ .../xandesvector/policy/non-overloaded/nds_vln8.c | 118 +++++++++++++++++++ .../policy/overloaded/nds_vfncvtbf16s.c | 46 ++++++++ .../policy/overloaded/nds_vfwcvtsbf16.c | 26 +++++ .../rvv/xandesvector/policy/overloaded/nds_vln8.c | 118 +++++++++++++++++++ 28 files changed, 1062 insertions(+), 22 deletions(-) create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.cc copy gcc/config/riscv/{sifive-vector-builtins-bases.h => andes-vector-builtins-bas [...] create mode 100644 gcc/config/riscv/andes-vector-builtins-functions.def create mode 100644 gcc/config/riscv/andes-vector.md copy gcc/config/riscv/{sifive_vector.h => andes_vector.h} (83%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non- [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non- [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non- [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/over [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/over [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/over [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-over [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-over [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-over [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overload [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overload [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overload [...]