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from 24ff83f CodeGen: If Convert blocks that would form a diamond when tai [...] new da04ce1 MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness earl [...] new 66b84cc [InstCombine] use m_APInt to allow icmp eq/ne (shr X, C2), C [...]

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Summary of changes: include/llvm/CodeGen/MIRYamlMapping.h | 2 -- include/llvm/CodeGen/MachineRegisterInfo.h | 6 +--- include/llvm/Target/TargetSubtargetInfo.h | 2 ++ lib/CodeGen/DetectDeadLanes.cpp | 4 +-- lib/CodeGen/LiveIntervalAnalysis.cpp | 7 ----- lib/CodeGen/MIRParser/MIRParser.cpp | 1 - lib/CodeGen/MIRPrinter.cpp | 1 - lib/CodeGen/MachineRegisterInfo.cpp | 7 ++++- lib/CodeGen/RenameIndependentSubregs.cpp | 4 +-- lib/Transforms/InstCombine/InstCombineCompares.cpp | 35 ++++++++++++---------- test/CodeGen/AArch64/ldst-opt-dbg-limit.mir | 2 -- test/CodeGen/AArch64/movimm-wzr.mir | 1 - test/CodeGen/ARM/ARMLoadStoreDBG.mir | 1 - .../MIR/AArch64/inst-size-tlsdesc-callseq.mir | 1 - .../MIR/AMDGPU/expected-target-index-name.mir | 3 +- .../MIR/AMDGPU/invalid-target-index-operand.mir | 3 +- test/CodeGen/MIR/AMDGPU/target-index-operands.mir | 6 ++-- test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir | 1 - test/CodeGen/MIR/Generic/register-info.mir | 3 -- test/CodeGen/MIR/Lanai/peephole-compare.mir | 9 ------ test/CodeGen/PowerPC/aantidep-def-ec.mir | 1 - test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 1 - test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 1 - test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 1 - test/CodeGen/X86/implicit-null-checks.mir | 4 --- .../DebugInfo/MIR/X86/live-debug-values-3preds.mir | 1 - test/DebugInfo/MIR/X86/live-debug-values.mir | 1 - test/Transforms/InstCombine/apint-shift.ll | 13 ++++---- test/Transforms/InstCombine/cast.ll | 4 +-- test/Transforms/InstCombine/icmp.ll | 20 +++++++++++++ test/Transforms/InstCombine/shift.ll | 17 ++++------- 31 files changed, 68 insertions(+), 95 deletions(-)