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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-aarch64-check_cross in repository toolchain/ci/qemu.

from d4127349e3 Merge remote-tracking branch 'remotes/berrange-gitlab/tags/c [...] adds a5dba9bc05 vfio: Fix CID 1458134 in vfio_register_ram_discard_listener() adds 936555bc4f vfio/pci: Change to use vfio_pci_is() adds 1bd9f1b14d vfio/pci: Add pba_offset PCI quirk for BAIDU KUNLUN AI processor adds bd306cfeee Merge remote-tracking branch 'remotes/awilliam/tags/vfio-upd [...] new b4cb178efb target/riscv: pmp: Fix some typos new 232a2c8c85 target/riscv: csr: Remove redundant check in fp csr read/wri [...] new d374575100 docs/system: riscv: Fix CLINT name in the sifive_u doc new 85198f189e docs/system: riscv: Add documentation for virt machine new bc083a51ca target/riscv: hardwire bits in hideleg and hedeleg new 6165dcb55f docs/system: riscv: Update Microchip Icicle Kit for direct k [...] new 074ca702e6 hw/riscv: sifive_u: Correct the CLINT timebase frequency new 623d53cb01 hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned new 24bfb98d06 char: ibex_uart: Update the register layout new 5ee257649f hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri new bb7e0cde3c hw/riscv: opentitan: Add the flash alias new b3d8aa2069 hw/riscv/boot: Check the error of fdt_pack() new 65388f4044 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...]

The 13 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++-- docs/system/riscv/sifive_u.rst | 2 +- docs/system/riscv/virt.rst | 138 +++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + hw/char/ibex_uart.c | 19 ++-- hw/riscv/boot.c | 6 +- hw/riscv/opentitan.c | 9 ++ hw/riscv/sifive_u.c | 12 ++- hw/vfio/common.c | 3 +- hw/vfio/pci.c | 12 ++- include/hw/pci/pci_ids.h | 3 + include/hw/riscv/opentitan.h | 3 + target/riscv/csr.c | 78 +++++++--------- target/riscv/pmp.c | 10 +-- 14 files changed, 272 insertions(+), 78 deletions(-) create mode 100644 docs/system/riscv/virt.rst