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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/llvm-project.

from 0985a8bfea4 Fix left shift overflow UB in PPC backend on LLP64 platforms adds c1d6de41a9d [mlir][CAPI] Add the missing <stdbool.h> in Support.h adds 37974b493a4 [lldb/test] Enable reverse-connect on windows too adds 62c94f06781 [RISCV] Define vector vfmul/vfdiv/vfrdiv intrinsics. adds bd576ac8d4b [RISCV] Define vector vfsgnj/vfsgnjn/vfsgnjx intrinsics. adds f86e61d8862 [RISCV] Define vector vfwadd/vfwsub intrinsics. adds 41ab45d6624 [RISCV] Define vector vfwmul intrinsics. adds 99562332e3d [lldb] [test] Update test status for NetBSD adds 35f2c3a8b41 [clang-tidy] cppcoreguidelines-pro-type-member-init: suppre [...] adds 7e84aa1b81e Fix MSVC "not all control paths return a value" warnings. NFCI. adds d86a00d8feb [RISCV] Define vslideup/vslidedown intrinsics adds 6fa1230594e [MemLoc] Fix debug print for LocationSize adds 3285ee143b7 [Analysis, IR, CodeGen] Use llvm::erase_if (NFC) adds 5d24935f220 [PGO] Remove dead member variable InstrumentFuncEntry (NFC) adds 43327ba98da [Object] Fix LFFile<ELFT>::getEntry on sizeof(size_t)==4 platforms adds e2863357de7 [lld-macho][nfc] Use split-file in order file test adds 5f9896d3b23 [lld-macho] Support Obj-C symbols in order files adds 64e47572002 [lld-macho] Have order files support filtering by archive m [...] adds bfa95b4ac79 [BasicAA] Add test for byval argument (NFC) adds f47bac5dd20 [ARM] Extra vecreduce tests with smaller than legal types. NFC adds 47dbee6790c Make NPM OptBisectInstrumentation use global singleton OptBisect adds 01d1de81963 [MC] Reject byte alignment if larger than or equal to 2**32 adds 36b0dd8f678 [OpenMP] Fixed the issue that CMake variables for OpenMP we [...] adds 1a883484afe [test] Fix reg-usage.ll under NPM adds 4dce7c2e209 [MachineLICM] delete dead flag if the duplicated def outsid [...] adds 564066524ad [PowerPC] add has side effect for SAT bit clobber intrinsic [...] adds db1616c7684 [test] Fix new-pass-manager-opt-bisect.c adds 966f1431de0 [Target] Use llvm::erase_if (NFC) new 9e4b682baf2 [RISCV][NFC] Add tests for multiplication with constant

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .../cppcoreguidelines/ProTypeMemberInitCheck.cpp | 4 + .../cppcoreguidelines-pro-type-member-init.cpp | 16 + clang/lib/Sema/SemaTemplate.cpp | 2 + clang/test/CodeGen/new-pass-manager-opt-bisect.c | 12 + lld/MachO/Driver.cpp | 94 +- lld/MachO/Writer.cpp | 18 +- lld/test/MachO/invalid/order-file-bad-arch.test | 9 - lld/test/MachO/invalid/order-file-bad-objfile.test | 10 - lld/test/MachO/order-file.s | 184 +- .../test/tools/lldb-server/gdbremote_testcase.py | 4 - .../api/multiple-targets/TestMultipleTargets.py | 1 + .../call-restarts/TestCallThatRestarts.py | 2 +- .../expression/ir-interpreter/TestIRInterpreter.py | 1 - .../expression/radar_9531204/TestPrintfAfterUp.py | 1 - .../save_jit_objects/TestSaveJITObjects.py | 1 - .../test/API/commands/expression/test/TestExprs.py | 1 - .../API/commands/gui/viewlarge/TestGuiViewLarge.py | 1 + .../commands/process/attach/TestProcessAttach.py | 1 + .../cpp_exception/TestCPPExceptionBreakpoint.py | 2 - .../TestBreakpointInGlobalConstructor.py | 1 - .../functionalities/completion/TestCompletion.py | 1 + .../TestDlopenOtherExecutable.py | 1 + .../inferior-assert/TestInferiorAssert.py | 4 - .../TestRecursiveInferiorStep.py | 1 + ...ConcurrentBreakpointDelayBreakpointOneSignal.py | 1 - .../TestConcurrentSignalDelayBreak.py | 2 +- .../TestConcurrentTwoBreakpointsOneDelaySignal.py | 2 +- .../TestConcurrentTwoBreakpointsOneSignal.py | 2 +- .../TestExitDuringExpression.py | 2 + .../TestStateAfterExpression.py | 1 + .../TestThreadSpecificBpPlusCondition.py | 2 +- .../unwind/noreturn/TestNoreturnUnwind.py | 1 - .../c/conflicting-symbol/TestConflictingSymbol.py | 1 - .../lang/c/const_variables/TestConstVariables.py | 1 - .../API/lang/c/function_types/TestFunctionTypes.py | 1 - .../lang/c/global_variables/TestGlobalVariables.py | 1 - lldb/test/API/lang/c/shared_lib/TestSharedLib.py | 2 - .../cpp/exceptions/TestCPPExceptionBreakpoints.py | 1 - .../TestNamespaceDefinitions.py | 1 - .../test/API/lang/cpp/stl/TestStdCXXDisassembly.py | 1 - lldb/test/API/lang/cpp/this/TestCPPThis.py | 1 - lldb/test/API/python_api/event/TestEvents.py | 2 +- .../lldbutil/iter/TestRegistersIterator.py | 1 + lldb/test/API/python_api/thread/TestThreadAPI.py | 1 - .../lldb-server/TestGdbRemote_vContThreads.py | 2 + .../TestVSCode_setExceptionBreakpoints.py | 1 - .../disconnect/TestVSCode_disconnect.py | 1 + lldb/test/Shell/Recognizer/assert.test | 1 + .../Functionalities/TestExpressionEvaluation.test | 2 +- .../ScriptInterpreter/Lua/watchpoint_callback.test | 1 + llvm/include/llvm/IR/IntrinsicsPowerPC.td | 42 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 33 + llvm/include/llvm/IR/OptBisect.h | 20 +- llvm/include/llvm/IR/PassManager.h | 6 +- llvm/include/llvm/Object/ELF.h | 9 +- .../include/llvm/Passes/StandardInstrumentations.h | 2 +- llvm/lib/Analysis/CGSCCPassManager.cpp | 31 +- llvm/lib/Analysis/MemoryLocation.cpp | 2 +- llvm/lib/Analysis/ScalarEvolution.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 4 +- llvm/lib/CodeGen/MachineLICM.cpp | 37 +- llvm/lib/CodeGen/RDFLiveness.cpp | 2 +- llvm/lib/CodeGen/StackMaps.cpp | 5 +- llvm/lib/IR/LLVMContextImpl.cpp | 15 +- llvm/lib/IR/LLVMContextImpl.h | 3 +- llvm/lib/IR/Metadata.cpp | 9 +- llvm/lib/IR/OptBisect.cpp | 2 + llvm/lib/MC/MCParser/AsmParser.cpp | 2 + llvm/lib/Passes/StandardInstrumentations.cpp | 8 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 8 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 10 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 +- .../Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp | 3 +- llvm/lib/Target/Hexagon/HexagonGenInsert.cpp | 8 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 +- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 91 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 5 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 353 +++- .../WebAssemblyLowerEmscriptenEHSjLj.cpp | 2 +- .../Instrumentation/PGOInstrumentation.cpp | 3 - llvm/runtimes/CMakeLists.txt | 3 + llvm/test/Analysis/BasicAA/noalias-param.ll | 19 +- .../CodeGen/PowerPC/machinelicm-cse-dead-flag.mir | 84 + llvm/test/CodeGen/PowerPC/sat-register-clobber.ll | 43 + llvm/test/CodeGen/RISCV/mul.ll | 410 ++++ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll | 881 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll | 1201 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll | 881 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll | 1201 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll | 441 ++++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll | 601 ++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll | 881 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll | 1201 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll | 881 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll | 1201 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll | 881 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll | 1201 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll | 401 ++++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll | 721 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll | 401 ++++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll | 721 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll | 401 ++++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll | 721 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll | 401 ++++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll | 721 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll | 401 ++++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll | 721 +++++++ llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll | 1705 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll | 2131 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll | 1705 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll | 2131 ++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll | 516 +++++ llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll | 575 ++++++ llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll | 447 ++++ llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll | 738 +++++++ llvm/test/MC/AsmParser/align_invalid.s | 4 + .../test/Transforms/LoopVectorize/X86/reg-usage.ll | 4 +- mlir/include/mlir-c/Support.h | 1 + 119 files changed, 28283 insertions(+), 430 deletions(-) create mode 100644 clang/test/CodeGen/new-pass-manager-opt-bisect.c delete mode 100644 lld/test/MachO/invalid/order-file-bad-arch.test delete mode 100644 lld/test/MachO/invalid/order-file-bad-objfile.test create mode 100644 llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir create mode 100644 llvm/test/CodeGen/PowerPC/sat-register-clobber.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll