[gcc] branch master updated (7c510fdcf1d -> 7c2ab5865ca) - Tcwg-commits

26 Aug 2025


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from  7c510fdcf1d arm: testsuite: make gcc.target/arm/bics_3.c generate bics again
       new  86a5e7770ca Fix RISC-V bootstrap
       new  f864fc36fe0 [PATCH] RISC-V: Add pattern for vector-scalar single-width  [...]
       new  28ab83367e8 AArch64: extend cost model to cost outer loop vect where th [...]
       new  7c2ab5865ca [PATCH] RISC-V: Add pattern for reverse floating-point divide
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Summary of changes:
 gcc/config/aarch64/aarch64.cc                      |  45 ++-
 gcc/config/riscv/autovec-opt.md                    |  38 +++
 gcc/config/riscv/riscv.cc                          |   2 +-
 gcc/config/riscv/vector.md                         |  24 +-
 gcc/testsuite/gcc.target/aarch64/pr121290.c        |  18 ++
 .../riscv/rvv/autovec/vls/floating-point-mul-2.c   |   2 +-
 .../riscv/rvv/autovec/vls/floating-point-mul-3.c   |   2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c  |   4 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c  |   5 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c  |   5 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c  |   4 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c  |   4 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c  |   5 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c  |   5 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c  |   5 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h  | 125 +++++++++
 .../riscv/rvv/autovec/vx_vf/vf_binop_data.h        | 304 +++++++++++++++++++++
 .../vx_vf/{vf_mulop_run.h => vf_binop_run.h}       |  21 +-
 ...{vf_vfmadd-run-1-f16.c => vf_vfmul-run-1-f16.c} |  15 +-
 .../riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c   |  15 +
 .../riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c   |  15 +
 ...f_vfnmadd-run-1-f16.c => vf_vfrdiv-run-1-f16.c} |  15 +-
 .../riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c  |  19 ++
 .../riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c  |  19 ++
 28 files changed, 680 insertions(+), 44 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/pr121290.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vf_mulop_run.h => vf_binop_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vf_vfmadd-run-1-f16.c => vf [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vf_vfnmadd-run-1-f16.c => v [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c
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