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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-project.

from 46d96c02b55 Fix uninitialized variable analyzer warning. NFCI. adds 67ad4c2f27b [X86][SSE] Add HADD/HSUB SimplifyDemandedVectorElts tests adds 1db0cc9e1be [X86][SSE] Add integer HADD/HSUB SimplifyDemandedVectorElts tests adds 4871a3057e4 [X86][SSE] Tweaked HADD/HSUB SimplifyDemandedVectorElts adds e7c51137aa4 HexagonConstEvaluator::evaluateHexExt - check incoming opco [...] adds 8039e838c67 [MC][X86] Add test cases from PR14056 adds 26f2b13a659 [X86] Use TLI.getRegClassFor to simplify some more fast ise [...] adds 74a436596d7 [X86] Sink some fast isel code into the only if that uses it. NFC adds c9d7484aa36 [X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use th [...] adds 5e0f92acad9 FixupLEAPass::fixupIncDec - non-LEA opcodes should not happ [...] adds e4c5b6d9bdd [X86][SSE] Add SimplifyDemandedVectorElts HADD/HSUB handling. adds a10f016006c [NFC] yaml2obj/yam2elf.cpp whitespace changes: dos2unix rem [...] adds 6b10fde69b8 [CostModel][X86] Add min/max reduction costs for all SSE targets adds 6f7c62d70ff [X86] Add avx512f tests for boolean reduction adds 91e697c145a [X86] Add scalar shl+lshr -> shift+mask tests (PR40758) adds 73e8b674382 Revert rL360499 and rL360464 from cfe/trunk: Reject attempt [...] adds 0303e8a3fd8 [CommandLine] Add long option flag for cl::ParseCommandLine [...] adds 3fa632a1123 [X86] Updated shift-mask test targets for D61830 adds 605a840747b [DAG] Add SimplifyDemandedBits support for BITREVERSE adds fda6bffd3bf [X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW Simpli [...] adds 91ab86fd29b [utils] update_test_checks.py: allow opt-8, opt-9 new d3d6f4f65c7 Fix handling of objects under construction during constant [...] new debad6460b6 Reject attempts to call non-static member functions on obje [...]

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Summary of changes: clang/include/clang/AST/Redeclarable.h | 7 + llvm/include/llvm/Support/CommandLine.h | 3 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 + llvm/lib/Support/CommandLine.cpp | 60 +- .../lib/Target/Hexagon/HexagonConstPropagation.cpp | 2 + llvm/lib/Target/X86/X86FastISel.cpp | 55 +- llvm/lib/Target/X86/X86FixupLEAs.cpp | 2 + llvm/lib/Target/X86/X86ISelLowering.cpp | 54 +- llvm/lib/Target/X86/X86InstrCompiler.td | 10 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 96 ++- .../Analysis/CostModel/X86/reduce-smax-widen.ll | 156 ++--- llvm/test/Analysis/CostModel/X86/reduce-smax.ll | 124 ++-- .../Analysis/CostModel/X86/reduce-smin-widen.ll | 154 ++--- llvm/test/Analysis/CostModel/X86/reduce-smin.ll | 124 ++-- .../Analysis/CostModel/X86/reduce-umax-widen.ll | 156 ++--- llvm/test/Analysis/CostModel/X86/reduce-umax.ll | 124 ++-- .../Analysis/CostModel/X86/reduce-umin-widen.ll | 156 ++--- llvm/test/Analysis/CostModel/X86/reduce-umin.ll | 124 ++-- llvm/test/CodeGen/AMDGPU/bitreverse.ll | 3 +- llvm/test/CodeGen/X86/bitcast-vector-bool.ll | 73 ++- llvm/test/CodeGen/X86/combine-bitreverse.ll | 2 - .../CodeGen/X86/fast-isel-select-pseudo-cmov.ll | 196 ++++++ .../CodeGen/X86/horizontal-shuffle-demanded.ll | 381 ++++++++++++ llvm/test/CodeGen/X86/masked_store.ll | 82 +-- llvm/test/CodeGen/X86/shift-mask.ll | 536 ++++++++++++++++ llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 532 +++++++++++++--- llvm/test/CodeGen/X86/vector-reduce-or-bool.ll | 527 +++++++++++++--- llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll | 680 +++++++++++++++++---- llvm/test/MC/X86/x86-64.s | 8 + .../SLPVectorizer/X86/horizontal-minmax.ll | 90 +-- llvm/tools/yaml2obj/yaml2elf.cpp | 64 +- llvm/unittests/Support/CommandLineTest.cpp | 73 +++ llvm/utils/update_test_checks.py | 3 +- 33 files changed, 3610 insertions(+), 1057 deletions(-) create mode 100644 llvm/test/CodeGen/X86/horizontal-shuffle-demanded.ll create mode 100644 llvm/test/CodeGen/X86/shift-mask.ll