This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch stable in repository llvm.

from 2dfb4034816 Creating branches/google/stable and tags/google/stable/2018 [...] adds 1184a94abb6 [X86] Make v2i1 and v4i1 legal types without VLX adds edb228306c0 [X86] Remove unneeded code from combineGatherScatter that u [...] adds dfa1e7c2672 [DAG] Fix for Bug PR34620 - Allow SimplifyDemandedBits to l [...] adds c0e1332bdb2 X86 Tests: Add Tests for PMADDWD selection. NFC. adds 846e3cad7f8 [X86] Revert accidental change to CMakeLists.txt in r321952 adds 16819e6bda3 [SLPVectorizer] Reintroduce std::stable_sort(properlyDominates()). adds 1a43ebcad28 Revert "[SCCP] Manually fold branches on undef." adds a4bb1920beb [X86] Add VSHUFF32X4 and similar instructions to load foldi [...] adds e4f4b771da9 [X86] Simplify some code in lower1BitVectorShuffle by relyi [...] adds fbe3e1c4cd3 [llvm-readobj] Support -needed-libs option for Mach-O files adds b10b1580534 Don't try to run MCJIT/OrcJIT EH tests when C++ library is [...] adds f3b2c065d54 [X86] Add patterns to allow 512-bit BWI compare instruction [...] adds 10c0bf7a263 [X86] Replace CVT2MASK ISD opcode with PCMPGTM compared to zero. adds d8b1487cb04 [X86] Remove side-effects from determineCalleeSaves adds 05828fa2811 [X86] Renamed CodeGen test adds a646970af8f [ARM] Fix PR35481 adds c5a9d9b7a5d [SystemZ] Comment fix in SystemZElimCompare.cpp adds 14e29de03db [DAGCombine] Fix for PR35761 adds ef7f9d0c03a [SLP] Fix PR35628: Count external uses on extra reduction a [...] adds 7c83c156f0b [SLP] Fix PR35777: Incorrect handling of aggregate values. adds 5feb0d9f5b4 [ARM] Fix PR35379 - incorrect unwind information when compi [...] adds ae612d7dfdd [InstCombine] fold min/max tree with common operand (PR35717) adds 80fc28f975f [DAG] Teach BaseIndexOffset to correctly handle with indexe [...] adds 3be0f86cb73 [mips] Improve diagnostics for instruction mapping adds db9af3fb6a3 Emit Function IDs table for Control Flow Guard adds ca5199fe25e [CVP] Replace incoming values from unreachable blocks with undef. adds 42eab8ac30a [mips] Remove duplicated R6 EVA instructions adds b4a3670a708 Revert "Emit Function IDs table for Control Flow Guard" adds 1ccef220b2e Fixed spelling mistake. NFCI. adds cc2e1c221c3 [TargetLibraryInfo] fix finite mathlib function availability adds c40df7553c3 [LiveDebugValues] Change condition for block termination re [...] adds a8b0169e5ea [ValueTracking] remove overzealous assert adds 29defdea8f4 Add lit.local.cfg in test/DebugInfo/MIR/Mips/ adds bda2efb5660 ArgPromotion: Allow setting MaxElements in the new-style pass adds 3693c1f4595 Fix uninitialized read error reported by MSAN. adds 4794bea0230 [cmake] Pass CMAKE_MAKE_PROGRAM to native configure adds e9fb716fe6b AlwaysInliner: Alow setting InsertLifetime in the new-style pass adds ecb72f41193 [PowerPC] Manually schedule the prologue and epilogue adds 3e1ae868476 [X86] Remove GCCBuiltin from int_x86_avx512_cvtb2mask_128 a [...] adds f5a4b472011 [CMake] Support for cross-compilation when build runtimes adds 3f8e15a6280 [MachineOutliner] AArch64: Handle instrs that use SP and wi [...] adds 80bcd57901e [X86] Remove unnecessary isel pattern that is a combination [...] adds 7ef3f8d9a1f [X86] Remove llvm.x86.avx512.cvt*2mask.* intrinsics and aut [...] adds 63c5ae2ff98 Revert "[PowerPC] Manually schedule the prologue and epilogue" adds aa847cebc78 Remove unused function HvxSelector::zerous. adds 16ee4086842 [PowerPC] Can not assume an intrinsic argument is a simple type. adds a377183cff1 [CGP] Fix Complex addressing mode for offset adds 090a0d657fb [SCEV] Do not cache S -> V if S is not equivalent of V adds fe61b632599 [X86] Allow more cmpps/pd immediate encodings to be commute [...] adds cb3923fb1cf [cmake] Use symlinks for Windows-hosted toolchains built on Unix adds b89275f988f Instrument Control Flow For Indirect Branch Tracking adds 27033c54209 [Nios2] Arithmetic instructions for R1 and R2 ISA. adds 714260a2fed [AArch64][SVE] Asm: Add parsing of merging/zeroing suffix f [...] adds 4e1cf66e6fb [MIR] Add support for the frame-destroy MachineInstr flag adds d3e342783da [InstCombine] Add pow2 mul -> shl tests for vectors with un [...] adds 8e2f4b41a12 [AArch64][SVE] Asm: Add predicated ADD/SUB instructions adds b9261dc3594 [X86][AVX] Add v2i64/v2f64 load tests adds 0d0979698a3 Reverted r322073 because of AddressSanitizer failure on san [...] adds 5646bdb21b9 [InstCombine] Check for out of range ashr values using APIn [...] adds 9f32fd27a8e [EarlyCSE] Salvage debug info during DCE adds b56f822bc76 [DAG] Elide overlapping stores adds 93f5fcdff38 [CodeGen] Don't print register classes in -debug output adds 8abb7fa6657 [SelectionDAG] lower math intrinsics to finite version of l [...] adds 2a21599e1df [CodeGen] Print frame-setup/destroy flags in -debug output [...] adds 8d3a0bc0c49 X86 Tests: Add common check prefix to test-case. NFC. adds a0c74d2002c X86 Tests: Update more isel tests with FastVariableShuffle feature adds 4f407a2b19a Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SU [...] adds 861f6eb2491 [Support] Add WritableMemoryBuffer::getNewMemBuffer adds 74e1b78a9dc [Support] Use realpath(3) instead of trying to open a file. adds 2cba0cc3859 [CodeGen] Don't print "pred:" and "opt:" in -debug output adds ff58e7c6d9b [TargetParser] Add missing armv8l ARMv8 variant. adds 21f75f812f8 Test commit adds 3db29f781f0 [lli] Make lli support -mcpu=native for CPU autodetection adds 7481a4cf21d [X86] Add a DAG combine to combine (sext (setcc)) with VLX adds 4d8dc918b40 [lit] Implement "-r" option for builtin "diff" command + a [...] adds 5e57c182840 Fix crash when linking metadata with ODR type uniquing adds 55a661586aa [InstCombine] weaken assertions for icmp folds (PR35846) adds 904cb14b26e [WebAssembly] Update libcall signature lists adds c719b31f2b7 [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86. adds 6ec8f0bf3c7 Make one of the emitFill methods non virtual. NFC. adds 2fd0a70e2df [Option] For typo '-foo', suggest '--foo' adds 283d9781d91 Add a pass to generate synthetic function entry counts. adds c50bdd9ce60 Inline a emitFill variant that is only used once. NFC. adds 63b6c9baf73 Don't duplicate names in comments. NFC. adds a6cca0e518a Profiling tests: Endianess XFAIL for powerpc- (32-bit) adds 41985cbc8e0 NewGVN: Fix PR/33367, which was causing us to delete non-co [...] adds b763cd8c493 [COFF] Process /EXPORT option in fastpath adds 0eaae26af34 [AMDGPU] Fixed incorrect uniform branch condition adds ebe2b0b004f [SelectionDAG] Fixed f16-from-vector promotion problem adds 6b54fc31e57 [WebAssembly] Explicitly specify function/global index spac [...] adds 8b2b7db3961 Don't create MCFillFragment directly. adds a630e3e00c8 [PowerPC] Manually schedule the prologue and epilogue adds 5489d322ef9 [IPSCCP] Remove calls without side effects adds ce329ac9cbd ADT: Add a range-based version of std::copy adds d37825459b7 Add a test. adds dbc354264d8 [WebAssembly] MC: Use zero for provisional value of undefin [...] adds 5d5caec1a9c Use a MCExpr for the size of MCFillFragment. adds 9004bff3469 temp adds 38e8da83a1d Tidy some grammar in some comments adds e1e7096503f [DWARFv5] MC support for MD5 file checksums adds e92250ac8f3 [WebAssembly] Add COMDAT support adds f19ed7af352 Reland "Emit Function IDs table for Control Flow Guard" adds e41f5c81f56 [LoopRotate] Detect loops with indirect branches better (we [...] adds ee4fbee7148 LowerTypeTests: Add limited support for aliases adds c7c090f1632 [ORC] Re-apply r321838 again with a workaround for a bug pr [...] adds 52483265a57 [llvm-readobj] Consistent use of ScopedPrinter adds b9313751950 [MIR] Repurposing '$' sigil used by external symbols. Repla [...] adds 6adb8a3e59a Add explanatory comment to LoadStoreVectorizer. adds 412260f8008 [ExecutionEngine] Remove an unused variable. adds 6880dba367e [ORC] Incorporate Dave Blaikie's feedback on r319839. adds b5930e85160 [SystemZ] Check for legality before doing LOAD AND TEST tr [...] adds 2c58c90e933 [ARM GlobalISel] Legalize G_CONSTANT for scalars > 32 bits adds 8d4f82b5e41 [SelectionDAGBuilder] Chain prefetches less aggressively. adds 9d528ea00b1 [ARM GlobalISel] Legalize s32/s64 G_FCONSTANT adds fe1f6bbc8a2 Temporarily revert adds 1d8ca3c3dc8 [TableGen][AsmMatcherEmitter] Generate assembler checks for [...] adds 145d75119b8 [ARM GlobalISel] Legalize G_FNEG for s32 and s64 adds 96d0a4da9fc [ARM GlobalISel] Map G_FNEG to the FPR bank adds 9c0a0ea7397 [ARM GlobalISel] Add inst selector tests for G_FNEG s32 and s64 adds 55c93e1f45f [AArch64][SVE] Asm: Add support for (mov|dup) of scalar adds d3e3709b027 [X86][SSE] Add v2f64 u2 shuffle test adds 0d3b6634671 Avoid inlining if there is byval arguments with non-alloca [...] adds a411aee2564 [X86][SSE] Add some basic FABS combine tests adds 2744714072d Fix -Wdocumentation warning by removing empty @brief. NFCI adds 18ab0b4852f [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support adds 2360e8a4374 X86 Tests: Add isel tests for truncate-extract_vector-extend. NFC. adds b9d31dadee9 [X86][MMX] Pull out common MMX VT test. NFCI. adds e4f2c80d8a6 [X86][MMX] Add test for PR35869 adds 1f2edf66a2a [MIR] Update MIRLangRef with documentation on bundled instructions adds 11adaf9955a AArch64: Fix emergency spillslot being out of reach for lar [...] adds 0dc649b1f5e [InstCombine] add test to show missed bswap; NFC adds 4f319f2682c [MachineOutliner] Outline ADRPs adds 703dd67544f [SelectionDAG][X86] Explicitly store the scale in the gathe [...] adds f23fe79caaa Test commit access adds 2e927189047 [RISCV] Support for varargs adds 58c4e96dc99 [RISCV] Support stack frames and offsets up to 32-bits adds 077409ff7e5 [RISCV] Add basic support for inline asm constraints adds 19f4e05ad98 [RISCV] Add support for llvm.{frameaddress,returnaddress} i [...] adds c752a363cf7 [RISCV] Implement branch analysis adds 40cc91a8f56 TargetLoweringBase: The ios simulator has no bzero function. adds 8ef96aef09a [RISCV] Implement support for the BranchRelaxation pass adds 5cf8c806693 [SLP] Add/update tests for SLP vectorizer, NFC. adds 9d85fa084af LiveRangeEdit: Simplify code; NFC adds 6cb095aa82a [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubt [...] adds d5651588f19 LiveRangeEdit: Inline markDeadRemat() into only user; NFC adds 682df3f9a23 Revert "AArch64: Fix emergency spillslot being out of reach [...] adds f7a79c98e5c [AArch64] add tests for notted variants of min/max; NFC adds b22abd24b6a SmallVector: fix use-after-poison MSAN error in destructor adds 5866a4d5ad9 [SimplifyCFG] Add cut-off for InitializeUniqueCases. adds a47fcdf56a6 [NFC] Commit to mention that r322248 is actually made by An [...] adds 861d9546fc5 [DWARF][NFC] Overload AsmPrinter::emitDwarfStringOffsets() [...] adds 3b174d7fb0c [X86] Optimize v2i32/v2f32 scatters. adds a4c68ceeeb6 [InstCombine] Missed optimization in math expression: sin(x [...] adds 50a58623288 [CodeView] Fix the type for a variadic argument adds a7386f0bb3b [X86] Fix unused variable in release builds. adds c1db41826aa [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB r [...] adds e42ccd65cd5 [Mips] Handle one byte unsupported relocations adds 945cca4ed0f Implementation of X86Operand::print. Differential Revision: [...] adds 585e4d50406 [RISCV] Reserve an emergency spill slot for the register sc [...] adds c33edc6aae0 X86: Fix LowerBUILD_VECTORAsVariablePermute for case Src is [...] adds 9901953429f [VectorLegalizer] Remove broken code in ExpandStore. adds 1694ebbaaf7 [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding adds e35ff4e49b6 [FuzzMutate] Avoid using swifterror as a source operand adds 83d93d47c24 [InstCombine] add min3-with-nots test (PR35875); NFC adds d0807050dd4 [ValueTracking] recognize min/max-of-min/max with notted op [...] adds f5200f6e382 [InstCombine] For cos/sin -> tan copy attributes from cos i [...] adds 934005581fa [InstCombine] Apply the fix from r322284 for sin / cos -> tan too adds a8c7c21d294 [NFC] Abstract out source argument index in MemTransferInst. adds 5b07bb01a03 [docs] Update Phabricator docs about setting repository for [...] adds 8b19a5d46ef [AArch64] Remove Unsupported = 1 flag for the WriteAtomic W [...] adds 1719a98cf0a [X86][SSE] Drop old insertps stack folding test adds ce7fc60a2bf X86: Refactor type-splitting to target-legal size vector to [...] adds d69c23cbe00 X86 Tests: Add zext cases in (trunc (subvector)) test. NFC adds 18780e4d4a3 [Hexagon] Use SetVector when queuing nodes to scan in selec [...] adds 542cfb168d5 [Hexagon] Impose limits on container sizes in HexagonGenInsert adds 20afd373f62 DAGCombine: Let truncates negate extension through extract- [...] adds eeebc9ffe02 [Hexagon] Cast elements to correct type when creating const [...] adds c0f35f84520 [Hexagon] Fix building 64-bit vector from constant values adds 3d4e94d1877 dag-combine: Transfer debug information when folding (zext [...] adds 03af6d41250 Use size_t to represent the size of a StringMapEntry length [...] adds 2b290a98f88 [WebAssemly] Rename and improve formatting for ctor/dtor test adds e470c702055 [X86] Legalize 128/256 gathers/scatters on KNL by using wid [...] adds 2c77fcc6e13 [WebAssemlby] MC: Don't write COMDAT symbols as global imports adds 94ecdace25e [Sink] Really really fix predicate in legality check adds 5431b562d29 [arm] Implement Target Operand Flag MIR serialization. adds d65aefc0e87 PeepholeOptimizer: Do not form PHI with subreg arguments adds 103c73c85e1 Tighten up DIFile verifier for checksums adds 1e1801ccb05 Make internal/private GVs implicitly dso_local. adds d0a44769adf PeepholeOptimizer: Fix for vregs without defs adds c42b49a3879 [InstSimplify] add tests for implied cmp with zero (PR35790); NFC adds 7cecff0f6f5 [hwasan] Stack instrumentation. adds e5f83314a1d PeepholeOpt cleanup/refactor; NFC adds efa3fe9ab20 [InstSimplify] fold implied cmp with zero (PR35790) adds f2243a7f0e3 [WebAssembly] MC: Remove SetUsed argument when calling MCSy [...] adds fb82947447c Revert r322279 due to Skylake miscompile. adds b8d3880c385 [ORC] Add a stub ExecutionSession and VModuleKey type. adds 0a75940cb98 Use ELF{32,64}{LE,BE} instead of ELFType<{little,big}, {tru [...] adds d4e08e171e1 [WebAssembly] Don't allow functions to be named twice adds 478b380537b Fix typo. adds c74d471711a [RISCV] Pass MCSubtargetInfo to print methods. adds 5a286a00411 Instead of ELFFile<ELFT>::Type, use ELFT::Type. NFC. adds 97f96f6d3f1 [CMake] Add LLVM_ENABLE_IDE option to better process source [...] adds 9c49bb65384 [X86] Disable movsq/stosq/scasqcmpsq/lodsq parsing in 64-bit mode. adds 176601f8263 [X86] Disable sldtq parsing in 64-bit mode. adds 0e158bf49b5 [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. adds 86b3702c2d9 [X86] Don't require suffix on 'clr' mnemonic in intel syntax adds a469e54dccb [X86] Don't allow lods/stos/scas/cmps/movs to be parsed wit [...] adds 8cca8822d95 [LoopDeletion] Handle users in unreachable block adds 7356a977a5a [CGP] Re-enable Select in complex addressing mode adds ef93cf0a24b [ARM] Fix erroneous availability of SMMLS for Armv7-M adds 8eb918fc8ad [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR adds 203daf128ef [IRCE][NFC] Make range check's End a non-null SCEV adds 6ee561bf04f [ARM GlobalISel] Legalize G_FMA adds f4d71c6ec7f [ARM GlobalISel] Map G_FMA to FPR adds 7156d518893 [ARM GlobalISel] Add inst selector tests for G_FMA adds bef5f248b85 Revert "[PowerPC] Manually schedule the prologue and epilogue" adds 509fe161ac2 [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP adds 6f9258f3c37 [PowerPC] Don't miscompile rotate+mask into an ANDIo if it [...] adds 0e050ed9a82 [llvm] Set up .arcconfig to point to Diffusion L repository adds 379dc2786ea [docs] Tweak update to Phabricator docs about setting repos [...] adds 41f99d78957 Allow dso_local on ifunc. adds a11d70e128d [X86] Remove unused isel pattern for zero extend from v16i1 [...] adds 30b413b0288 [X86][AVX] Regenerate element insertion tests adds b59aba61d50 [X86][SSE] Force blend domains on stack folding tests adds b8b639505b0 MC: Remove redundant `SetUsed` arguments in MCSymbol methods adds 9063ca5c8bd [DWARFv5] CodeGen support for MD5 file checksums adds e2f3fc91e4b [AArch64] Fix scheduling resources for post indexed loads a [...] adds 72ff17fa7ce Add toothpicks to test from r322391 adds 1b2f7ed6f00 Remove ELFDataTypeTypedefHelper class. adds 99a85c5f420 [llvm-cov] Skip unnecessary coverage computations for "expo [...] adds 3bd99e29d34 Silence GCC 7 warning by using an enum class. adds e2b0a2aafa1 Try to fix more bots after r322391 adds a57b9dfaee5 [JumpThreading] Preservation of DT and LVI across the pass adds d6fbd6ac450 AMDGPU/SI: Add d16 support for buffer intrinsics. adds 87f140feb28 [NFC] Change MemIntrinsicInst::setAlignment() to take an un [...] adds 0b5677cbf87 Update MSF File Documentation. adds 292965c406b Allow unaligned access to ELF file data structures. adds ac338a42f02 [InstSimplify] add tests for implied ptr cmp with null (PR3 [...] adds bc95ef32528 [AMDGPU] stop image_store being moved illegally adds cfe93a85f94 [MachineOutliner] Move hasAddressTaken check to MachineOutl [...] adds d7757c7a67c [hwasan] An LLVM flag to disable stack tag randomization. adds 66a7ae17e9c XFAIL a test on Darwin, line-table stuck on DWARF 2 adds 0a340bfcc9d [X86] Add DAG combine to promote vXi1 result of a vXi8/vXi1 [...] adds 9556f0b8410 X86 Tests: add more pamddwd cases. NFC adds 5f1c93f53ac [X86][MMX] Add test for MMX zero folding adds 72f9c7b2933 [InstSimplify] fold implied null ptr check (PR35790) adds 2fffa91251f [X86] Regenerate double shift tests adds da7456a5e45 X86: Add pattern matching for PMADDWD adds 5f72017a8b7 [X86] Add an avx512bw command line to the avx512-vec-cmp.ll [...] adds cf6e4313b83 [X86] Improve legalization of vXi16/vXi8 selects. adds 30e8c8a377a [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode. adds 920e52f67ec [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when inpu [...] adds 17f2d728b2f [InstSimplify] fix code comments; NFC adds 5c84e9e5c08 [x86] auto-generate complete checks; NFC adds 58c11102cf3 [X86][SSE] Add v2f64 3u shuffle test adds f59d7a558d1 [X86][SSE] Support combining MOVLHPS undef inputs adds 2de4f410fbd [X86] Regenerate fp128 test adds 404cc916198 [X86] Autoupgrade kunpck intrinsics using vector operations [...] adds f74f1f199d5 [X86][SSE] Add PR22391 test case adds c75126d5b18 [X86] Add test cases for D41794. adds 73e8cb2d417 [X86][SSE] Tag PR21137 test case adds bc98528887c [GlobalISel][Legalizer] Convert some typedefs to using. NFC. adds 4b328961226 [BasicAA] Stop crashing when dealing with pointers > 64 bits. adds 311c4d31b96 [NFC] Fix comment to adjust to reality adds f70e21b37d9 [GlobalsAA] Don't let dbg intrinsics affect analysis result adds 72491738573 [X86][AVX512F_512]: Adding full coverage of MC encoding for [...] adds 9bfe6e5ae2d [LV] Don't call recordVectorLoopValueForInductionCast for n [...] adds 6f0bf733f3b Revert "[DAG] Elide overlapping stores" adds c471cfcc0c6 [Support] Remove MemoryBuffer::getNewMemBuffer adds b00ca29732c [X86] Fix missing predicates HasAVX512 Predicates in avx512 [...] adds ee8836d6c02 [AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) fu [...] adds 674d7cbcf56 [X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr. adds f1200274805 Update BTVER2 sched numbers for some AVX instructions (xmm [...] adds 59f7ab69b51 [X86] Add missing predicates for VRNDSCALES{D,S}{m,r} adds 4b7d612a694 Allow function_ref(nullptr) like std::function, since it's [...] adds 3b8332372a3 [SystemZ] Check for legality before doing LOAD AND TEST tr [...] adds e8afc14df40 [WebAssembly] Make WasmObjectWriter's destructor public; NFC adds 94cb0130bcb [docs] Fix mention of GCC frontend adds 844c0ec2bb3 [X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt patt [...] adds df0e58eed1a [AMDGPU] Copy impdefs from pseudo to real instructions adds 68ee79b605b [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors adds b46f02d9e67 [Hexagon] Implement signed and unsigned multiply-high for vectors adds f20c58e01be [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32 adds 64adfe61ed9 [WebAssembly] Update README.txt. adds e11130040b8 [X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCI adds 54db3129fe2 [X86] Generalize some code in LowerBUILD_VECTOR. NFC adds 992efa9c1f9 [X86] Use MVT::getVectorVT instead of EVT::getVectorVT when [...] adds 1c8f7fe3626 [x86] regenerate test checks; NFC adds 5006689534e [docs] Only LLVM IR bitstreams begin with 'BC' adds c8ba1936a69 [x86] regenerate test checks; NFC adds 04df9eb4281 [x86] regenerate test checks; NFC adds c96fe476db6 [x86] add tests to show missed constant shrinking (PR35907); NFC adds 52f615d2707 [X86][SSE] Add custom execution domain fixing for BLENDPD/B [...] adds 4ef75dc2cf7 [X86][MMX] Add support for MMX zero vector creation adds 9ac873f1425 Avoid Wparentheses warning. adds 736b52b86d1 [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop enc [...] adds b43bf79618a [X86] Revisit the fix I made years ago to make 'xchgl %eax, [...] adds 4727bc748a4 [SROA] fix assetion failure adds 41de4a2833e [BPF] Teach DAG2DAG AND elimination about load intrinsics adds 7283ac31b43 [BPF] Mark pseudo insn patterns as isCodeGenOnly adds 3206f3b6c73 [FileCheck] - Fix possible buffer out of bounds access when [...] adds 7b9d2090837 [X86][XSAVE]: Adding full coverage of MC encoding for the X [...] adds 262e25ddf8d Add a value_type to ArrayRef. adds 19988dd44d4 [CodeGen][NFC] Correct case for printSubRegIdx adds 5c1ffd92319 [CodeGen] Remove special case of printing subRegIdx from Ma [...] adds 231176041f8 [DebugInfo] Unify dumping of address ranges adds 62031844425 [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full cover [...] adds f90f5519985 [NFC] fix trivial typos in documents adds 8c341debfd2 [X86][MMX] Improve MMX constant generation adds 18704c2df54 [LiveDebugValues] recognize spilled reg killed in instructi [...] adds c7155838a1b [LiveDebugValues] update kill-after-spill test with target triple adds 8e297952674 [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMX adds 559e93a4dfd [SLP] Fix for PR32164: Improve vectorization of reverse ord [...] adds e628eadf7b4 [GlobalISel][TableGen] Add support for SDNodeXForm adds 1aee848f65f [CodeGen] Skip some instructions that shouldn't affect shri [...] adds 1321836c8a6 [PPC] Add a new register XER aliased to CARRY adds 08bbfe4e7a1 [ExecutionEngine] Rename JITSymbol::isStrongDefinition to i [...] adds 71d9d3df401 Specify inline for isWhitespace in CommandLine.cpp adds b0f73c4ac3c [X86][BTVER2] Use instrs instead of instregex for single us [...] adds 0f90c00f8f2 [X86][BTVER2] Use instrs instead of instregex for low match [...] adds cbd51085102 [CallSiteSplitting] Pass list of (BB, Conditions) pairs to [...] adds c270fd4c0fb [X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructions adds 0c4657388e9 [hwasan] Rename sized load/store callbacks to be consistent [...] adds 7e2c299573f Fix pretty printing the unspecified param of a variadic function adds ae04debe25b Fix build error - 'default label in switch which covers all [...] adds 4d5aa75efba [Support] Return an enum instead of an unsigned; NFC. adds 411826c8b7c [pdbutil] Replace 0 byte PDB input with correct version to [...] adds 8a3613ae142 [X86] Remove duplicate lines from scheduler models. NFC adds fb421b00e67 [X86] In LowerBUILD_VECTOR, rename ExtVT to EltVT so it mak [...] adds a470b46d806 [MC] Fix -stack-size-section on ARM adds f3c589a0352 Allow usage of X86-prefixes as separate instrs. Differentia [...] adds a4cc0e368c8 [ThinLTO] - Remove code duplication. NFC. adds ff1be352937 [X86][AVX] Add extra 'interleaved+lanepermute' shuffle test adds 5c66ee588ad [SCEV] fix typo adds 4d639a09201 Rewrite debugger tuning test case to not depend on apple sections adds 8cfd67e0a72 Don't emit apple accelerator tables on non-darwin targets adds 5cba328f5a3 [NFC] fix trivial typos in comments adds 849f39db173 [X86] Constify DebugLoc parameters. No functionality change. adds 538e75cb32e [X86] Don't mutate shuffle arguments after early-out for AVX512 adds 6adafb6098c [Transforms] Support making mutable versions of new-format [...] adds fb7e70c44e2 [ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNC adds 351eabaab70 [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands adds a520636d371 [AMDGPU] add LDS f32 intrinsics adds 6d1111277e3 [ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR adds 0e62a1a1e76 [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.n [...] adds 3d5f5fc6b15 [InstCombine] add test to show hole in demanded bits; NFC adds 9d923086dec [InstCombine] fix demanded-bits propagation for zext/trunc adds 0c6c2732e56 [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian adds c03ed175328 [ARM GlobalISel] Add instselect tests for G_FPEXT and G_FPTRUNC adds 8dfab7e453f [ARM GlobalISel] Rename local variable. NFC adds 13467f82dc9 Add tests for ConstantFoldTerminator preserving DomTree adds e1a3fe1fdba AMDGPU: Error in SIAnnotateControlFlow instead of assert adds 88add379549 [SystemZ] Handle BRCTH branches correctly in SystemZLongBr [...] adds 4ac94a7d394 [ARC] Add missing condition codes. adds b2367d131df Fix MSVC "not all control paths return a value" warning. adds 4379bc4ba12 [PowerPC] Add handling for ColdCC calling convention and a [...] adds e14d8114801 [X86][SSE] Add v4i16 PMULLD tests adds 42c5a95af4e [X86] When legalizing (v64i1 select i8, v64i1, v64i1) make [...] adds 37c809b9801 [utils] Make .cfi_startproc optional for powerpc adds 28ab04cec0d [X86] Teach LowerBUILD_VECTOR to recognize pair-wise splats [...] adds 97bd3fcc117 [InstCombine] add baseline tests for D39958; NFC adds ec7462a4a4c [X86][BTVER2] Reduce instregex usage (PR35955) adds 9bc0b1080f1 [Attributes] Fix crash when attempting to remove alignment [...] adds 88fd7e98fc5 [ARM] Optimize {s,u}{add,sub}.with.overflow. adds 47c91393e11 [ARM] Optimize {s,u}mul.with.overflow. adds 86a8744d381 Use a got to access a hidden weak undefined on MachO. adds eb7fd730fae [WebAssembly] Remove debug names from symbol table adds 7c831c8c4ac [GISel] Make constrainSelectedInstRegOperands() available t [...] adds ec5a93629f9 [MDA] Use common code instead of reimplementing same. [NFC] adds bbb2a7afcc2 Revert [PowerPC] This reverts commit rL322721 adds 6459a2d3270 [globalisel][tablegen] Honour priority order within nested [...] adds 5e26fb04486 [SCEV] Fix typo. NFC. adds c505b213ee3 [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization. adds cedeeaab1eb [X86][MMX] Add PR35982 test cases adds fd335155cc6 Add a ProfileCount class to represent entry counts. adds 4101985b71b Add support for emitting libcalls for x86_fp80 -> fp128 and [...] adds 45915dee3d7 Add a TargetOption to enable/disable GlobalISel adds f368028af49 [hwasan] LLVM-level flags for linux kernel-compatible hwasa [...] adds d3309408027 [LangRef] Clarify Varargs forwarding for musttail calls. adds daef2dedfff [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and [...] adds 8f190bf023e [MachineOutliner] Add DISubprograms to outlined functions. adds 3b5a174ad0f Fix the failure caused by r322773 adds d1bf46631c6 [WebAssembly] Remove duplicated RTLIB names adds 3df0e396727 GlobalISel: Make MachineCSE runnable in the middle of the G [...] adds 7e523c1287d Make GlobalValues with non-default visibilility dso_local. adds 2871d3aefed [DAGCombiner] Add a DAG combine to turn a splat build_vecto [...] adds f3275a04adc Don't drop dso_local in LTO. adds 4da3aa07400 [X86] Remove windows line endings from a test file. NFC adds f0244a364ab Revert "Add a value_type to ArrayRef." adds 67a8b9b97bf [X86] Remove isel patterns for using unmasked vmovdqa32/vmo [...] adds 36049c5e9c8 [X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector s [...] adds 41fd5a1d52d [SelectionDAG] Convert assert to condtion adds b983f38ced4 [RISCV][NFC] Add nounwind to functions in div.ll and mul.ll adds b43fe4d6c76 A new test to demostrate the current SHLD/SHRD code generation. adds be058281ec7 [ADT] Split optional to only include copy mechanics and dto [...] adds ff5fe575250 [RISCV] Implement frame pointer elimination adds eac9f8788fc [RISCV] Codegen support for the standard RV32M instruction [...] adds d9789a6dfb7 test commit adds 4b18f5e93c7 [X86] Add PR35918 test case adds 07b6bcc2857 [HWAsan] Fix uninitialized variable. adds 23b4612e315 [CodeGen][NFC] Refactor MachineInstr::print adds a317810bb4f [docs] Make ReleaseProcess.rst 80 column. NFCI adds f78b1b74e8a [MachineOutliner] Fix r322788 - don't write to working directory adds b5501c956e5 [TargetLowering] add punctuation for readability; NFC adds 884543269e4 [ADT] Add a workaround for GCC miscompiling the trivially c [...] adds 933d1a7b933 [ADT] Just give up on GCC, I can't fix this. adds fb4e566d08a [SLP] Fix test checks, NFC. adds 96ed12f5f36 [CodeGen] Print RegClasses on MI in verbose mode adds 7bee1ceb03a [CodeGen][NFC] Rename IsVerbose to IsStandalone in Machine*::print adds c8ec2e99bb1 Speed up iteration of CodeView record streams. adds cd579cf70b0 [X86][AVX] Add 256/512-bit slow PMULLD tests adds 24f3a274df1 Add a -no-libcxxabi option to the test-release.sh script. adds ab7e40f5e24 [RISCV] Fixed setting predicates for compressed instructions. adds ab816743d04 [X86][SSE] Regenerate vector promotion tests adds 787c92d41ef [AArch64][GlobalISel] Add isel support for global values in [...] adds d05a0b8641b Follow-up to rL322875 by initializing the do_libcxxabi vari [...] adds cee6e0a2c1e we have now https support for apt.llvm.org. Updating the URL adds dca3ef156ea [DWARFv5] Number the line-table's directory array correctly. adds c01e81835c7 Support: Add missing #include. adds 98a9acb5a0c [test] Actually check the common parts in CodeGen/ARM/globa [...] adds 31e026c6188 Typo fix SIBABRT -> SIGABRT. adds 1e426c2a34d AMDGPU/SI: Add d16 support for image intrinsics. adds 1ef4dbfc0f0 [CodeView] Sink complex inline functions to .cpp file, NFC adds cbd60f7c94b [CodeView] Add line numbers for inlined call sites adds 8691a358b03 AMDGPU/SI: Fix typos in d16 support patch the buffer intrinsics. adds 807369220f1 [InstSimplify] regenerate checks and add tests for commutes; NFC adds 8677133ebc5 [X86] Add intrinsic support for the RDPID instruction adds 7a680c0d7cf [ORC] Redesign the JITSymbolResolver interface to support b [...] adds 84238b38546 [ORC] Revert r322913 while I investigate an ASan failure. adds f2f8ac2bd79 [WebAssembly] Add test expectations for gcc C++ tests (gcc/ [...] adds 93b966c2e9c AArch64: Omit callframe setup/destroy when not necessary adds 5d9e10f4430 AArch64: Fix emergency spillslot being out of reach for lar [...] adds fb72d026be0 Revert [CGP] Re-enable Select in complex addressing mode adds 3d7e4a4b98b [X86] Make better use of instregex for cmovcc/setcc/jcc ins [...] adds 10c6c76ce2d Move tests to the correct place adds 9334f5c86b8 Split TailDuplicatePass into pre- and post-RA variant; NFC adds 09008367fca Split MachineLICM into EarlyMachineLICM and MachineLICM; NFC adds 9fcafd067a8 [InstCombine] Make foldSelectOpOp able to handle two-operan [...] adds b3ba8e9df4c [ModRefInfo] Return NoModRef for Must and NoModRef. adds c99a2c432fc [ValueLattice] Use getters instead of direct accesses (NFC). adds 1cc0555256f [NFC] fix trivial typos in comments adds e97eca6f699 [CodeGen] Unify printing format of debug-location in both M [...] adds ce6a5c92b75 [X86] Regenerate RDPMC intrinsic test adds 674fbfa7633 [X86] Add RDPID schedule test adds 72407162894 [X86] Add KNL target to slow PMULLD tests adds 98b3f4e791c Fix line endings. NFCI. adds bfe367d1e2a [AMDGPU][MC] Corrected parsing of image modifiers and encod [...] adds 2975ccf2e03 [Support] - Check nullptr after allocation with malloc in M [...] adds 0d23c0467f2 [SLP] Fix vectorization for tree with trunc to minimum requ [...] adds cc8b87e0806 [X86][AVX] Add more variable permute tests for source vecto [...] adds b2debb2fad4 [AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions adds d5dd5d3520d [X86] Extend load-op-store fusion merge to ADC/SBB. adds b1b5a889fa3 [InstSimplify] use m_Specific and commutative matcher to re [...] adds 4956f498478 [x86] shrink 'and' immediate values by setting the high bit [...] adds 9b8cffe9a68 Test commit adds 1256d61e28a [cmake] Fix typo in LLVM_UTILS_INSTALL_DIR definition. adds 13149c89f35 [x86] regenerate complete checks; NFC adds 9e17395714e [x86] add RUN line and auto-generate checks adds 757e87a197d Fallback option for colorized output when terminfo isn't available adds afa2e7e6a69 Remove alignment argument from memcpy/memmove/memset in fav [...] adds cee475a4d74 [WebAssembly] Make sign-extension opcodes a distinct feature. adds f445ab028c8 Fix docs build break caused by r322965 adds 4f82436e1dd Additional fixes for docs in addition to r322968. adds 667e26447a8 [WebAssembly] Fix libcall signature lookup adds 1f504230b98 [ARM] Fix perf regression in compare optimization. adds 5dc05a9e894 [cmake] Include LLVM_LIBXML2_ENABLED in LLVMConfig.cmake, PR36006 adds b1c9d37e541 [X86][SSE] Add SSE2 gather tests adds 3fb85bc80de [WebAssembly] MC: Start table at offset 1 rather than 0 adds a565e7db88d [SystemZ] Run branch-12.ll test only if long tests enabled adds f937aee1784 [SelectionDAG] Teach computeKnownBits about ATOMIC_CMP_SWAP [...] adds 1166428e09e [SystemZ] Implement computeKnownBitsForTargetNode adds e762c03a671 [SystemZ] Rework IPM sequence generation adds ff28671f85a [SystemZ] Directly use CC result of compare-and-swap adds 8466b57b535 [SystemZ] Prefer LOCHI over generating IPM sequences adds fa14209a6c1 Add optional DICompileUnit to DIBuilder + make outliner deb [...] adds b552ffa8123 [Dominators] Visit affected node candidates found at differ [...] adds 6c4e0e3baf3 [X86] Autogenerate complete checks on a couple tests. NFC adds 156b994bcec [ORC] Re-apply r322913 with a fix for a read-after-free error. adds 250016404b2 [x86] add tests for sqrt estimate that should respect denor [...] adds 598fd0131bc Fix -Wunused-variable. adds 4c73606e33b [AArch64] Add ARMv8.2-A FP16 scalar intrinsics adds 9b103df21bb [ObjCARC] Do not turn a call to @objc_autoreleaseReturnValu [...] adds 889833f36e1 [WebAssembly] Fix MSVC build adds 2f472871bc1 [X86] Add support for passing 'prefer-vector-width' functio [...] adds 8bb1297fe01 [X86] Teach X86 codegen to use vector width preference to a [...] adds 860652c3f8c CodeGen: handle llvm.used properly for COFF adds d6398c64e4a test: move ARM test from x86 adds 7cc04d977ce test: fix ARM tests harder adds 54aeb345ddc [X86] Add test cases for failures to use movzx due to vario [...] adds 7987a0b910f [X86] Add some more v32i1 shuffle tests with shuffles betwe [...] adds 6d979aef2dd [Dominators] Fix some edge cases for PostDomTree updating adds 9188313527c [COFF] Keep the underscore on exported decorated stdcall fu [...] adds e64dbcb7afb [SelectionDAG] Fix codegen of vector stores with non byte-s [...] adds 58ea0e72d4f [InstCombine] add baseline tests for (X << Y) / X -> 1 << Y; NFC adds 9ed46d5b975 Move new test from Generic to SystemZ. adds f91a0727458 [X86][SSE] Check for out of bounds PEXTR/PINSR indices duri [...] adds 10fbe29b938 [X86] Add an override of targetShrinkDemandedConstant to li [...] adds 2d05f76ffa9 [ValueLattice] Use union to shave off ptr size bytes from e [...] adds 18789ab5c48 [cmake] Don't build Native llvm-config when cross compiling [...] adds 7f165c8ada2 [DSE] Minor rename for clarity sake [NFC] adds 840901cb394 [DSE] Factor out common code [NFC] adds e85f69d55b3 [ORC] Cleanup. NFC. adds 4f0f375320d [Dominators] Remove misleading double-deletion test adds 11d16601805 [ORC] More cleanup. NFC. adds c69d5ffd14a [ORC] Add a lookupFlags method to VSO. adds 7ec5710f328 [ThinLTO] Implement summary visualizer adds cd23c8a6f43 An attempt to fix buildbot after rL323062 adds 93150c76d7e Temporarily revert r323062 to investigate buildbot failures adds 424be7676e9 [InstSimplify] add baseline tests for (X << Y) % X -> 0; NFC adds 00352310aa6 [InstCombine] (X << Y) / X -> 1 << Y adds e0267674fdb [ORC] Add orc::SymbolResolver, a Orc/Legacy API interop hea [...] adds 25f98100596 [NFC] fix trivial typos in comments adds 7494874c5b8 [SCEV] Fix isLoopEntryGuardedByCond usage adds cecc5a23281 Revert [SCEV] Fix isLoopEntryGuardedByCond usage adds 3290f994704 [BinaryFormat] Add .debug_names support adds ef279188ca9 Separate ExecutionDepsFix into 4 parts: 1. ReachingDefsAnal [...] adds f2a8b010a3f ExecutionDepsFix refactoring: - Remove unneeded includes an [...] adds 7dc5e8539c0 ExecutionDepsFix refactoring: - Changing DenseMap<MBB*, Liv [...] adds 982e8803a80 ExecutionDepsFix refactoring: - Changing LiveRegs to be a vector adds 8957ed6f205 ExecutionDepsFix refactoring: - Removing LiveRegs adds c77727aa829 ExecutionDepsFix refactoring: - Moving comments to class de [...] adds 95ade18a36d ExecutionDepsFix refactoring: - clang-format adds d6bf9cdf270 Rename ExecutionDepsFix files to ExecutionDomainFix adds be6cfa95858 Separate LoopTraversal, ReachingDefAnalysis and BreakFalseD [...] adds 5e110fb917b Break false dependencies for POPCNT, LZCNT, TZCNT adds 93cf9f7e719 [YAML] Plain scalars can not begin with most indicators. adds a9d988a1d42 [AArch64][SVE] Asm: Predicate patterns adds 7e9a1c6fb40 [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding [...] adds 3bd60530e34 [X86][AVX] Add test case for PR34370 adds efadeb465ef Rename DwarfAcceleratorTable to AppleAcceleratorTable. NFC adds 66bd7d7663a Fixing warnings caused by commit 323095 adds 731becc9105 [ThinLTO] Re-commit of dot dumper after test fix adds 95a5df84b6c [AArch64] optimise v4f16 fcmps to utilise vector instructions adds 971d988a6dd [AArch64][SVE] Asm: PTRUE and PTRUES instructions adds f3c5f2b5431 Fix bug in commit 323096 exposed by test in test-suite-veri [...] adds 9052f33934d [SystemZ] Fix bootstrap failure due to invalid DAG loop adds d9fb399f430 [mips] add warnings for using dsp and msa flags with inappr [...] adds a7bc888f48d [Dockerfiles] Use a newer version of ninja when building in [...] adds 7193f5e4f09 [CodeGen] Shrink MachineOperand by 8 bytes on Windows adds 49ee2f20548 [ARM] Cleanup part of ARMBaseInstrInfo::optimizeCompareInst [...] adds 7bbe32b5341 [AArch64] Create a separate feature set for Exynos M3 adds ca19eaabd75 asan: allow inline instrumentation for the kernel adds c127e0c9742 [llvm-objcopy] Use physical instead of virtual address when [...] adds fb6bc12a56f [AMDGPU] SI Load Store Optimizer: When merging with offset, [...] adds fd5a8723ce9 Introduce the "retpoline" x86 mitigation technique for vari [...] adds 3183187fd5b Revert r322595: Specify inline for isWhitespace in CommandLine.cpp adds 5d85c66118c [WebAssembly] Store function index rather than table index [...] adds 0ac8747929f NewPM: Add an extension point for the start of the pipeline. adds fc933f332cc [X86] Various vXi1 insertion improvements. adds 30a2bf5c68b [X86] Remove 'NOREX' comment from the printing of _NOREX in [...] adds 34edacbdd61 [X86] Don't reorder (srl (and X, C1), C2) if (and X, C1) ca [...] adds c0d997dcdfa [NFC] fix trivial typos in comments adds 95461910b81 update_mir_test_checks: Improve the check for LLVM IR in MIR files adds a375f9297d0 [InstSimplify] (X << Y) % X -> 0 adds cde404af391 This change add's optimization remark in LoopVersioning LICM pass. adds 76abbaff702 [mips] Properly select abs and sqrt instructions adds 3c68a979876 [Analysis] Disable exp/exp2/pow finite lib calls on Android [...] adds 32eb83ac880 [X86][SSE] LowerBUILD_VECTORAsVariablePermute - fix PSHUFB [...] adds 93d01ce52a5 [CGP] Fix the GV handling in complex addressing mode adds f864e512def llvm-objdump: prevent out of bounds accesses during unwind [...] adds f50f6edbe04 [X86] Add missing MOVSX/MOVZX instructions to load folding tables. adds 60a0ef023c2 [X86] Legalize v32i1 without BWI via splitting to v16i1 rat [...] adds f6fa06bcb82 AArch64: get type from correct result when forming BFI/BFM adds e17aaf826b9 AArch64: get type from correct result when forming BFX adds 088d7796ed1 [X86][SSE] LowerBUILD_VECTORAsVariablePermute - ensure that [...] adds 3d96cf80b81 Use EVT::changeVectorElementTypeToInteger() to convert inde [...] adds 09ce1bd00f0 [x86] Mostly reautogenerate a bunch of tests that affect D3 [...] adds 1423fd89fd5 [X86][SSE] LowerBUILD_VECTORAsVariablePermute - ensure that [...] adds e558b6ee997 [X86] Rewrite vXi1 element insertion by using a vXi1 scalar [...] adds 73f6582e917 CodeGen: Fix assertion in ScheduleDAGMILive::scheduleMI due [...] adds 90f5ff4016b [x86] Reautogenerate a bunch of tests for D42287. NFC adds 1ac5a3d2791 Verifier: fix bug treating debug info issue as non-debug in [...] adds 64b37973fba [WebAssembly] Switch to *-wasm as the default target triple. adds ecb7ca8228e [WebAssembly] Add mem.* intrinsics. adds fe48225d2a6 [X86][SSE] LowerBUILD_VECTORAsVariablePermute - extract sub [...] adds 7347a656755 [Hexagon] Implement basic vector operations on vectors vNi1 adds e6dd7b2ff46 [Hexagon] Fix unused variable warning in release build adds 4fcde573baa [WebAssembly] Remove "name" section of object wasm object files adds 78b36298513 Introduce errorToBool() helper and use it. adds 74811c0a781 [Hexagon] Implement hasLoadFromStackSlot and hasStoreToStackSlot adds 22a87532ffa X86 Tests: Add AVX512BW config to CodeGenPrepare test. NFC adds eac7ece1f74 [SLP] Fix for PR32086: Count InsertElementInstr of the same [...] adds aa212ffb28d Add a utility to reduce GlobalISel tests adds 19bf288e654 [Hexagon] Add patterns for sext_inreg of HVX vector types adds 67a08f23310 Revert "[SLP] Fix for PR32086: Count InsertElementInstr of [...] adds bfc9a5a17e8 docs: Remove reference to a deprecated flag adds 48c582c9ac0 [Debugify] Add a mode to opt to enable faster testing adds b06a0ab6c38 Fix MSVC "result of 32-bit shift implicitly converted to 64 [...] adds 8d5a764aadb [safestack] Inline safestack pointer access when possible. adds 1e1ff854ff4 [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support [...] adds 3c94d120f95 [X86] Move 'Int_' to the end of the name of the VCOMISS/VUC [...] adds 79a01aab604 [X86] Remove 'Int_' from instregexs in Zen scheduler model. adds 9ddf1ec1345 [X86] Merge some regular expressions in Zen scheduler model [...] adds cc796b344dd Regenerate shuffle sink test. NFCI. adds c05d316517c Regenerate select test. NFCI. adds 22b25645810 [llvm-extract] Support extracting basic blocks adds 29416d6d5bb Add bdver shuffle sink tests. adds bf4a8b9bd62 [SLPVectorizer] add test for PR13837; NFC adds 04b580d0637 [PPC] Avoid incorrect fp-i128-fp lowering. adds 9f9675607aa BlockExtractor: Remove unused variable. NFC. adds ab3fff6daed [WebAssembly] Add to test expectations for test/MC/WebAssem [...] adds 77c05dd512c Add missing include to fix the failure caused by r323266 adds 7db4b1729a7 [WebAssembly] MC: Use inline triple in test bitcode files adds eb9d9e319bd [TblGen] Inline an (almost) trivial accessor. No functional [...] adds ed48d8b95fa [TableGen] Optimize the regex search. adds a86bbf6148f [llvm-readobj] Fix double 0x prefix in RVA table printing a [...] adds 3cbe6ce128f AArch64: Cyclone: Remove SlowMisaligned128Store tuning flag adds 9a49b21c24b [WebAssembly] Add minor helper functions to WasmObjectFile adds 2ad4fe5e46b [GISel]: Remove redundant copies at the end of ISel adds 8de5923f1f7 X86: Update isVectorShiftByScalarCheap with cases covered b [...] adds b395ea0a2c5 Remove set but unused variable IsUndef. adds 9f5cce814b7 Don't assume a null GV is local for ELF and MachO. adds a48e1dac6f0 [Dominators] Introduce DomTree verification levels adds 206dbdc5056 [X86] Use ISD::SIGN_EXTEND instead of X86ISD::VSEXT for mas [...] adds a30b26ccde9 [NFC] fix trivial typos in comments adds e12ac269310 [X86] Remove redundant regular expression from the Znver1 s [...] adds 28fc37f2441 [X86] Rename 256-bit VFRCZ instructions to have the Y befor [...] adds c3bbd2f972a [X86] Move 'Y' to correct place in FMA4 regular expression [...] adds 37b4a05821c [GlobalMerge] Don't merge dllexport globals adds 34715e9f75e [ARM] Call __chkstk for dynamic stack allocation in all win [...] adds 11a2ca6eea8 [NFC] Remove overconfident assert from IRCE adds e8a15e2fd6a [Doc] Guideline on adding exception handling support for a target adds d1c00f71096 [DAGCombiner] Bail out if vector size is not a multiple adds 959cee720da [Metadata] Extend 'count' field of DISubrange to take a met [...] adds 20b5be1d099 [llvm-opt-fuzzer] Add couple of popular passes adds 52662527d7e Fixes Sphinx issue ('undefined label') introduced in r32331 [...] adds 5fc96281fc7 Fix typos of occurred and occurrence adds 3c8f2b3adf8 [X86][SSE] Avoid calls to combineX86ShufflesRecursively tha [...] adds 594d89a6144 [InstCombine] Introducing Aggressive Instruction Combine pa [...] adds c407eae5d5d [DebugInfo] Emit DWARF reference for DIVariable 'count' in [...] adds 01a9f28a412 [Hexagon] Remove unused HexagonISD opcodes, NFC adds 0a636a9b7d2 [AArch64] Avoid unnecessary vector byte-swapping in big-endian adds 39319e40650 Reverted 323321. adds e232d7b94aa Regenerate shuffle sink test adds cc3fce39516 X86 Tests: Add more sdiv combine cases. NFC adds 207c75bf19e [ValueTracking] add recursion depth param to matchSelectPattern adds ef0ae3d57ba [dsymutil] Make NonRelocatableStringPool a wrapper around D [...] adds ffaa48bd2f3 [NFC] Make magic number for DJB hash function customizable. adds 2ce5d0b2bca [globalisel] Introduce LegalityQuery to better encapsulate [...] adds f2b2f1fda33 InstSimplify: If divisor element is undef simplify to undef adds eaa7682afb5 Handle R_386_PLT32 in RuntimeDyldELF. adds 0dfab7e362b [Hexagon] Run late copy propagation and dead code eliminati [...] adds d9c395b630d [SLP] Fix for PR32086: Count InsertElementInstr of the same [...] adds cd25118a7fc [ThinLTO] Add call edges' relative block frequency to per-m [...] adds a2bac3d6138 [X86] Remove '(_REV)?' from a bunch of scheduler regular ex [...] adds ca2c6a2a140 [X86] Adjust names of PINSRW/PEXTRW intructions between MMX [...] adds cb6ecd40572 [X86] Fix some inconsistencies in the itineraries and Sched [...] adds e999114a775 [ARM] Expand long shifts for Thumb1 to __aeabi_ calls adds 6ca23fea811 Revert r321751, "StructurizeCFG: Fix broken backedge detection" adds fab3c917935 [AMDGPU] Make sure all super regs of reserved regs are mark [...] adds e2f036e8e9b Fix up and document controlling ccache via CMake options. adds a9daa087388 Revert "[ThinLTO] Add call edges' relative block frequency [...] adds fca705a118d Revert "[SLP] Fix for PR32086: Count InsertElementInstr of [...] adds 54a259915a3 [X86][SSE] Add slow-pmulld attribute (silvermont-style) test adds db41c44eb00 Simplify. NFC. adds 3513754b46f [X86][SSE] Aggressively use PMADDWD for v4i32 multiplies wi [...] adds 542b076346a [GlobalISel] Don't fall back to FastISel. adds 25064a71280 [AArch64][GlobalISel] Fall back during AArch64 isel if we h [...] adds 9aa1beb43aa [globalisel] Fix long lines from r323342 adds 3e7c0ec1ef6 [Hexagon] Replace EmitFunctionEntryCode with a DAG preproce [...] adds 9bf5d53af81 [ORC] Add a LambdaSymbolResolver convenience class and docs [...] adds 363b6eef03b [InstCombine] fix datalayout in test file adds 8001e1bb4ef [TableGen] Add a way of getting the number of generic opcod [...] adds e9651653b47 [GlobalISel] Add a requires: asserts to a test. adds 57dd12eceab [ORC] Add helpers for building orc::SymbolResolvers from le [...] adds 542224fdbbb [GlobalISel][TableGen] Fix the statistics for emitted patters adds 723eb1a922a [GISel]: Implement GlobalISel combiner API. adds 34ecead16e7 [ORC] Try to silence compiler error at http://lab.llvm.org: [...] adds c0c5320d764 [GISel]: Fix modules build by including <cassert> adds faeaa17224a [ORC] Refactor the various lookupFlags methods to return th [...] adds 6ab5bbcc087 Add support for pattern matching MachineInsts. adds bd21ad7c41f [X86] Remove unnecessary '_alt' and '_Int' from scheduler m [...] adds b847a7476a3 [X86] Remove 64/128/256 from MMX/SSE/AVX instruction names [...] adds 6fa3a743355 [X86] Name the MMX phaddd instruction with 3 Ds instead of [...] adds b4cbf181f05 [cmake] Set cmake policy CMP0068 to suppress warnings on OSX adds b60df1c3941 [X86] Expand IMUL/MUL instregexs in Znver1 scheduler to sho [...] adds 4c005bebd42 [X86] Expand IMUL/MUL instregexs in Intel scheduler models. [...] adds 266aad55dfc [IRMover] Add comment and fix test case adds 1d27d9a3c59 [FuzzMutate] Inst deleter doesn't work with PhiNodes adds 2c5d1b3ef69 [GlobalOpt] Emit fragments using field offsets from struct layout adds 760506b8eba [Dwarf] Add dsymutil Atom extensions. NFC adds f83ca8289b6 [LTO] - Get rid of friend 'computeDeadSymbols'. NFC. adds c6483fb8735 Another try to commit 323321 (aggressive instruction combine). adds 579ae6ab25b X86 Tests: Add AVX+XOP config to SDIV combine tests adds 3519396cb09 [X86][SSE] Add tests for vector truncation with unsigned sa [...] adds bfb98438175 Update build_llvm_package.bat adds 5f7f26d78fe [X86][SSE] Add tests for vector truncation with signed saturation adds edd25896b5e [SLP] Fix for PR32086: Count InsertElementInstr of the same [...] adds d80d8d29ed8 Revert "[SLP] Fix for PR32086: Count InsertElementInstr of [...] adds 3011c54029b [InstCombine] add tests for PR35792; NFC adds baba397f01d [InstCombine] narrow masked zexted binops (PR35792) adds 63ac05d7dba Revert "[Hexagon] Replace EmitFunctionEntryCode with a DAG [...] adds 146e3ce1eb4 [X86] Apply clang-format to detectUSatPattern. NFCI. adds 80e5ea7e4f3 [SLP] Fix for PR32086: Count InsertElementInstr of the same [...] adds 1e9dc04b3b5 Give scope_exit helper correct move semantics adds 400b8143bf4 [LTO] - Introduce GlobalResolution::Prevailing flag. adds 211131c1d53 [ADT] Make moving Optional not reset the Optional it moves from. adds 974e2fc5fbf Revert "[SLP] Fix for PR32086: Count InsertElementInstr of [...] adds a59163a1b43 asan: add kernel inline instrumentation test adds ae0c8015e09 [Hexagon] SETEQ and SETNE are valid integer condition codes adds 595b8a58219 Revert "asan: add kernel inline instrumentation test" adds d65af934296 [CMake] Fix Bug Report URL adds bdb305ac14f Re-land "[ThinLTO] Add call edges' relative block frequency [...] adds c06c914ec16 tmp adds f1534d01fc2 Reverting r323463 as it appears to be an accidental commit. [...] adds ab7a41171bc Revert r322132; it appears to be an accidental commit, base [...] adds 8f9cfffb921 [X86] Combine two unnecessarily complicated ifs that had th [...] adds 335ad172691 [X86] Teach Intel syntax InstPrinter to print lock prefixes [...] adds 1b3b337d18c [asan] Fix kernel callback naming in instrumentation module. adds cdd614dc669 [Debug] Add a utility to propagate dbg.value to new PHIs, NFC adds b7162f298a2 [Debug] Add dbg.value intrinsics for PHIs created during LCSSA. adds 9d4d53577fe [AArch64] Enable aggressive FMA on T99 and provide AArch64 [...] adds efb87178ab8 [SyntheticCounts] Rewrite the code using only graph traits. adds 920b6750b93 [DWARFv5] Support DW_FORM_line_strp in llvm-dwarfdump. adds f0c7c0917c4 [llvm-objcopy] Add --add-gnu-debuglink adds 259c18e64e0 Add testcase accidentally left out from r323460. adds ca099d91d2f [llvm-objcopy] Refactor llvm-objcopy to use reader and writ [...] adds 2bcebb6e560 [DWARFv5] Classify all the new forms. NFC. adds 8dd9991a9bc [Debug] LCSSA: Insert dbg.value at the first available inse [...] adds f251ca0c6cc [CodeGen] Ignore private symbols in llvm.used for COFF adds 41dbb453ef5 Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader [...] adds e68d8ccc39c Revert "Reland "[llvm-objcopy] Refactor llvm-objcopy to use [...] adds a9659be5fce Fix buildfailure by making some MIPatternMatchers inline adds 6ea62d72a91 Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader [...] adds 1b9f1faf572 Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader [...] adds e0009989525 Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader [...] adds 807062f0a15 [X86] Fix killed flag handling in X86FixupLea pass adds e6b7506e2ea [CGP] Re-enable Select in complex addressing mode. adds a685d042de1 [X86] Remove some dead code from LowerVSETCC. NFC adds 2013da6abc3 [X86] Remove LowerVSETCC code for handling vXi1 setcc with [...] adds 3857e0da22f [X86] Simplify condition in VSETCC. NFC adds 6206aa4ad55 [X86] Remove unused intrinsic type handling. NFC adds 5e8ab2225ae [X86] Remove code from combineBitcastvxi1 that was needed t [...] adds c615c14b1d9 [SelectionDAG] Replace a std::vector<SDValue> with a SmallVector. adds 836550d5d62 [X86] Remove dead code from LowerBUILD_VECTOR that tried to [...] adds f80c9bf2377 [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary b [...] adds 8040eab5894 [NFC] fix trivial typos in comments and documents adds 3b4e0d39af7 [ARM] Armv8.2-A FP16 code generation (part 1/3) adds 574f0927d02 [X86FixupBWInsts] Prefer positive checks in the test. NFC adds 635c67a6b2c [ARM] Accept a subset of Thumb GPR register class when emit [...] adds 22fd1d34b76 [CallSiteSplitting] Fix infinite loop when recording conditions. adds 0869ae1027e [AMDGPU] fix LDS f32 intrinsics adds 1a619ce7775 [MIR] Add support for addrspace in MIR adds dfd62ce9003 [TableGen][NFC]Remove dead variable. adds 862c071736d [X86] Cleanup SDLoc arguments as mentioned on D42544 adds 1ae3e2029df [AMDGPU][MC] Enabled disassembler for image atomic operations adds 320b80d34b3 [SLP] Fix for PR32086: Count InsertElementInstr of the same [...] adds b382fb28604 [X86][SSE] Add tests for vector truncation with PACKUS styl [...] adds b7085586804 [SLP] Removed the warning about unused variable, NFC. adds 7393afb9640 [AMDGPU][MC] Added support of 64-bit image atomics adds 17d3ed3a32f [DAGCombine] reduceBuildVecToShuffle - ensure EXTRACT_VECTO [...] adds 1a600508c3c [MIPS] Don't crash on unsized extern types with -mgpopt adds c9091f8a066 [AMDGPU][MC] Added validation of image dst/data size (must [...] adds 3455380959f [DAG] Teach findBaseOffset to interpret indexes of indexed [...] adds 7a72b437520 [X86][SSE] Drop PMADDWD in lowerMul adds ccc55d20516 [X86][SSE] Don't colaesce v4i32 extracts adds 61a65ef2ab5 [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support [...] adds 3ae9ebfc0dd [NFC] Remove apostrophe to use 'it' in the possessive form. adds abaf111068d [x86] fix typo in comment; NFC adds cf947acc655 [DWARF] Generate DWARF v5 string offsets tables along with [...] adds d8b5d0f3bc2 [Hexagon] Fix an incorrect assertion in HexagonConstExtenders adds 27030222338 [X86] Add 'rdrnd' feature to silvermont to match recent gcc [...] adds 8e7779351f2 [SelectionDAGISel] Add a debug print before call to Select. [...] adds 94b1fc65470 [X86][AVX512] Add combining support for X86ISD::VTRUNCS adds 51c00ba1de0 [X86] Allow any_extend to be combined with setcc on VLX targets. adds b5e54f84556 [SLP] Test for trunc vectorization, NFC. adds 99509aa7350 [X86] Unbreak the build. adds e4a395e88a7 [Support] Move PrintEscapedString into the library its decl [...] adds fc0863a5ee7 [LivePhysRegs] Preserve pristine regs in blocks with no suc [...] adds 0ce929c5c67 [DWARF] Temporarily removing a test that caused an independ [...] adds 71ff88bf213 [Hexagon] Replace multiple vector extracts with store-load [...] adds b810cf80d55 [Hexagon] Make sure that offset on globals matches alignmen [...] adds 963eda6a531 [DWARF] Temporarily removing test to make buildbots happy w [...] adds 48628130005 [Hexagon] Generate constant splats instead of loads from co [...] adds c4921c173ba Inline variable only used within assert. adds f4d58a052ea [InstCombine] Preserve debug values for eliminable casts adds e0c60de72ec [x86] auto-generate complete checks; NFC adds 6a32c10bad6 [X86] Use vpternlog to implement vector not under AVX512. adds 7bf5988467a update_mir_test_checks: Accept "." in function names adds 472d76161ee [InstrProfiling] Improve compile time when there is no work adds 1b24b74c004 [LangRef] Update out-of-date instrprof names adds 17eda3f4337 [InstrProfiling] Don't exit early when an unused intrinsic [...] adds b6965713827 Revert "[SLP] Removed the warning about unused variable, NFC." adds 1cd5ead0a53 Revert "[SLP] Fix for PR32086: Count InsertElementInstr of [...] adds 1ac46286b4b [GlobalISel][Legalizer] Convert the FP constants to the rig [...] adds 4a62f243f32 [SelectionDAG] Make DAGTypeLegalizer::PromoteSetCCOperands [...] adds 103218aea9d [TargetLowering] Teach TargetLowering::SimplifySetCC to sim [...] adds 52d87c13374 [X86][SSE] Add broadcast from v2i32 memory tests (PR34394) adds 90900faf49b Regenerate test results for and-su.ll . NFC adds e2250f6b02f [X86][SSE] Regenerate fp2int/int2fp tests adds ae2123945b5 Regenrate test results for avx-brcond.ll . NFC adds 7a3392112df Regenrate brcond.ll test results. NFC adds fbcbf6093b4 Regenerate test result for stateppint-vector.ll. NFC. adds eab8a177a4c Regenerate test result for testb-je-fusion.ll. NFC. adds c01d1363ea0 Regenerate test result for vastart-defs-eflags.ll. NFC. adds e2b8d977230 Add IRBuilder API to create memcpy/memmove calls with diffe [...] adds bff47ee6d19 [X86][SSE] Simplify demanded elements from BROADCAST shuffl [...] adds 391a2859dce Regenerate test. NFCI adds c4a39a10792 [X86] Remove X86ISD::PCMPGTM/PCMPEQM and instead just use X [...] adds 6faa377a410 [X86] Use vptestm/vptestnm for comparisons with zero to avo [...] adds 3a32c347ae1 [X86][AVX512] Add avx512dq fp2int/int2fp tests (PR31630) adds e865eb4d0b9 Add triples or specify REQUIRES: default_triple to some tests adds c1520fcd045 [X86] Add test to demonstrate missed opportunity to merge k [...] adds d03876d4e0b [X86] Add patterns for using masked vptestnmd for 256-bit v [...] adds 9e52f9c545e [X86] Remove VPTESTM/VPTESTNM ISD opcodes. Use isel pattern [...] adds 952dbe41bb0 [X86] Fix a crash that can occur in combineExtractVectorElt [...] adds 164d4a1cf6d [Support] Move DJB hash to support. NFC adds fdf79b6770d [InlineCost] Mark functions accessing varargs as not viable. adds d1b456b6d12 [NFC] fix trivial typos in comments and documents adds 674f4d74284 [CVP] Don't Replace incoming values from unreachable blocks [...] adds 175e3ee84d7 [X86] Make foldLogicOfSetCCs work better for vectors pre le [...] adds 426dcef49f8 [ThinLTO] - Stop internalizing and drop non-prevailing symbols. adds ba8a402a70c [AArch64] Generate the CASP instruction for 128-bit cmpxchg adds cf29510f52f [X86FixupBWInsts] Fix miscompilation if sibling sub-registe [...] adds 0757989b8c3 [DebugInfo] Basic .debug_names dumping support adds 657d19d6964 [ARM] FP16Pat and FullFP16Pat patterns. NFC. adds 9c834d348e5 Refactor dwarfdump -apple-names output adds 1b7ed97142e Fix build broken by r323641 adds c2b2c5730c4 [Sparc] Account for bias in stack readjustment adds d52b34fd898 [DebugInfo] Fix fragment offset emission order for symbol l [...] adds af49ca6b29e [AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code adds ca3dd9c4d57 Fix windows test failure caused by r323638 adds 334d2239fad [AMDGPU][MC] Corrected parsing of image opcode modifiers r1 [...] adds 4cd1837737e [NFC] Refactor Apple Accelerator Tables adds 633599ba035 [NFC] Rename DwarfAccelTable and move header. adds a9aab590d53 [dsymutil] Generate Apple accelerator tables adds 104718c7bba [AccelTable] Fix undefined reference adds ba63532a00f [AccelTable] Try making MSVC happy adds 2d5d897622c [SLP] Add a test with extract for PR32086, NFC. adds 3f3f6a12511 [SLP] Fix for PR32086: Count InsertElementInstr of the same [...] adds bedb1391781 Add test case for truncated and promotion to test. NFC adds 36e20e37f1b Add myself to CREDITS.txt adds 0e79832916c [AccelTable] Workaround for MSVC bug adds 41fccf273ee [globalisel] Make LegalizerInfo::LegalizeAction available o [...] adds e62bd4b0270 [DWARF] Recommitting a test reverted in r323560. Moved to x [...] adds 7afb0bfdb5c [X86] Add test case for pr34592 adds 062efb1ba72 [X86] Don't create SHRUNKBLEND when the condition is used b [...] adds f1e44dfc90a Move getPlatformFlags to ELFObjectFileBase and simplify. adds ff75b997f1b [AMDGPU][X86][Mips] Make sure renamable bit not set for res [...] adds 42ffd3b775b [MachineVerifier] Add check that renamable operands aren't [...] adds 89b977367fb Improve testcase. adds 27c28519031 [globalisel][legalizer] Adapt LegalizerInfo to support inte [...] adds acc481d33fb Revert "AArch64: Omit callframe setup/destroy when not necessary" adds c3398249f51 [AArch64] Change the filename of the Exynos M1 scheduling defs adds 11d041a905f [X86] Add test case to ensure testw is generated when optim [...] adds 3b001774363 [CodeGen] Simplify conditional. NFC adds bf6c8a51e40 [globalisel][legalizer] Change identity() to changeTo() to [...] adds f8d1af04894 [X86] Avoid using high register trick for test instruction adds ab9f4325f57 [DWARFv5] Re-enable dumping a line table with no CU. adds ca71b347178 [ARM][GISel] PR35965 Constrain RegClasses of nested instruc [...] adds a833b13610b [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, e [...] adds 2495d26abd3 [JumpThreading][NFC] Rename LoadInst variables adds 56188ef9267 [X86] Add FeaturePOPCNTFalseDeps to skylake server CPU to m [...] adds a58b230718b Stop tracking .debug_line_str in DWARFUnit. NFC. adds 88fdf29ab63 LiveInterval: Print weight in print() function. adds f40a9908bf3 [DSE] add test for PR36129; NFC adds 4aef7d16d7a Fix some regular expressions in llvm-mode.el. adds 7fc7c20e8cb AMDGPU: Allow a SGPR for the conditional KILL operand adds bffe946b917 [X86] Use VMOVDQA64 for aligned vXi32 stores. adds e2a3316ce93 AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td adds 263c46c7a92 [RAFast] Don't dereference MBB::end adds 94ac7599811 [globalisel][legalizer] Fix a fallthrough case in the unitt [...] adds c7224c2649a [SelectionDAG]: Ignore "returned" in the presence of an imp [...] adds 6d276fdd078 [InstSimplify] (X * Y) / Y --> X for relaxed floating-point ops adds 6ceb7d83e65 [utils] De-duplicate utils/update_{llc_,}test_checks.py adds f2e22f98b7b [DWARF] Corrected test committed in r323670 to use llc inst [...] adds c2a5bf91f63 [X86] Auto-generate complete checks. NFC adds 4faefeda45b [ARM GlobalISel] Legalize G_FPTOSI and G_FPTOUI adds 94f2bb562ca [ARM GlobalISel] Map G_FPTOSI and G_FPTOUI adds 1700098d053 [ARM GlobalISel] Add inst selector tests for G_FPTOSI and G_FPTOUI adds 1af76d8ad89 [ARM GlobalISel] Legalize G_SITOFP and G_UITOFP adds 504e5b63a0d [ARM GlobalISel] Map G_SITOFP and G_UITOFP adds 198ca8698ab [ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFP adds 4a8b5148a2e Change simple-register-allocation-read-undef.mir so that it [...] adds 9a9c09a24f5 Spelling mistake in comment. NFCI. adds d556d2669bb Test commit. As per the LLVM Developer Policy under "Obtain [...] adds af8973d6a6a [AccelTable] Move print methods to implementation. NFC adds fcdc4c0273c [XRay] clarify error messages when parsing broken traces adds 771594b9ab0 [DSE] make sure memory is not modified before partial store [...] adds b61aa7b6675 [X86] Add test case for PR32690 adds 36a30fc7c9e Revert "[X86] Avoid using high register trick for test inst [...] adds 3589a0db71d [X86FixupBWInsts] mir-simplify fixup-bw-inst.mir test. NFC. adds 2b9844300c7 [RS4GC] Handle call/invoke instructions as base defining va [...] adds 517ef8d874c [AArch64] Add pipeline model for Exynos M3 adds 863055450d3 [AArch64] Add new target feature to handle cheap as move fo [...] adds 1febf59617e [AArch64] Update test cases for Exynos M3 adds 22339ab797d [X86][AVX512] Add VBMI target shuffle-trunc tests adds 83a78f7584e Add more initializers to quiet a clang warning adds 12b04c98f74 Re-commit : [PowerPC] Add handling for ColdCC calling conve [...] adds 99eac1b767f [mips] Fix incorrect sign extension for fpowi libcall adds 4f30de8d0a6 [AArch64] Add new target feature to fuse address generation [...] adds e7676fec11b CodeGen: support an extension to pass linker options on ELF adds c22557992e3 [DeadArgumentElimination] Preserve llvm.dbg.values's first [...] adds 95db9f18a7a AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. adds 5b32b731155 [AMDGPU] Add options for waitcnt pass debugging; add instr [...] adds 41dfb8c4cc8 [CodeView] Micro-optimizations to speed up type merging. adds 505994887d4 [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debu [...] adds c0e84a438ae [AMDGPU] isRenamable fixes to support copy forwarding adds 23aa7daadd5 [X86][XOP] Update isVectorShiftByScalarCheap with cases cov [...] adds 216bd9526a6 Revert: [Hexagon] Make sure that offset on globals matches [...] adds 9e0fe7588b7 [Hexagon] Handle non-aligned offsets in globals in extender [...] adds 6f0f199f277 [XRay] fix 99th percentile lookups by sorting the array correctly adds d14b8f63313 [DWARF] Recommitting a test that was removed with r323564. [...] adds bc91a48126a [LoopStrengthReduce] add test to show potential macro-fusio [...] adds 34517fa50b8 [TableGen] Make sure !if is evaluated throughout class inhe [...] adds cce60c106a2 [AArch64] Properly handle dllimport of variables when using [...] adds 676b6c0e0ee [GlobalISel] Bail out on calls to dllimported functions adds 2fa8e76d041 [dsymutil] Enable -minimize feature. adds 61c5605f601 Teach ValueMapper to use ODR uniqued types when available adds 45adc55a27c [SLP] Add extra test for extractelement shuffle, NFC. adds fe768b50ad0 [AArch64] Expand testing of zero cycle zeroing adds 23f8193f02e [ThinLTO/gold] Write empty imports even for modules with symbols adds a92b6bb2f6a [LLVM-C] Add Accessors For A Module's Source File Name adds 6e998edf16d Turn two static functions into methods, to simplify calling them. adds 3497821514e [X86] Remove redundant check for hasAVX512 before calling h [...] adds db459e238ae [Hexagon] Handle truncates in polynomial multiply idiom rec [...] adds 7c2d049c5b3 LLParser: add an argument for overriding data layout and do [...] adds ae5d34e5eff [AMDGPU] Clarify ReqdWorkGroupSize and MaxFlatWorkGroupSize [...] adds 0f98f5f2b53 [RDF] Clear the renamable flag when copy propagating reserv [...] adds a0050c286c2 Rename path libpath in .linker-options. adds 90018a5eacf [AMDGPU] Update relocation documentation and elf flag machi [...] adds 5ee8d5edce8 llvm-nm should show a symbol type of T for symbols in the ( [...] adds 77fc888bfe1 docs: wordsmith some of the linker option extension adds d2701eb8a1f [X86] Add more madd reduction tests with wider vectors. adds 0b03560d6c4 Revert r323559 due to EXPENSIVE_CHECKS regression. adds b359cf72b9a LTO: Drop comdats when converting definitions to declarations. adds 6c3c15cc0f9 [WebAssembly] Remove some unused code and tidy logging. NFC. adds 2589f81ceee Mark two tests REQUIRES: x86-registered-backend adds dbea76e0ee1 [ARM] Allow the scheduler to clone a node with glue to avoi [...] adds 6ac1c6ccf1f [PowerPC] Return true in enableMultipleCopyHints(). adds e18fe9a179d [ARM] Armv8.2-A FP16 code generation (part 2/3) adds 02fa2967453 [AggressiveInstCombine] Make TruncCombine class ignore unre [...] adds 32582568475 [SystemZ] Check the bitwidth before calling isInt/isUInt. adds b659d3fca5d Add a regression test for problems caused by D42646 . NFC adds d69d8351ae6 [ARM] Lower lower saturate to 0 and lower saturate to -1 us [...] adds 1eecb87b779 Take into account the cost of local intervals when selectin [...] adds c4f543d2673 [MachineCombiner] Add check for optimal pattern order. adds f135378ec63 Fix build error in r323870 adds d79f6c086b6 [ARM GlobalISel] Modernize LegalizerInfo. NFCI adds c462f69b5fa [InstCombine] reduce code duplication for canEvaluate* func [...] adds 5af811c1218 Fix formatting for r323876. NFC adds 3faecaf800f [DAG] Prevent NodeId pruning of TokenFactors in Instruction [...] adds 75c882ca5fb [InstCombine] add tests to show limit of canEvaluate* ; NFC adds 885cc9ab168 [InstCombine] move related tests into the same file; NFC adds f8faafd0e54 [DWARF] Allow duplication of tails with CFI instructions adds 8ff1aed7d4c [Lint] Upgrade uses of MemoryIntrinic::getAlignment() to ne [...] adds 99a8ae2d400 [Hexagon] Only process bitcasts of vsplats when selecting c [...] adds e1ec36c55a0 [X86] Avoid using high register trick for test instruction adds 734066da24d [Hexagon] Handle BUILD_VECTOR from undef values in buildHvx [...] adds 0fe1fb20ecc [CodeGenPrepare] Improve source and dest alignments of memo [...] adds 430f9f72af0 [llvm-cov] Improvements for summary report generated in HTM [...] adds a0ae1f88fb1 [Analysis] Disable calls to *_finite and other glibc-only f [...] adds b8d2903300c [X86] Generate testl instruction through truncates. adds 58528fe1742 [WebAssembly] MC: Resolve aliases when creating provisional [...] adds bfa1dc6a7ad [WebAssembly] MC: Remove unused code for handling of wasm globals adds 111980697bf [MachineOutliner] Freeze registers in new functions adds 097b607c720 [SeparateConstOffsetFromGEP] Preserve metadata when splitting GEPs adds 45ce427076d AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm. [...] adds e16a4c10b65 AMDGPU: Fold inline offset for loads properly in moveToVALU [...] adds 1698c0e2bfc [GlobalOpt] Fix exponential compile-time with selects. adds 2df7962ff46 [Hexagon] Handle SETCC on vector pairs in lowering adds 8e8c64faa1f [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering adds 2bd04d66a7c [SeparateConstOffsetFromGEP] Fix up addrspace in the AMDGPU test adds f42f82fde05 [Hexagon] Implement HVX codegen for vector shifts adds e4eed790f89 [x86] Make the retpoline thunk insertion a machine function pass. adds 42b2a1d5ed9 [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC adds 1076969bfeb Followup on Proposal to move MIR physical register namespac [...] adds 48c8d1e7632 [llvm-cov] Fix incorrect usage of .precision specifier in f [...] adds b43e1871ddc [X86] Make the type checks in detectAVX512USatPattern more robust adds 6a68ef84785 [AggressiveInstCombine] Fixed TruncCombine class to handle [...] adds 9a2ee25a73b AMDGPU: Fix missing SCC def from s_xor_b64_term adds 0c580ec2a43 Utils: Fix DomTree update for entry block adds 37f3f33c55d Revert "[ARM] Lower lower saturate to 0 and lower saturate [...] adds a405c834e6c DAG: Fix not truncating when promoting bswap/bitreverse adds 3890645def7 [GlobalOpt] Improve common case efficiency of static global [...] adds ea9d3ea6d44 [MC] Fix assembler infinite loop on EH table using LEB padding. adds 194fef4761d [XRay][compiler-rt+llvm] Update XRay register stashing semantics adds ab60b05a472 [LSR] Don't force bases of foldable formulae to the final type. adds 39ab914d9d5 Test commit: Fix a comment. adds 217ad732629 [NFC] 'DWARFv5' -> 'DWARF v5' adds ab1bf91d67a [InstCombine] Allow common type conversions to i8/i16/i32 adds 0d1ee416a9f [ARM] Add support for unpredictable MVN instructions. adds f4bc83c250d [AArch64][NFC] Make all ProcResource definitions include th [...] adds 35768cbbc64 [mips] Include EVA instructions in Std2MicroMips mapping tables adds b13e6ff1af6 Revert commit rL323951 adds 1e23490f9a0 [ARM] FullFP16 LowerReturn Fix adds 56ad0925494 [X86][AVX512DQ] Add DQ var permute 256 tests as requested o [...] adds 309e2d7d196 [X86][SSE] Add PR26491 horizontal add test adds 332d15e981e [SelectionDAG] Fix UpdateChains handling of TokenFactors adds f712d3af436 [DAGCombiner] filter out denorm inputs when calculating sqr [...] adds 7cca90c1c12 [X86] Turn X86ISD::AND nodes that have no flag users back i [...] adds b3022309e53 [X86] Remove custom lowering vXi1 extending loads and trunc [...] adds 96db22698dc [AArch64] auto-generate complete checks; NFC adds bbafe884fcd [AArch64] add tests with sqrt estimate and ieee denorms; NFC adds 1fd44f70ffa [X86][SSE] LowerBUILD_VECTORAsVariablePermute - add support [...] adds e65367bf453 AMDGPU/SI: Adjust the encoding family for D16 buffer instru [...] adds 436fd9a2e34 [GraphTraits] Add support for iterating over children edges. adds c1676d54618 [MachineCopyPropagation] Extend pass to do COPY source forwarding adds 51c934180b9 Remove CallGraphTraits and use equivalent methods in GraphTraits adds 44579f3e811 [AArch64] remove bogus comment; NFC adds a83fdf4fd7e [ADT] Replace sys::MemoryFence with standard atomics. adds 2fd14ed24de [CodeView] Class record member counts should include base c [...] adds 514aed67bfd [GlobalISel] Fix assert failure when legalizing non-power-2 loads. adds 3b21b563edb [DAGCombiner] When folding (insert_subvector undef, (bitcas [...] adds 5ac13ad1101 Coding Standards: Document library layering requirements & [...] adds e0c3a9252db [PowerPC] Tell VSX swap removal that scalar conversions are [...] adds 0b5268af735 [InstCombine] allow multi-use values in canEvaluate* if all [...] adds 1e17f1bf735 [X86][XOP] Add XOP to variable permute tests adds 80eee38bf75 [X86][SSE] Add SSE41 to variable permute tests adds c202cc12698 Fix check-prefixes typo and line endings. adds 661251a34f4 [GlobalISel][Legalizer] Relax a legalization loop detecting [...] adds e30fe5ea768 [X86] Separate the call to LowerVectorAllZeroTest from Emit [...] adds 4de242bbc85 [cfi-verify] Add blame context printing, and improved print [...] adds 23475155aaa Fix broken builds due to mismatched min/max types adds ffc6b4654a7 SplitKit: Fix liveness recomputation in some remat cases. adds 9b3e43b39ec Add missing includes adds cfca1a5f0eb Remove non-modular header containing static utility functions adds 2f5a85e441f [GlobalISel] Constrain the dest reg of IMPLICT_DEF. adds f2316f6e764 Fix debug spelling in ResetMachineFunction pass. adds c51be815517 [AArch64][GlobalISel] Fix old use of % sigil in test. adds 9c84a48b2dc [RISCV] Define getSetCCResultType for setting vector setCC type adds 8683684c3b6 [RISCV] Fix c.addi and c.addi16sp immediate constraints whi [...] adds e2a15d065a0 [X86] Legalize (i64 (bitcast (v64i1 X))) on 32-bit targets [...] adds fb0498b03e8 [X86] Legalize (v64i1 (bitcast (i64 X))) on 32-bit targets [...] adds 10bc2944589 [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-ob [...] adds 04dc2a8af38 [SystemZ] Update test case (NFC) adds 5c0a276d264 [SelectionDAG] Add an assert in getNode() for EXTRACT_VECTOR_ELT. adds 87885d427aa [SelectionDAG] Consider endianness in scalarizeVectorStore(). adds 299f8c346e1 [GlobalOpt] Include padding in debug fragments adds 8c1970134e5 [ARM] fixed some tabs/whitespaces in test. NFC. adds 89df749abf1 [ThinLTO] - Fix for "ThinLTO inlines variables that should [...] adds 16a6b6772cc [LTO] - Simplify. NFC. adds 8f67b73a144 [DWARF v5] Add limited support for dumping .debug_rnglists adds 2af2e6c776c Add missing new files from r324077 adds f89cdbc3663 [Analysis] Support aggregate access types in TBAA adds c315ca49dc8 [X86][SSE] Force double domain for SHUFPD stack folding tests adds 6c6c7ace56d [ThinLTO] - Add comment. NFC. adds a4e44968ac7 Fix type sizes that were causing incorrect string formatting adds 1ae814a8816 Add llc tests for comparison chains. adds a2386c3b261 [AMDGPU] Switch to the new addr space mapping by default adds b02fa517300 Make utils/UpdateTestChecks/common.py Python 2/3 compatible [...] adds d18d42cea9b [X86] Remove checks for FeatureAVX512 from the X86 assembly [...] adds 7a74094f7e3 [InstCombine] add baseline tests for unsigned saturated sub [...] adds aed8e7d4fb5 [AArch64][GlobalISel] Use getRegClassForTypeOnBank() in sel [...] adds af1e2a16bdb [InstCombine] fix typos, formatting; NFC adds de02ec6d5b5 [InstCombine] simplify logic for swapMayExposeCSEOpportunit [...] adds 25b29aac893 Fix typo adds 43f741e3e69 [X86] Add tests for missed opportunities to use ptest for a [...] adds 9175ef395eb [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into Tar [...] adds 8bbebc91854 Partially revert r324124 [X86] Add tests for missed opportu [...] adds 0942ed12811 [X86] Add avx512 command line to ptest.ll to demonstrate th [...] adds 541c833e776 [X86] Pass SDLoc by const reference in a few more places in [...] adds 467e95dae58 [InstCombine] make sure tests are providing coverage for th [...] adds 032ebac6e4f [X86] Prefer to create a ISD::SETCC over X86ISD::PCMPEQ in [...] adds 8f8e0c4845d [InstCombine] Use getDestAlignment in SimplifyMemSet (NFC) adds b13ea4ef636 Fix incorrect usage of std::is_assignable. adds a3fd47f78a1 Fix MSVC signed/unsigned comparison warning. NFCI. adds 4cc68b7d8c5 [RISCV] Update two RISCV codegen tests after rL323991 adds 00abba46451 [InstCombine] Allow common type conversions to i8/i16/i32 adds 6ec36e0d625 [ORC] Rename NullResolver to NullLegacyResolver. adds abcd7c6ab0e Remove unneeded -debug argument from new test adds 128eeec0ca1 [X86] Remove and autoupgrade kand/kandn/kor/kxor/kxnor/knot [...] adds f99af6b7668 [X86][SSE] Don't chain shuffles together in schedule tests adds a0143b72d90 [SelectionDAG] Don't use simple VT in generic shuffle code adds f97f105a582 [MIPS] Regenerate vector tests with update script adds 616c32878e5 [DAGCombiner] When folding fold (sext/zext (and/or/xor (sex [...] adds b8468b438e9 [X86] Remove unused function argument. NFC adds 5a244937201 [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast [...] adds 451a188a25a [LV] Use Demanded Bits and ValueTracking for reduction type [...] adds cb6c95b2024 [TableGen][AsmMatcherEmitter] Fix tied-constraint checking [...] adds d0f9a4c472e [InlineFunction] Set arg attrs even if there only are VarAr [...] adds 5cc819f73b0 [PartialInliner] Update test (NFC). adds 3e2c3b54524 X86 Tests: Add shuffle that can be improved by widening ele [...] adds 2358f7672d3 [X86] Auto-generate full checks. NFC adds 7d069980db3 Re-apply [SCEV] Fix isLoopEntryGuardedByCond usage adds b9b376e42ea [X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp [...] adds 100a6ece373 [X86] Remove unused lambda. NFC adds b60798cc7b8 [SimplifyCFG] Relax restriction for folding unconditional branches adds 0170158e0d9 [NFC] Add tests for PR35743 adds 2dabb842317 [X86] Add isel patterns for selecting masked SUBV_BROADCAST [...] adds f2b55fd78c9 Revert [SimplifyCFG] Relax restriction for folding uncondit [...] adds f4f7821f84b Fix more print format specifiers in debug_rnglists dumping adds a32887991d1 [llvm-opt-fuzzer] Avoid adding incorrect inputs to the fuzz [...] adds 703a63c82fa [CodeGenSchedule][NFC] Always emit ProcResourceUnits. adds 8041c24c953 [PowerPC] Check hot loop exit edge in PPCCTRLoops adds dfc05c7fc8f [AMDGPU][MC] Added validation of d16 and r128 modifiers of [...] adds 8b61abeffdf [llvm-opt-fuzzer] Fix build after rL324225 adds 13db890d328 [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with [...] adds 1af48d71ee3 [Hexagon] Use V6_vmpyih for halfword multiplication adds b46c3d9efb8 [ThinLTO] Convert dead alias to declarations adds 61660661cdf [Hexagon] Don't use garbage mask in HvxSelector::shuffp2 adds 97e9c0be975 [Hexagon] Forgot about HexagonISD::VZERO in selecting const [...] adds 9897784e9a5 BitTracker.h needs a full definition of MachineInstr, so in [...] adds 337461796d0 Revert r323472 "[Debug] Add dbg.value intrinsics for PHIs c [...] adds 42bbfa76e41 [X86] Teach X86DAGToDAGISel::shrinkAndImmediate to preserve [...] adds 6661a9b542a [Hexagon] Memoize instruction positions in BitTracker adds 16748767563 [InstCombine] only allow narrow/wide evaluation of values w [...] adds 2e9c44b034c LTO: Include dso-local bit in ThinLTO cache key. adds 50b49991b4e [InstCombine] add unsigned saturation subtraction canonical [...] adds 73cb5b8a646 [X86] Artificially lower the complexity of the scalar ANDN [...] adds 85db023889f [X86] Teach DAG unfoldMemoryOperand to reconvert CMPs to tests adds 70622fa2540 Add release note on change to memcpy/memmove/memset builtin [...] adds 1df38097f57 [InstCombine] add test corresponding to r324252 (PR36225); NFC adds c849b2e28e6 [DWARF] Regularize dumping strings from line tables. adds 0ff4ca1d0c7 [SimplifyLibCalls] Update from deprecated IRBuilder API for [...] adds 111d6cf1fe3 [SDAG] Legalize all CondCodes by inverting them and/or swap [...] adds 8b37fb9d3fe [InstCombine] don't try to evaluate instructions with >1 us [...] adds 614d9e0b482 [LowerMemIntrinsics] Update uses of deprecated MemIntrinsic [...] adds cf9dda307c7 Fix Windows bots for test from r324270. adds 9d8994460a6 [PEI][NFC] Move StackSize opt-remark code next to -warn-stack code adds c359c50d079 [PEI] Fix failing test caused by r324283 adds 74007202a34 [LoopStrengthReduce, x86] don't add cost for a cmp that wil [...] adds 36db7109260 LTO: Also include dso-local bit for calls in ThinLTO cache key. adds 0c105e21b44 [X86] Relax restrictions on what setcc condition codes can [...] adds 2d3a710d770 [X86] Auto-generate complete checks. NFC adds 41600e64fdc Fix regex from r324279 more better. adds dfa5766c55d [ThinLTO] Remove dead and dropped symbol declarations when [...] adds ffaaef68dba Revert "Don't assume a null GV is local for ELF and MachO." adds 7899db5d080 [RISCV] Add support for %pcrel_lo. adds f7b5a9db658 Update test expectations after reverting PLT change adds 9cdef71294b [WebAssembly] Fix test expectations after r324274 adds e48a32e1953 [DAGCombiner] Pass the original load to ExtendSetCCUses not [...] adds 976af7236d6 ThinLTOBitcodeWriter: Do not include module-level inline as [...] adds dd08ac8392a AMDGPU/MemoryModel: Fix monotonic atomic loads adds b9ffb69d86d [X86] Modify a few tests to not use icmps that are provably false. adds b4e4b30a38a [ThinLTO] fix test failure without x86 backend adds b458d85f09b [MergeICmps] Enable the MergeICmps Pass by default. adds 74c3cb19aa1 Revert "[MergeICmps] Enable the MergeICmps Pass by default." adds 96102045c0f [ARM] Armv8.2-A FP16 code generation (part 3/3) adds ee84001a30d [MergeICmps][NFC] Add more assertions. adds 19cf5bffa2c [ARM][AArch64] Add CSDB speculation barrier instruction adds 1f8ce5a193d [AArch64] Fix spelling of ICH_ELRSR_EL2 system register adds e616200081f Fix unused variable warning in release mode. NFC. adds 63cc6a2391b [DeadArgumentElim] Set pointer to DISubprogram before calli [...] adds 7a14dfdd147 [PowerPC] fix up in rL324229, NFC adds f53fdc23081 [X86][SSE] Add PACKSS support for truncation of clamped values adds bed04b64f4a [MergeICmps] Handle chains with several complex BCE basic blocks. adds e2da79543b4 [AArch64][SVE] Asm: Add AND_ZI instructions and aliases adds e978c0e4111 [AMDGPU] do not generate .AMDGPU.config for amdpal os type adds 6dc4a6eff43 [X86][SSE] Add PACKUS support for truncation of clamped values adds fd9c3b75f9d [Hexagon] Handle lowering of SETCC via setCondCodeAction adds e39f6339854 [Hexagon] Add helper functions to identify single/pair vect [...] adds 70d2ee57961 [Hexagon] Split HVX operations on vector pairs adds 351ef5d8be3 [Hexagon] Remove leftover assert adds 51588a05505 AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALU adds 63783791183 Regenerate vector-urem test. NFCI. adds b2c8f01446f [DAG, X86] Improve Dependency analysis when doing multi-nod [...] adds e79570a513b [ARM] f16 conversions adds 17b6342a4d5 [X86] Auto-generate checks. NFC adds 82c0b7b5985 [InstCombine][ValueTracking] Match non-uniform constant pow [...] adds 01bc4f32c4b [Hexagon] Don't form new-value jumps from floating-point in [...] adds 0c588bfa870 [AMDGPU] removed dead code handling rmw in memory legalizer adds e89505778ed [InlineFunction] Update deprecated use of IRBuilder CreateM [...] adds 35f84d86666 [SLP] Update test checks, NFC. adds 5eede4c237a [Hexagon] Lower concat of more than 2 vectors into build_vector adds 1fb795d68ff [Hexagon] Extract HVX lowering and selection into HVX-speci [...] adds 92a98cdeb44 [DWARFv5] Emit .debug_line_str (in a non-DWO file). adds 0f44c538fb0 [InferAddressSpaces] Update uses of IRBuilder memory intrin [...] adds 1f521e37994 [TargetLowering] use local variables to reduce duplication; NFCI adds 6e27fa2c736 [TargetLowering] use local variable to reduce duplication; NFCI adds 0f6540180d4 [DSE] Upgrade uses of MemoryIntrinic::getAlignment() to new [...] adds 5d3c5707673 [x86] add test to show missed BMI isel; NFC adds eee0a13a174 [AArch64] add test to show sub-optimal isel; NFC adds 35ca32d346a [ORC] Start migrating ORC layers to use the new ORC Core.h APIs. adds a0fdd1603b4 [docs] Add out-of-date warnings to the BuildingAJIT tutorial text. adds 35d2753f256 [x86] add tests to show demanded bits shortcoming; NFC adds 8552f5ed267 [X86] Add test cases that exercise the BSR/BSF optimization [...] adds bd873c23e16 [ORC] Remove some unused lambda captures. adds 7583f3e2412 [ORC] Use explicit constructor calls to fix a builder error [...] adds 4d5131f3a58 Fix a crash when emitting DIEs for variable-length arrays adds 9319f6d8dd7 Add OrcJIT dependency for Kaleidoscope Chapter 9. adds 89348bbca7e Add SelectionDAGDumper support for strict FP nodes adds 3ca48048bef [AArch64] Adjust the cost model for Exynos M3 adds c1d66bad333 [LivePhysRegs] Fix handling of return instructions. adds a5bd54307b1 Place undefined globals in .bss instead of .data adds 04aa65061f7 Add DWARF for discriminated unions adds c8c76d329a8 [DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_un [...] adds 811a2d380fd [LCSSAVerification] Run verification only when asserts are [...] adds 9051a39c8ae AMDGPU: Select BFI patterns with 64-bit ints adds d917ccf0ddb [Mips][AMDGPU] Update test cases to not use vector lt/gt co [...] adds 4fe7c58adf9 [AMDGPU] Suppress redundant waitcnt instrs. adds d083255aa28 GlobalISel: Always check operand types when executing match table adds d3f03a62273 [ThinLTO] Serialize WithGlobalValueDeadStripping index flag [...] adds 9cac4d02e5f Follow-up for r324429: "[LCSSAVerification] Run verificatio [...] adds d595719b5e7 AMDGPU/GlobalISel: Mark 32-bit G_FPTOUI as legal adds 79a0b06f2ea [LegalizeDAG] Truncate condition operand of ISD::SELECT adds e81b912cb6d Xfail the test added in r324445 until the underlying issue [...] adds 59b64490fda [x86/retpoline] Make the external thunk names exactly match [...] adds 40a9bb2b06d [LoopPrediction] Introduce utility function getLatchPredica [...] adds 1cadf878a40 The xfailed test from r324448 passed on one of the bots: re [...] adds 3e91db1b809 [SCEV] Make isLoopEntryGuardedByCond a bit smarter adds e6e1e5227c5 [ThinLTO] - Simplify code in ThinLTOBitcodeWriter. adds 5ccd52a267d [ARM] FP16 mov imm pattern adds b5ecf3cbd69 Revert r324455 "[ThinLTO] - Simplify code in ThinLTOBitcode [...] adds 70d8d9d0ff1 Revert [SCEV] Make isLoopEntryGuardedByCond a bit smarter adds ee43c8204a4 [MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass [...] adds 38f2c0f249c Re-enable "[SCEV] Make isLoopEntryGuardedByCond a bit smarter" adds 97d47c0facf [BinaryFormat] Remove dangling declaration of DiscriminantString adds a6b1e26f19f [mips] Handle 'M' and 'L' operand codes for memory operands adds 75f9b54f1ee [mips] Support 'y' operand code to print exact log2 of the operand adds 1ba4d9a6f34 [Orc] Pacify -pedantic. adds 5065b0d4249 [X86] Regenerate atomic i32 tests adds 87dba15eee7 [dsymutil] Upstream update feature. adds d1e87f618b6 [SLPVectorizer][NFC] Make a loop more readable. adds 3d6da040af9 [dsymutil][test] Check the updated dSYM instead of companion file. adds 634098b2d13 [X86][AVX] Add PACKSSDW/PACKUSDW support for truncation of [...] adds ea06ecf3436 AMDGPU: Remove the s_buffer workaround for GFX9 chips adds 3afd566557f AMDGPU: Add 32-bit constant address space adds a3b503f0223 [DebugInfo] Improvements to representation of enumeration t [...] adds 124213f0abf [SelectionDAG] More Aggressibly prune nodes in AddChains. NFCI. adds 6bac809af91 Revert dsymutil -update commits adds c9525380858 Revert "AMDGPU: Add 32-bit constant address space" adds 00812da33db [X86] Regenerate test using update_mir_test_checks.py. NFC adds f45b60fe2f4 Generate PDB files for profiling even in Release build. adds 3750e6f0a31 [SLP] Add a tests for PR36280, NFC. adds 0b268d60e82 Revert "[DebugInfo] Improvements to representation of enume [...] adds cb2b332d414 [X86] Auto-generate complete checks. NFC adds fb775f9736a [X86] When doing callee save/restore for k-registers make s [...] adds 49ae5eae2d6 [X86] Remove dead code from EmitTest that looked for an i1 [...] adds 4777e1f22bc [X86] Prune some unreachable 'return SDValue()' paths from [...] adds 19265c931f2 Verify profile data confirms large loop trip counts. adds 6e5a6506b1b [x86] Fix nasty bug in the x86 backend that is essentially [...] adds 84f9e041390 [AMDGPU] Fixed wait count reuse adds b712efa9386 [NVPTX] When dying due to a bad address space value, print [...] adds 0bd3aded703 AMDGPU: Don't crash when trying to fold implicit operands adds ba4bd09db24 Fix PR36268. adds 6879e4b17a9 AMDGPU: Fix incorrect reordering when inline asm defines LD [...] adds b07c392c111 gold-plugin: Do not set codegen opt level based on LTO opt level. adds 37962a331c7 bpf: Improve expanding logic in LowerSELECT_CC adds 4892373b324 [DAGCombiner] Rename variable to be slightly better. NFC adds 1176aede920 [DAGCombiner] Avoid creating truncate nodes in (zext (and ( [...] adds 530107fbbbd [CodeGen] Print MachineBasicBlock labels using MIR syntax i [...] adds 3328d973237 ARM: Remove dead code. NFCI. adds d758b76106f [DAGCombiner] Don't create truncate nodes in (aext (zextloa [...] adds f1980331dbe [DAGCombiner] Fix a couple mistakes from r324311 by really [...] adds 62cd19d8ac5 CMAKE: apply -O3 for mingw clang adds 4c64dfea378 [SimplifyCFG] Re-apply Relax restriction for folding uncond [...] adds 97f86a9714e Recommit r324455 "[ThinLTO] - Simplify code in ThinLTOBitco [...] adds 181057ed1fc [X86] Don't emit KTEST instructions unless only the Z flag [...] adds 3b77e6eb3b9 [X86] Allow KORTEST instruction to be used for testing if a [...] adds cf087c19138 [X86] Support folding in a k-register OR when creating KORT [...] adds ca1a7d0e5bd [AArch64] Don't materialize 0 with "fmov h0, .." when FullF [...] adds ee765a1d8f1 [TargetSchedule] Expose sub-units of a ProcResGroup in MCPr [...] adds 80d11db652b [AVR] Fix the testsuite after '%' changed to '$' in MIR adds c61c2f0f83a [mips] Define certain instructions in microMIPS32r3 adds 33f35fbf6fe Revert accidental changes that snuck in r324584 adds 66561603636 [X86] Fix compilation of r324580. adds 91a90a2587c [Loop Predication] Teach LP about reverse loops with uge an [...] adds 61693460a19 Re-land [dsymutil] Upstream update feature adds fad57339219 [X86][MC]: Adding test coverage of MC encoding for several [...] adds aca8af8c384 Add missed PostDominatorTree analysis dependency to GVN hoi [...] adds fd8aee0ade6 [test][dsymutil] Fix tests for Windows bots. adds 8cc62813ce4 [ARM] Fix disassembly of invalid banked register moves adds 03662ff6197 [x86] Add test/CodeGen/X86/vmaskmov-offset.ll. NFC. adds 879372e3661 [InstCombine] Improve mul(x, pow2) -> shl combine for vecto [...] adds 35aa696084a Revert r324600 as it breaks a buildbot adds 78c0953f5cb Fix unused variable warning. adds 75f7e7d6c0d [ARM] Re-commit r324600 with fixed LLVMBuild.txt adds a53fc2e9d86 [InstCombine] Fix issue with X udiv 2^C -> X >> C for non-s [...] adds ce8aaf3706a [ValueTracking] don't crash when assumptions conflict (PR36270) adds a69986c1fab [LoopVectorize] auto-generate complete checks; NFC adds 24f7956b08c [SLPVectorizer] auto-generate complete checks; NFC adds 0a5886c1e09 [InstCombine] Fix issue with X udiv (POW2_C1 << N) for non- [...] adds 306ada1fe00 [SLPVectorizer] move RUN line to top-of-file; NFC adds 6412c3723bd [SLPVectorizer] auto-generate complete checks; NFC adds 86517c4a081 [SLPVectorizer] auto-generate complete checks; NFC adds a43548c0566 [AMDGPU] Updae documentation about address space adds f1567ab48db [dwarfdump] Normalize input path. adds 0648dd9ef80 [dsymutil] Use llvm::sys::path to join bundle path. adds da8116fe7f1 [ARM] Add 'fillValidCPUArchList' to ARM targets adds 3d5f3291985 Fix signed/unsigned compare warning I introduced adds b9a5c1a63b5 [LoopIdiom] Be more aggressive when setting alignment in memcpy adds 0ec6e0c9ee2 [InstCombine] Regenerate vector mul tests. adds 74894cdfee9 Use ranged for loops in TypeFinder.cpp, NFC adds 934bc505b79 [InstCombine] Add vector urem tests. adds 90222ff7984 [X86] Add a few new test cases for shrunkblend combine adds 28a96ee0712 [InstCombine] Add m_Negative pattern matching adds cc227f84d7a Change "UNSUPPORTED: windows" to be "UNSUPPORTED: system-wi [...] adds 267578962dc Simplify function prototypes in bugpoint, NFC adds d3663859cfc [SelectionDAG] Add a helper function for creating a boolean [...] adds a5944e599a6 [InstCombine] Add vector udiv tests adds 7adf52c27ef [InstCombine] visitSRem - use m_Negative(APInt) helper. NFCI. adds 7fa81061c05 [X86] Add shift undef, %X tests adds 3a4a2680cd2 [X86] Add common CHECK prefix to shift combine tests adds 16273d21817 Regenerate test adds 3c8d6c5a04c [MSan] Update uses of IRBuilder::CreateMemCpy to new API (NFC) adds fa797f4d33f Fix missing field initializer warning in TableGen SubtargetEmitter adds 43849be6e44 [X86] Support 'V' register operand modifier adds 2206986770a [X86] Remove kortest intrinsics and replace with native IR. adds deeff3d70bd WIP: [DAGCombiner] Assert that debug info is preserved adds 0f1e6f8445e [bugpoint] Simplify the global initializer reducer, NFC adds 5309a7b3dd5 Revert "WIP: [DAGCombiner] Assert that debug info is preserved" adds 66bf8e614f9 [ASan] Update uses of IRBuilder::CreateMemCpy to new API (NFC) adds 0745d956f99 [DSan] Update uses of memory intrinsic get/setAlignment to [...] adds e5fa4fc4781 Parameterize a test. adds 1d564e0c398 [ThinLTO] Skip BlockAddresses while replacing uses in funct [...] adds f7664e8c6de CMake: Explicitly #undef LLVM_REVISION rather than using a [...] adds e4e4fc4ec23 [X86] Add DAG combine to constant fold a bitcast of a vXi1 [...] adds 1a2742d054e [X86] Improve combineCastedMaskArithmetic to fold (bitcast [...] adds 6a919aa7ac1 [GlobalIsel][X86] Making {G_IMPLICIT_DEF, s128} legal adds cbd9100de9c [GlobalISel][X86] Fixing failures after https://reviews.llv [...] adds 7913bcdcffe AMDGPU: Minor cleanups adds c9ae4f956af AMDGPU: Process SDWA block at a time adds f0574ca6a6c [DWARFv5] Fix dumper to show the file table starts at index 0. adds 7fa9b1fe0e7 Minor tweak to test case. adds 980f103186a Use a stable topological sort in DwarfCompileUnit::createSc [...] adds cde943d9759 [x86] consolidate and add tests for undef binop folds; NFC adds 5c4660bc608 [Lanai] Code model dictates section selection. adds 331b6f31af8 [CodeGen] Move printing '\n' from MachineInstr::print to Ma [...] adds f66532b0601 [CodeGen] Unify the syntax of MBB successors in MIR and -de [...] adds e4de84b6004 [CodeGen] Only print successors when the list is not empty adds 2abdc456cba [CodeGen] Don't compute BranchProbability for MBB::print adds e046923bade [hwasan] Fix kernel instrumentation of stack. adds 6d64e7c26be [x86] Add test cases to demonstrate some dumb mask->gpr->ma [...] adds d7d9e379b55 [CodeGen] Unify the syntax of MBB liveins in MIR and -debug output adds 5aa15f49a29 [GISel]: Verify COPIES involving generic registers. adds 89f42483f9a Make test changes added in r324584 more robust by using a r [...] adds 8c824db15ae [ORC] Remove Layer handles from the layer concept. adds 683b0c59a0c DebugInfo/llvm-symbolizer: Test symbolizing Split DWARF wit [...] adds 33a891ee1f1 [bugpoint] Avoid noisy errors by passing a valid opt to tests adds a1b53a04f19 [bugpoint] Delete a dead cl::opt (-child-output) adds 00088b80667 [bugpoint] Simplify reducers which can fail verification, NFC adds db43c8fed62 [lit] Pass CLANG env var to testing configuration adds 53aca48bc8c [X86] Add 512-bit shuffle test cases for concatenating 128/ [...] adds 5856e092a46 [X86] Teach shuffle lowering to recognize 128/256 bit inser [...] adds c37c34be72e [X86] Simplify some code in lowerV4X128VectorShuffle and lo [...] adds 3940160b8f6 LTO: Include live bit in ThinLTO cache key. adds 2f8f367bc69 [AMDGPU] More descriptive names in the memory legalizer adds 099ec628245 [bugpoint] Report non-existent opt binary adds 5e12a214f69 Rename and move utility function getLatchPredicateForGuard. NFC. adds 562d4e516ab [AArch64] Return true in enableMultipleCopyHints(). adds cfb2d8c3014 [CodeGen] Optimize AccelTable adds f1973366b74 [TargetSchedule] Fix r324582. adds be64cee9b56 [InstCombine] Add constant vector support for X udiv C, whe [...] adds 2e6bdcc7a80 [mips] UnXFAIL gprestore.ll test. adds 32bbb278db0 [ELF] Print the .type assembly directive correctly for STT_NOTYPE adds 1e20442ba75 [SelectionDAG] Provide adequate register class for RegisterSDNode adds 3d785e7419e [DebugInfo] Don't insert DEBUG_VALUE after terminators adds 828c10a9a2b [Hexagon] Express calling conventions via .td file instead [...] adds 9c095c46d42 Remove some unnecessary REQUIRES: shell from a couple of ll [...] adds b23979377ad Pre-emptively fix test case for windows path separators adds 7bac5986e1c [AArch64] Refactor stand alone methods (NFC) adds 33901e33bf2 AMDGPU: Fix layering issue adds 6f2da0b6ad8 Reapply "AMDGPU: Add 32-bit constant address space" adds d64f170e117 Use assembler expressions to lay out the EH LSDA. adds 22b178502a7 Emit smaller exception tables for non-SJLJ mode. adds 77c3498babd AMDGPU: Remove tied operand from si_else adds 8b71a9f090e [InstCombine] Add vector xor tests adds d26fcac7987 [x86] remove duplicate undef tests; NFC adds 6c589fe15aa [ThinLTO] Teach ThinLTO about auto hide symbols adds 396b5314e8e [tablegen] Fixed few !foreach evaluation issues. adds 0fe6d1926c3 Declare PostDominatorTree as a class adds 5d35c6fe4f1 [Hexagon] Add code to select QTRUE and QFALSE adds afa0bdd9d04 [Utils] Salvage debug info from dead 'or' instructions adds a8be8c611e1 [AArch64] Adjust the cost model for Exynos M3 adds 6ccb37f13ab llvm-objdump when printing the Objective-C meta data also p [...] adds e18a2b4e7d7 [CodeGen] Print predecessors as MIR comments in -debug output adds b39f4115762 [WebAssebmly] Report undefined symbols correctly in objdump adds c64f12d301e [CodeGen] Add lifetime markers to the list of meta-instructions. adds 9f2f4847b9e [X86][MC] Fix assembling rip-relative addressing + immediat [...] adds dde42c49229 [AArch64FastISel] Replace deprecated calls to MemoryIntrins [...] adds 3a406d4ae78 [AMDGPUPromoteAlloca] Replace deprecated memory intrinsic A [...] adds 8a584bc952d [WebAssembly] Add an LLVM_FALLTHROUGH to address a warning. NFC. adds 0f32e136587 [WebAssembly] Add mechanisms for specifying an explicit imp [...] adds 10e696774ed CMake: Allow specifying arbitrary CCACHE parameters adds cf46f9ffb97 [ARMFastISel] Replace deprecated calls to MemoryIntrinsic:: [...] adds 810572205c9 [X86] Teach lower1BitVectorShuffle to recognize shuffles th [...] adds 09d56824f57 [llvm-objcopy] Make modifications in-place if output is not [...] adds ba26ff8dcb6 [Hexagon] Update uses of deprecated IRBuilder CreateMemCpy/ [...] adds 757ef7ca81a [LV] Fix analyzeInterleaving when -pass-remarks enabled adds 8666bdacf75 REQUIRES: shell a couple of tests that require the shell adds 6f3ebe2135c Make LLVM timer reprintable: that is, make more than one pr [...] adds 04b113b4bf1 [X86] Teach combineInsertSubvector how to combine some k-re [...] adds e8e03ba1cc1 [DAG] Make early exit hasPredecessorHelper return true. NFCI. adds 19c9b1cc72a [utils] Refactor utils/update_{,llc_}test_checks.py to shar [...] adds c7bf2b1200b [X86] Teach combineExtSetcc to handle ZERO_EXTEND by wideni [...] adds 5e6ffb9ab1d [X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 [...] adds cdd1b4c0292 [X86] Custom legalize (v2i1 (fp_to_uint/fp_to_sint v2f64)) [...] adds 69c5372c4e5 [X86][SSE] Regenerate old sitofp v2i32 test adds f6734f67abb Fix Wdocumentation warnings. NFCI. adds 7262e96fe8c [ARM] preserve test intent by removing undef adds c5d89705992 Fix Wdocumentation warning. NFCI. adds 5cca66c8c71 [x86] preserve test intent by removing undef adds a9fbd05487b [x86] preserve test intent by removing undef adds 16349f2a1f2 [X86] Remove some check-prefixes from avx512-cvt.ll to prep [...] adds bd76e65234a [X86] Extend inputs with elements smaller than i32 to sint_ [...] adds 85960022c45 [X86] Custom legalize (v2i32 (setcc (v2f32))) so that we do [...] adds 15833560a5d [X86][SSE] Increase PMULLD costs to better match hardware adds e44a949ca65 [InstCombine] Add constant vector support for ~(C >> Y) --> [...] adds 53c9481819a [X86][SSE] Add UMIN/UMAX combine test adds 06dc5820cf1 [X86] Change signatures of avx512 packed fp compare intrins [...] adds cd0b6313606 [X86][SSE] Add SMIN/SMAX combine test adds 33e861c4893 [X86] Remove some redundant qualifications from the setOper [...] adds a7d13fbe246 [SelectionDAG] Remove TargetLowering::getConstTrueVal. Use [...] adds fab5e4d91a8 [X86] Remove setOperationAction lines for promoting vXi1 SI [...] adds 35542ad55d8 [X86] Don't make 512-bit vectors legal when preferred vecto [...] adds fa2037abb8f [X86] Reduce Store Forward Block issues in HW adds 8d295d41b32 fix test/CodeGen/X86/fixup-sfb.ll test failure after commit [...] adds 43e7c1ccf9e [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for a [...] adds 6c93e2af214 [X86] Add PR33747 test case adds 3f985a3da1a [TargetLowering] try to create -1 constant operand for math [...] adds e2ff19ed66a [InstCombine] add tests for div-mul folds; NFC adds bafade2e5b9 [X86][SSE] Moved SplitBinaryOpsAndApply earlier so more met [...] adds ff687abc6ec [X86] Use min/max for vector ult/ugt compares if avoids a s [...] adds fab575cbcb0 [InstCombine] X / (X * Y) -> 1 / Y if the multiplication do [...] adds b174e11560c [X86][SSE] Use SplitBinaryOpsAndApply to recognise PSUBUS p [...] adds 84e573c17ac [X86] Update some required-vector-width.ll test cases to no [...] adds 552a6fb7dbc [CodeView] Allow variable names to be as long as the codevi [...] adds c13f8098687 [ThinLTO] Add GraphTraits for FunctionSummaries adds dc4aa4dc554 [X86] Remove LowerBoolVSETCC_AVX512, we get this with a tar [...] adds 1ef1bef7929 [X86] Remove dead code from getMaskNode that looked for a i [...] adds 52664b00717 [X86] Remove MASK_BINOP intrinsic type. NFC adds 22c58837577 Follow on to rL324854 (Added tests) adds 6ab8e7c6e76 [X86] Allow zextload/extload i1->i8 to be folded into instr [...] adds f055c23d11e [X86] Add KADD X86ISD opcode instead of reusing ISD::ADD. adds 634f93ef18f [X86] Autogenerate complete checks. NFC adds e82c0140325 [X86] Change some compare patterns to use loadi8/loadi16/lo [...] adds 042fe30f8f5 [X86] Remove check for X86ISD::AND with no flag users from [...] adds 00884fea345 [X86] Don't look for TEST instruction shrinking opportuniti [...] adds e4f9fdee4b7 [SCEV] Make getPostIncExpr guaranteed to return AddRec adds 0b708765175 [NFC] Fix typos adds a438b617183 [MC] Issue error message when data region is not terminated adds 289fcee6332 [mips] Fix 'l' constraint handling for types smaller than 32 bits adds 4d4c57240a7 [gtest] Support raw_ostream printing functions more compreh [...] adds 78a2fedd78a [CodeGen] Add a -trap-unreachable option for debugging adds dee18271096 [LoopInterchange] Simplify splitInnerLoopHeader logic (NFC). adds 9c8b55d17f3 [mips] Revert rL324869 adds 70675617679 [mips] Fix 'l' constraint handling for types smaller than 32 bits adds ed3f0858d72 Revert r324835 "[X86] Reduce Store Forward Block issues in HW" adds 14498370e4d Test commit: reformat comment adds 0a090c80ad3 [InstCombine] various clean-ups for commonIDivTransforms; NFC adds c01a55434a1 [AArch64] Improve v8.1-A code-gen for atomic load-subtract adds c7432f53e00 [SLP] Take user instructions cost into consideration in ins [...] adds 263d0a1f4b7 [NFC] Fix comment of class InstrStage adds f9670219dbb [X86][MMX] Add missing scheduling class tag for EMMS/FEMMS adds 3c2ea0e03ba [X86] Tag CET-IBT instruction scheduler classes adds 0c69bf465f0 Re-commit r324489: [DebugInfo] Improvements to representati [...] adds 07c6e350bbd [X86][AVX512] Add missing scheduling class tag for VMOVQ/VM [...] adds 0137ee6cae6 [AArch64] Refactor identification of SIMD immediates adds ca78a8c1842 [X86][AVX512] Add missing scheduling class tag for KMOVB/KM [...] adds 4c334a7e90d [AArch64] Improve v8.1-A code-gen for atomic load-and adds 2e8d5c6cc7e [X86] Add missing scheduling class tag for i64 absolute add [...] adds 539d5295114 [AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - llvm portion adds c94f97483f2 [LICM] update BlockColors after splitting predecessors adds dd467c1e78d [InstCombine] various clean-ups for div transforms; NFC adds cfeb4c62eba [InstCombine] regenerate checks; NFC adds a2e33f36d20 [InstCombine] add tests for missing fdiv fold; NFC adds 4ac9cb02bcc [InstCombine] X / (X * Y) --> 1.0 / Y adds 4863252becc [DebugInfo] Unify ChecksumKind and Checksum value in DIFile adds c91f4ccc3d8 Revert "Follow on to rL324854 (Added tests)" as part of r32 [...] adds fc5c4dcc7a0 Revert "[ThinLTO] Add GraphTraits for FunctionSummaries" adds 6e9d6c255ea Move the debuginfo-dce-or test into debuginfo-variables.ll, NFC adds ff17b09f19b Factor out common condition into an easier to understand he [...] adds 792927c7683 Fix the syntax highlighting of strings in dwarfdump. adds 0d2725c460e [GlobalMerge] Allow merging of dllexported variables adds c0afb8925db [X86] Remove unused multiclass argument. NFC adds e985e4a8d3e [X86] Simplify X86DAGToDAGISel::matchBEXTRFromAnd by creati [...] adds 9d75b0c4830 [DAG] make binops with undef operands consistent with IR adds 0d25ba137fc [WebAssembly] Fix casting MCSymbol to MCSymbolWasm on ELF adds 4321cf65af1 [LSR] Avoid UB overflow when examining reuse opportunities adds 3bbbdc333c2 Simplify switch statement (NFC) adds e4043bc2212 [x86] add select test to show there's no single right answe [...] adds 7916c9ef78e [WebAssembly] MC: Remove redundant `private` specifiers adds 05ca387efe9 [X86] Reverse the operand order of the autoupgrade of the k [...] adds 5b0a1fc9c4b [SafeStack] Use updated CreateMemCpy API to set more accura [...] adds ddc563a7638 [WebAssembly] MC: Remove redundant struct types adds 0d1fcacb124 Revert "[LSR] Avoid UB overflow when examining reuse opport [...] adds f28222f31c0 [InstCombine] Simplify MemTransferInst's source and dest al [...] adds a609eb0df37 [InstSimplify] consolidate tests for log-exp inverse folds adds 31b15987901 [Dominators] Always recalculate postdominators when update [...] adds 6fee311f948 [InstSimplify] change tests to 'fast' to reflect current folds adds d3663e64d3e [X86] Auto generate complete checks. NFC adds 8e4ce734496 [WebAssembly] Update ADT/TripleTest.cpp now that default fi [...] adds 860eb48e1fb [InstSimplify] allow exp/log simplifications with only 'rea [...] adds 9fec6c0fd1b GlobalISel: IRTranslate llvm.fmuladd.* intrinsic adds 099f3f878b5 Document the shortcomings of DwarfExpression::addMachineReg(). adds 1ca28946c69 [Utils] Salvage the debug info of DCE'ed 'xor' instructions adds 9c9e1cde863 [Utils] Salvage the debug info of DCE'ed 'sub' instructions adds ca78c752ff7 [Utils] Salvage debug info of DCE'ed shl/lhsr/ashr instructions adds 2bbd73403b7 [Utils] Salvage debug info of DCE'ed mul/sdiv/srem instructions adds 957c7c76d11 Revert "Document the shortcomings of DwarfExpression::addMa [...] adds e533c7947da [X86] Remove duplicate CHECK-LABEL line the update script d [...] adds 5dd5ab3651c [X86] Use getTypeAction in most places that were checking E [...] adds 232b1a899c2 Revert "Rewrite the cached map used for locating the most p [...] adds d6e0db83ad3 [Utils] Salvage debug info from all no-op casts adds 7bdbf6e4d2b [X86] Autogenerate complete checks. NFC adds ebf3d94ea57 [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND wh [...] adds e925ce01161 [X86] Add a blsr test case with a shift from PR35792. NFC adds c6a263bfa2f [X86] Add a test case showing blcic matching being broken b [...] adds 4436334bfc1 [LoopInterchange] Check number of latch successors before a [...] adds bac740f8ef8 [Thumb] Handle addressing mode AddrMode5FP16 adds c8ff25f66e4 [X86] Rename function main->foo in CodeGen/X86/pr35316.ll. NFC adds 1a38f4851fe [ARM] Don't print "Requires NEON" error message for M-profile adds f4f1f074885 [CallSiteSplitting] Support splitting of blocks with instrs [...] adds de85a83eb31 [CallSiteSplitting] Fix new-pm test, as TargetIRAnalysis is [...] adds 913da000b57 [InstCombine] Simplify getLogBase2 case for scalar/splats. NFCI. adds ac28bc23422 [CallSiteSplitting] Dereference pointer earlier. adds aadb70d6151 [CallSiteSplitting] Clear ValueToValue maps. adds 70f366846f5 [IR] Fix creating mutable versions of TBAA access tags adds 1f703fd80dd Revert r325001: [CallSiteSplitting] Support splitting of bl [...] adds 81540ce1080 [DAG] fix type of undef returned by getNode() adds 4b977b2e67d [ARM] Allow half types in ConstantPool adds 1ba90b39233 [Hexagon] Remove unnecessary check adds 0140a14c552 [Hexagon] Simplify some code, NFC adds a7204c7b8c5 [X86] Add combine to shrink 64-bit ands when one input is a [...] adds 7947e7211b5 [DAGCombiner] Add one use check to fold (not (and x, y)) -> [...] adds 2930e5c52df [AMDGPU] Change constant addr space to 4 adds 3fa22fa403d [CodeGen] Print bundled instructions using the MIR syntax i [...] adds e156d07a1bc Revert r324903 "[AArch64] Refactor identification of SIMD i [...] adds c9c691411d1 [DeadStoreElimination] Salvage debug info from dead insts adds 877eaaa20ee [Debugify] Avoid verifier failure on non-definition subprograms adds 30138e81791 [InstCombine, InstSimplify] (re)move tests, regenerate checks; NFC adds 743dbe8367a [InstCombine] fix test comment and add vector test; NFC adds 7c57f9ef8d8 Document the shortcomings of DwarfExpression::addMachineReg(). adds e4b5c6ac632 [AMDGPU] Cleanup in memory legalizer tests. NFC. adds bdeb539dcc8 [GISel]: Make Pattern matcher for FADD commutative adds 24775560e22 [GISel]: Add Pattern Matcher for G_FMUL. adds 57d82ee0807 [LLD] Implement /guard:[no]longjmp adds b0e47911f9a [InstCombine] (bool X) * Y --> X ? Y : 0 adds 197917a303a [X86] Use EDI for retpoline when no scratch regs are left adds 2a3f34a9794 [InstCombine] add vector tests, fix comments; NFC adds 96c99810d80 [InstCombine] (lshr X, 31) * Y --> (ashr X, 31) & Y adds 3dd5724d79c [GVN] Salvage debug info from dead insts adds 0dcc17c9b06 [InstCombine] put tests of mul with neg operand(s) together; NFC adds 747839c4838 [globalisel][legalizerinfo] Follow up on post-commit review [...] adds 14eb0f411e1 Fix off-by-one in set_thread_name which causes truncation t [...] adds b851d97de27 [gold] Fix error report in thinlto_emit_linked_objects.ll test adds d09d7393dda [X86] Remove dead code from retpoline thunk generation adds 35abcb5e69a Refactor DisassembleInfo in MachODump.cpp adds fef5198e5ce Use delete[] to deallocate array of chars adds e019ebf3614 Use delete[] instead of free adds f71997e9112 [SelectionDAG] Remove duplicate code from TargetLowering::S [...] adds 8e229ec0e5f Adding a width of the GEP index to the Data Layout. adds fd7c224b389 Implement a case-folding version of DJB hash adds ce2ac038281 Fix build broken by r325107 adds c8650a44884 [IRMover] Move type name extraction to a separate function. NFC adds ef56f2df647 Revert r325107 (case folding DJB hash) and subsequent build fix adds 4ef378ed280 [Utils] Salvage the debug info of DCE'ed 'and' instructions adds 9e8a4253371 Use EXPECT_FALSE instead of EXPECT_EQ(false, ... adds 2f7051e39f3 [LoopInterchange] Incrementally update the dominator tree. adds 283bc8f7bda Recommit r325001: [CallSiteSplitting] Support splitting of [...] adds a5e5821989e [X86][SSE] Relax type legality for combineTruncateWithSat P [...] adds 693160b019e [X86] Reduce Store Forward Block issues in HW - Recommit af [...] adds 9e4131672d2 Fix GCC -Wlogical-op-parentheses warning. NFCI. adds 1dd33b89293 [ARM] f16 stack spill/reloads adds acdbc6f43e7 [SLP] Allow vectorization of reversed loads. adds ba2e473a530 [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV adds 05fb85ea810 [x86] add baseline vector compare tests for D42948; NFC adds c8281cb44fb Store defined macros in MCContext. adds 8be336f7ed1 [InstCombine] refactor folds for mul with negated operands; NFCI adds e735f34e8b4 [InstCombine] replace isa/cast with dyn_cast; NFC adds a7c2acc8f19 [InstCombine] simplify isFMulOrFDivWithConstant(); NFCI adds bcf26eacc01 [DWARF] Fix incorrect prologue end line record. adds d6953a90f79 [InstCombine] regenerate checks; NFC adds 32d5031a435 [AMDGPU] Remove non-temporal flag from argument loads adds 29dc0262dff [InstCombine] Don't fold select(C, Z, binop(select(C, X, Y) [...] adds 7767e14d9df [X86][SSE] truncateVectorWithPACK - Use src type instead of [...] adds 5bd84cc8500 Move llvm::computeLoopSafetyInfo from LICM.cpp to LoopUtils [...] adds 9f9d3d9a03b [RegisterClassInfo] Invalidate the register pressure set li [...] adds 06d6207c1c6 Pass a reference to a module to the bitcode writer. adds 4fe1287be8a Update examples for API change. NFC. adds 22b7724fe30 Pass a module reference to CloneModule. adds 394c5f7af9c [InstCombine] add tests and comments for fdiv X, C; NFC adds 2d51ba3a299 GlobalISel: Add templated functions and pattern matcher sup [...] adds 8b96d7cf104 Use std::unique_ptr. NFC. adds c80da497307 Use std::unique_ptr. NFC. adds 16b4c29d610 Use std::unique_ptr. NFC. adds 4569bffc7a8 [CodeGen] Print predecessors, successors, then liveins in - [...] adds d19206140ba Use std::unique_ptr. NFC. adds a7ae9840dec Removed superfluous semicolon to fix -Wpedantic gcc warning. NFCI. adds 1cdbd1bcfd9 [Hexagon] Split HVX vector pair loads/stores, expand unalig [...] adds 1db3d9946c0 Use std::unique_ptr. NFC. adds c84d87c995f Use std::unique_ptr. NFC. adds d86697c7307 Use std::unique_ptr. NFC. adds f96e649d015 Use std::unique_ptr. NFC. adds c2241df969e Use std::uniue_ptr. NFC. adds cdac12cdfaf Change the BugDriver to store the current module with std:: [...] adds 9eb66edbc2c [X86] Don't swap argument on BOUND instruction in at&t syntax. adds d8d27ad50da [ORC] Switch to shared_ptr ownership for AsynchronousSymbol [...] adds 8115e01f129 [ORC] Consolidate RTDyldObjectLinkingLayer GetMemMgr and Ge [...] adds 4a81fc6db8d [ThinLTO/CFI] Include TYPE_ID summaries into GLOBALVAL_SUMM [...] adds 4ba06d7558a [InstCombine] clean up fold for X / C -> X * (1.0/C); NFCI adds 2785020fa23 [llvm-objcopy] Fix handling of zero-size segments in llvm-objcopy adds 563bfa637ca [X86] Reverse the operand order of invlpga in at&t syntax t [...] adds 87e965c1394 [X86] Don't use 64 bit hex constants in a 32 bit assembler test. adds 6a56a6379c7 [X86] Dont' allow 'outs' and 'ins' in at&t syntax without s [...] adds edfd445801b [X86] Change 32 and 64 bit versions of LSL instruction have [...] adds 0d9435c9307 [X86] Regnerate test to show scheduling comments. NFC adds bf830a86e66 [SCEV] Favor isKnownViaSimpleReasoning over constant ranges check adds 185af7af533 [NFC] Fix metadata placement in test adds 724361f7769 [NFC] Rename isKnownViaSimpleReasoning to isKnownViaNonRecu [...] adds 89b2bec4e03 (NFC)[MachineCombiner] Improve debug output. adds ca451d02e47 Report fatal error in the case of out of memory adds 9d4478cdf25 Specify namespace for realloc adds 165fd931ac2 Revert r325224 "Report fatal error in the case of out of memory" adds 164091b722c [ARM] f16 vcmp fixes adds 371e6cc130d [SelectionDAG] Add initial implementation of TargetLowering [...] adds 032b42a4b9a [DebugInfo] Accept enumeration types without underlying int [...] adds 6671a9d78f1 [X86][SSE] combineTruncateWithSat - use truncateVectorWithP [...] adds 0e9e744bddd [InstCombine] allow X / C -> X * (1.0/C) for vector splat F [...] adds 64f776d49e2 [X86][SSE] combineTruncateWithSat - use truncateVectorWithP [...] adds 5f393824aef [ARM] Allow 64- and 128-bit types with 't' inline asm constraint adds b1c2195313a [InstCombine] allow sin/cos transforms with 'reassoc' adds 5ca0745329a [CodeGen] Print irreducible loop header weight as a MIR comment adds 87eb10ac0c0 [SelectionDAG] Pull out repeated Op.getOpcode(). NFCI. adds 34534d0082c [Hexagon] Fix lowering of formal arguments after r324737 adds e9184306cf0 [CodeGen] Separate MBB metadata from instructions in -debug [...] adds 0623406b2a5 [Hexagon] Make the vararg handling a bit more robust adds faba0c86987 [InstCombine] test fdiv folds better; NFC adds 04ab83e17bc [InstCombine] use m_OneUse to reduce code; NFC adds 0b720faa051 [SLP] Added test for reversed stores, NFC. adds 23d8aebeaf9 Revert "[Hexagon] Make the vararg handling a bit more robust" adds 13758ad5153 bpf: fix a bug in dag2dag optimization for loads from reado [...] adds 90f3933650f [SLP] Fix the test for the reversed stores, NFC. adds a0f5c858468 Recommit [Hexagon] Make the vararg handling a bit more robust adds ee57c2c7b24 [X86][SSE] Add saturated truncation tests for storing illeg [...] adds fe3d5697302 [WebAssembly] Restore "*-wasm" tests. adds 8b2a3e8b203 Call FlushFileBuffers on output files. adds cc12669dc8a Silence warning about unused private variable. adds 24b087fbba6 [X86] Add test cases for opportunities for using BT instead [...] adds 09cae80a9d6 [Utils] salvageDI: Add a comment and move a call earlier, NFC adds 430cc952f4f [SCCP] Test that constant propagation updates debug info, NFC adds b093e4e6512 [ARM] Fix redirect in inline assembly test adds adf9928ba42 [Coroutines] Don't move stores for allocator args adds 37496d05582 [X86] Use btc/btr/bts to implement xor/and/or that affects [...] adds 297d461b010 [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (l [...] adds d2e6138dff1 [X86] Enable BT to be used in place of TEST for single bit [...] adds b8c067b8506 [opt] Port the debugify passes to the new pass manager adds 048f392b852 [X86][3DNOW] Teach decoder about AMD 3DNow! instrs adds ff74bbe2b9e Don't make PDBs by default in Release mode adds da3c20caee4 [Debugify] Don't check functions which were skipped adds ee1ab185391 [AMDGPU] Combine adjacent waitcounts in a single strongest wait adds ed02ca36988 [DCE] Salvage debug info from dead insts adds 51f803307e0 Allow 0 to be a valid value pruning interval in C LTO API. [...] adds 30753597d82 [X86] Add the test cases that were supposed to go with r325287. adds 3da5dcf4be7 [GVN] Partially revert debug info salvage change (r325063) adds 4f9b5530092 Remove brittle check lines from a test, NFC adds 6e5a3d77a3c [APInt] Fix extractBits to correctly handle Result.isSingle [...] adds 2ae7492272a [X86] Don't zero_extend cmov up to i64, stop at i32. adds 05d8e598f19 [X86] Allow CMOVs of constants to be sign extended from i32. adds 11b0e47b5b7 [ThinLTO] Import global variables adds ca353f0f9c1 [ARM] Materialise some boolean values to avoid a branch adds 053d9bfd93a [LegalizeDAG] Fix legalization of SETCC adds a596a56b232 [ARM] Return true in enableMultipleCopyHints(). adds 04bf737a846 [Transforms] Propagate TBAA info in SROA adds 7735c733573 [SelectionDAG] Add initial SimplifyDemandedVectorElts suppo [...] adds 63623d97024 [mips] Remove codegen support from some 16 bit instructions adds 148bc17b95d [PowerPC] Fix transform in table gen file causing UB adds 7267bdf4929 [X86][SSE] Allow float domain crossing if we are merging 2 [...] adds a60b694525c [InstCombine] reduce code duplication; NFC adds e0288d90cb0 [SelectionDAG] Enable SimplifyDemandedVectorElts support fo [...] adds 7256cd438bf AMDGPU/SI: Turn off GPR Indexing Mode immediately after the [...] adds 55da8a3a3e0 [JumpThreading] PR36133 enable/disable DominatorTree for LV [...] adds 76c06b10978 [InstCombine] remove redundant debug info setting; NFC adds ce034459357 Fix signed/unsigned comparison warning. NFCI. adds 884f75aff36 [ThinLTO] Fix data race in test adds dcd1ba6449b [ThinLTO] Fix data race in test #2 adds d23faddc17f Fix signed/unsigned comparison warning. NFCI. adds e7f780caf1c [InstCombine] add FMF to better show current fdiv fold beha [...] adds e150103e1c7 [InstCombine] clean up fdiv-with-fdiv folds; NFCI adds f010b43ca2c [WebAssembly] MC: Make explicit our current lack of support [...] adds d10074617b6 [X86] Remove call to ShrinkDemandedCosntant from the SHRUNK [...] adds 2b45169dc8d [X86] Only reorder srl/and on last DAG combiner run adds 88d6664b978 AMDGPU/SI: Extend promoting alloca to vector to arrays of u [...] adds 2458d2d4505 [AArch64] Fix BITCAST lowering crash adds 68041a58acf Remove useless comment - seems to be a copy+paste typo. NFCI adds feaa594c1db Fix emission of PDB string table. adds 17cc300e03c Try to fix broken build with some compilers. adds c0a57c68cab Try again to fix the build. adds 4bf0aa0c174 AMDGPU: Bring processors and features in sync with the spec adds ec071fa9373 [X86] In lowerVSELECTtoVectorShuffle, don't map undef selec [...] adds 45ebd75cc10 Make sure we invoke ld64.lld and ld-wasm in the build directory. adds 8afcfc323d9 [Constant] add floating-point helpers for normal/finite-nz; NFC adds 16290892d31 AMDGPU: Bring elf flags in sync with the spec adds 25462c08b90 [GISel]: Make GlobalISelEmitter rule prioritization compati [...] adds fe95155e6c4 Silence an unsigned vs signed compare warning. adds 090b6e29312 Remove an unused function. adds 6b408e84d08 Run these tests, the errors were old and not valid anymore. adds 1ef7c4d9873 AMDGPU: Remove unused private member of AMDGPUTargetELFStreamer adds 2749eb2cdfc [ThinLTO] Allow indexing to request backend to ignore the module adds ce96f9844a8 Remove "--full-shutdown" and instead use an environment var [...] adds fd8f168188d [X86] Turn selects with constant condition into vector shuf [...] adds 8ea31b8db0c [InstSimplify] add vector select tests with undef elts in c [...] adds 20ea0e4c87d [DAG, X86] Revert r324797, r324491, and r324359. adds 0d9a8774c98 Revert "[MachineCopyPropagation] Extend pass to do COPY sou [...] adds 2c7faba719f [AMDGPU] Return true in enableMultipleCopyHints(). adds 25242678c96 Report fatal error in the case of out of memory adds ba9330b1269 [DebugInfo] Removed assert on missing CountVarDIE adds 7abdc5f5e1a Fix signed/unsigned comparison warning in AsmGenMatcher gen [...] adds c26f626148f [DAGCombiner] Remove simplifyShuffleMask - now handled more [...] adds 8b9c4c3e78d [dwarfdump] Fix spurious verification errors for DW_AT_loca [...] adds 604b57e7d4e Fix unused variable warning. NFCI. adds 7c5411cd78e [AArch64] Implement dynamic stack probing for windows adds 29a500dd45d [InstSimplify] move select undef cond fold with other const [...] adds fb191fe666f [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168) adds 0c8faa825c0 [InstSimplify, InstCombine] add tests with vector undef elts; NFC adds 96d4ee9e0ed [PatternMatch] enhance m_One() to ignore undef elements in vectors adds 68a901a7ad1 [DebugInfo][FastISel] Fix dropping dbg.value() adds e8664b0b333 [X86] Add 'sahf' to getHostCPUFeatures so -march=native wil [...] adds e3ea6ec6c06 Made test dbg_value_fastisel.ll specific to AArch64 fast-isel. adds b10600ed2c6 [RISCV] Revert r324172 now r323991 was reverted adds 2a61c464abd [ARM] Add LLVM tests for the vcvtr builtins adds b70374c20ad [MIPS][MSA] Convert vector integer min/max opcodes to use g [...] adds a67b2497a9c [ThinLTO] Add GraphTraits for FunctionSummaries adds 8a630465fbd [SelectionDAG] SimplifyDemandedVectorElts - add support for [...] adds 95e99979dc4 [SelectionDAG] ComputeNumSignBits - add support for SMIN+SM [...] adds d76d550dc7c Fix Wparentheses warning. NFCI adds 17c6cf08e50 Revert: [llvm] r325448 - [ThinLTO] Add GraphTraits for Func [...] adds 36d49041ee5 [X86] Add -show-mc-encoding to the avx512-vec-cmp.ll test a [...] adds cfbc9a9681e [X86] Make masked pcmpeq commutable during isel so we can f [...] adds 52d33aeae9b [BPF] Return true in enableMultipleCopyHints(). adds d8f57105010 [AArch64] Coalesce Copy Zero during instruction selection adds ef788ddab2f [Support] Replace hand-written scope_exit with make_scope_exit. adds 29b1d741030 [PatternMatch] reformatting and comment clean-ups; NFC adds a6ba3ad8c05 [AArch64][GlobalISel] Support G_INSERT/G_EXTRACT of types < [...] adds 9a27616fda1 [AArch64][GlobalISel] Fix an assert fail/miscompile when fp [...] adds dfb9c78c9f2 Fix unused assertion variable warning. adds 142011a54be [InstSimplify] add tests with vector undef elts; NFC adds 5563781f3f7 [PatternMatch, InstSimplify] enhance m_AllOnes() to ignore [...] adds d5971e83a6e [X86] Correct a typo I made in combineToExtendCMOV recently. adds 33d48226d10 Add LanaiMCTargetDesc.h to LanaiInstrInfo.h to make it self [...] adds 7737462b290 [AVR] Fix a lowering bug in AVRISelLowering.cpp adds a78fde85591 Add default address space for functions to the data layout (1/3) adds 88b07629402 [AVR] Set the program address space in the data layout adds de603ec82d5 [llvm-opt-fuzzer] Add another pack of passes for continuous [...] adds 0b603b77476 [Transforms] Propagate new-format TBAA tags on simplificati [...] adds db74b76ab5d [X86][SSE] combineTruncateWithSat - use truncateVectorWithP [...] adds f751ac3a9c3 Revert "[CodeGen] Move printing '\n' from MachineInstr::pri [...] adds b0f8fe52832 [ThinLTO] Add GraphTraits for FunctionSummaries adds cf75fe0300c [CodeGen] Fix tests breaking after r325505 adds 94eb72df457 Bring back r323297. adds 1fceaab0288 [TTI CostModel] change default cost of FP ops to 1 (PR36280) adds b64767750ba [CodeGen] Refactor AppleAccelTable adds 7c93b6c31ca [Dominators] Update DominatorTree compare in case roots are [...] adds db070bbdacd [AMDGPU] Increased vector length for global/constant loads. adds 176cbb368e9 [SelectionDAG] ComputeKnownBits - add support for SMIN+SMAX [...] adds 04c7451aa8d [AMDGPU] Make note of existing waitcnt instrs; this is add- [...] adds d57c7490c56 bitcode support change for fast flags compatibility adds 56fd21e66cb [X86] Reduce the number of isel pattern variations needed f [...] adds c3ed6c4bc30 [X86] Stop swapping the operands of AVX512 setge. adds fb04979cdff [llvm-objcopy] Use the full filename in --add-gnu-debuglink adds 2e45370fea5 [Coroutines] Move debug statement before assert adds e9859e6fe6d [InstCombine] move fdiv tests; NFC adds 17348b5856f [InstCombine] refactor fdiv with constant dividend folds; NFC adds 3a368d57a02 [mem2reg] Use range loops (NFCI) adds c6e8ed569c3 [InstCombine] allow fdiv with constant dividend folds with [...] adds 822227740b4 [X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible. adds 9a792f91149 Revert "[mem2reg] Use range loops (NFCI)" adds 645e59085ae [InstCombine] use CreateWithCopiedFlags to reduce code; NFCI adds 5d159adbed1 [GISel]: Add pattern matchers for G_BITCAST/PTRTOINT/INTTOPTR adds 4ef7037e537 [X86] Make a helper function for commuting AVX512 VPCMP imm [...] adds d8eec01d783 [X86] Make XOP VPCOM instructions commutable to fold loads [...] adds 400726575b7 [X86] Mark XOP vpmac* and vpmadc intrinsics as being commut [...] adds a583f9e7c12 [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 [...] adds 06c71d8a6f9 Report fatal error in the case of out of memory adds cd1a39550da [X86] Remove GCCBuiltin from a bunch of intrinsics that are [...] adds b7da3a52b96 [X86] Add 512-bit unmasked pmulhrsw/pmulhw/pmulhuw intrinsi [...] adds 692f0570722 [X86][CET]: Adding full coverage of MC encoding for the CET [...] adds 91b97da7a3f [MC] - Don't crash on unclosed frame. adds ac0fe3df711 [AMDGPU] stop buffer_store being moved illegally adds 930bcc9bdfb [llvm-mc] - Produce R_X86_64_PLT32 for "call/jmp foo". adds 3be7f43a553 [ARM] Mark -1 as cheap in xor's for thumb1 adds c9d87a17ca4 [VectorLegalizer] Fix uint64_t typo in ExpandUINT_TO_FLOAT [...] adds 530e3d2b560 [X86] Regenerate XOR tests adds f59ede63fef [Hexagon] Fix alignment calculation of stack objects in Hex [...] adds 1f9881f51a2 [PowerPC] Reduce stack frame for fastcc functions by only a [...] adds 196883612a4 [DEBUGINFO] Add support for emission of the inlined strings. adds b39c3c39cdf [mips] Correct the definition of cvt.d.w adds c1de3c6452a [InstCombine] fold fdiv with non-splat divisor to fmul: X/C [...] adds 162d2b4f9c8 [InstCombine] remove compound fdiv pattern folds adds 928e1d73a4d [InstCombine] remove unneeded dyn_cast to prevent unused va [...] adds aedbf6f6f98 [vim] Recognize more FileCheck comments adds 35c4cd1eb57 [dsymutil] Correctly handle DW_TAG_label adds a7f9439a213 [X86] Promote 16-bit cmovs to 32-bits adds bff6449bb83 [SelectionDAG] Add LegalTypes flag to getShiftAmountTy. Use [...] adds 20db0963755 [X86] Correct SHRUNKBLEND creation to work correctly when t [...] adds 771994be2dd [SLP] Fix tests checks, NFC. adds 1837dbf46a8 [Hexagon] Handle *Low8 register classes in early if-conversion adds e271f8c46c6 [IRBuilder] fix CreateMaxNum to actually produce maxnum (PR36454) adds ae97c16c39c [X86][3DNow] Regenerate intrinsics tests adds 8f4be0b00f0 [X86][MMX] Regenerate MMX bitcast test adds adbbd244528 [llvm-objdump] Use unique_ptr to simplify memory ownership adds 050ca4d5a49 [AMDGPU] Removed redundant run lines for fmuladd.f16 test. NFC. adds c381a107ab2 [ARM] Lower BR_CC for f16 adds 1918edb644b [LV] Fix test checks, NFC. adds f4aea131884 [ThinLTO/gold] Avoid race with cache pruner by copying to t [...] adds 761281e6685 [LTO] Remove unused Path parameter to AddBufferFn adds b859fa27862 [AArch64] Refactor instructions using SIMD immediates adds d6257e1cb66 [InstSimplify] add tests for m_SignMask with undef vector e [...] adds d4f4a8e82dc [PatternMatch] enhance m_SignMask() to ignore undef element [...] adds 6a9e037dc72 [SelectionDAG] Support known true/false SimplifySetCC cases [...] adds 968ac28c667 [InstCombine] remove unneeded operand swap: NFCI adds c138405948d [MemoryBuiltins] Check nobuiltin status when identifying ca [...] adds 2e9f926ca04 [PBQP] Fix PR33038 by pruning empty intervals in initializeGraph. adds 3f03f0d1c79 Fix broken test from r325630. adds edfc1e1c63c [X86] Fix copy/paste mistake in test. adds 29d38d85596 [InstCombine] add test for vector -X/-Y; NFC adds 3affd583226 [InstCombine] auto-generate full checks; NFC adds 9302e9a5002 [DSE] Don't DSE stores that subsequent memmove calls read from adds cd622ef7a2f [PatternMatch] allow vector matches with m_FNeg adds 8d864b81e18 Revert "[AMDGPU] Increased vector length for global/constan [...] adds 99eb4ff05c0 [InstCombine] add tests for fdiv with negated op and consta [...] adds ba989e1b97f [InstCombine] -X / C --> X / -C for FP adds 2fb7f37b947 [InstCombine] C / -X --> -C / X adds d29c876d9ac [mips] Spectre variant two mitigation for MIPSR2 adds 931063957a0 [X86] Disable CLWB for Cannon Lake adds 652f5b5017a [lit] Fix a problem with spaces in the python path by addin [...] adds 1c629279f17 revert r325515: [TTI CostModel] change default cost of FP o [...] adds fd30c2ddf8c [BDCE] Salvage debug info from dying insts adds 636cb99c294 RISCV: Add COFF address space adds 11cbda7d816 [X86][MMX] Add some MMX build vector tests adds febc65750a5 [X86][MMX] Add PR29222 test case adds 63879585679 [AMDGPU][MC] Added lds support for MUBUF instructions adds b794d6e087d AMDGPU: Do not combine loads/store across physreg defs adds 3949dba9fa7 [X86] Regenerate GPR:XMM bitcast test adds 43fc4caeb85 [X86][MMX] Regenerate MMX PSUB commutation test adds 7159bb59fed [IRMover] Implement name based structure type mapping adds 1f383654e09 [SCEV] Temporarily disable loop versioning for the purpose [...] adds b44298865b3 [Sparc] Include __tls_get_addr in symbol table for TLS calls to it adds 27e6b3dc3f6 [SLP] Fix test checks, NFC. adds 446c4af51cf [X86] LowerBITCAST - pull out repeated calls to getOperand( [...] adds 71603d9c778 [X86][MMX] Regenerate MMX arithmetic tests adds e5be8f99d82 [Hexagon] Return true in enableMultipleCopyHints(). adds 818af9b6fea [X86][MMX] Regenerate MMX MASKMOV test adds bde3a918119 [LV] Fix test checks, NFC adds 2bbb2bdf2e8 Handle IMAGE_REL_AMD64_ADDR32NB in RuntimeDyldCOFF adds f3f5d48b6b7 [X86][MMX] Run MMX bitcast test on 32 and 64-bit targets adds 646efe67c8e asan: add kernel inline instrumentation test (retry) adds 73071d5e044 [hwasan] Fix inline instrumentation. adds 9540e47959f Fix a memory leak and a cross module reference. adds 2d01b0d814c Revert "[IRMover] Implement name based structure type mapping" adds b0c13268b82 [AArch64] add SLP test for matmul (PR36280); NFC adds 5c377f610d6 [AArch64] fix IR names to not be 'tmp' because that gives t [...] adds fc8ba497cd1 [ORC] Switch RTDyldObjectLinkingLayer to take a unique_ptr< [...] adds 40be992c34c [ORC] Switch from a StringMap to an internal VSO in RTDyldO [...] adds 734c4808f82 [ORC] Switch to shared_ptr ownership for SymbolSources in VSOs. adds 2f11b47f482 [X86][MMX] Add MMX_MOVD64rr build vector tests showing unde [...] adds 8ff0fbbcf6b [InstCombine] add and use Create*FMF functions; NFC adds fda791f47a1 [Hexagon] Add TargetRegisterInfo::getPointerRegClass() override adds 274527c9b5c Resubmit r325107 (case folding DJB hash) adds d4a6a59bf38 [InstCombine] add some random FMF to tests so we know it's [...] adds e4507fb8c94 bpf: disable DwarfUsesRelocationsAcrossSections adds 4acf80e7043 [X86][MMX] Generlize MMX_MOVD64rr combines to accept v4i16/ [...] adds e088ad8d0cc [Utils] Avoid a hash table lookup in salvageDI, NFC adds 634abdc95e3 [PowerPC] Do not produce invalid CTR loop with an FRem adds 3f840502160 [SCEV][NFC] Factor out common logic into a separate method adds 77fc8fce7e1 [SampleProf] NFC. Expose reusable functionality in SampleProfile. adds de866c328a8 [DAGCombiner] Add two calls to isVector before making calls [...] adds 1763be43736 [NFC] fix trivial typos in comments adds b7234d1b80a [ARM] f16 constant pool fix adds fa4cc6cd989 Added a test that I forgot to svn add in my previous commit [...] adds 558fe760327 Revert r325754 and r325755 (f16 literal pool) because build [...] adds 44638356964 [dsymutil] Be smarter in caching calls to realpath adds 7f3a2c29f3f [ARM] Fix issue with large xor constants. adds 612ed3c0007 [dsymutil] Replace PATH_MAX in SmallString with fixed value. adds 7fa2858a2c3 Recommit: [ARM] f16 constant pool fix adds 3ad0c5ad842 [dsymutil] Fix typos and formatting. NFC. adds 92a76c5814a [dsymutil] Remove \brief from comments. NFC adds bc148d46fc0 [mips] Regenerate tests for D38128 (NFC) adds b891e74e206 [SLPVectorizer][X86] Add load extend tests (PR36091) adds 2f5aa6879da [RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValu [...] adds a5e74bb3bda Fix Wdocumentation warning - remove param tag for old argument adds fb06b4ce66a Syndicate duplicate code between CallInst and InvokeInst adds 16c81d461c3 [mips] Generate memory dependencies for byVal arguments adds da8cf80cf10 [InstCombine] add fmul multi-use test; NFC adds 037e821391b [FunctionAttrs][ArgumentPromotion][GlobalOpt] Disable some [...] adds bcdec400081 [RISCV] Implement c.lui immediate operand constraint adds 83e2fa52c4e AMDGPU: Stop using .NAME in .td files adds a61d1a5d0b8 TableGen: Add some more helpful error messages adds 869ea800def TableGen: Generalize type deduction for !listconcat adds b5681f5c717 TableGen: Fix type deduction for !foreach adds b5d03008a3a TableGen: Fix type of resolved and converted lists adds 6d22c1fe698 TableGen: Allow implicit casting between string and code adds f410ef7d961 TableGen: Add strict assertions to sanity check earlier typ [...] adds 82c99bc02ea [DEBUGINFO] Do not output labels for empty macinfo sections. adds 81a6bfd7ef6 [X86][AVX512] Add DQ+VLX scalar int<->fp tests cases for D43441 adds adb809f2fad [IRBuilder] add creators for FP with FMF; NFCI adds 0bbd02e7757 [MC] Don't crash on modulo by zero (PR35650) adds e07827f03be [SelectionDAG] Move matchUnaryPredicate/matchBinaryPredicat [...] adds 425c3b09bec [AlignmentFromAssumptions] Set source and dest alignments o [...] adds 21ed2a6e296 [libFuzzer] Include TEMP_MAX_LEN in Fuzzer::PrintStats. adds f662ded3c60 [gold] Extract runLTO to avoid exit(0) from function with n [...] adds 55523deb41a [ThinLTO] Always create linked objects file for --thinlto-i [...] adds 1e23b92b968 Fix DataFlowSanitizer instrumentation pass to take paramete [...] adds 95d34a2e597 [ThinLTO] Represent relative BF using a scaled representation . adds 7a328048c98 [PDB] Implement more find methods for PDB symbols adds 514c796d39c Revert "[DebugInfo][FastISel] Fix dropping dbg.value()" adds fe83c7abdde [PDB] Fix buildbot failure from missing include for DIAEnum [...] adds e2e807c4e11 [X86] Make the subus special case in LowerVSETCC self contained adds d27cd09ede7 [PDB] Add missing override to silence buildbots adds fbabe6e9f62 [TargetLowering] Rename isCondCodeLegal to isCondCodeLegalO [...] adds 327fc51147b [ThinLTO/gold] Perform cache pruning when cache directory s [...] adds 1dff32f122d [DWARFv5] Turn an assert into a diagnostic. Hand-coded asse [...] adds dd9756f8e8e [InstrTypes] add frem and fneg with FMF creators adds 3159c5f29dc Fix the build of the wasm backend. adds be6ebba4a11 Update comment for whether or not we can optimize an alias [...] adds 1d5bed06d6b Fix llvm-pdbutil to handle new built-in types adds fa1ecef5465 [AArch64] Improve macro fusion test case adds 52ddc71fc37 [X86] Turn setne X, signedmin into setgt X, signedmin in Lo [...] adds c7f6e5de57b Fix grammar. NFC. adds d6bbd59585d [PDB] Check the result of setLoadAddress() adds 03b6034a16b [AArch64] Refactor macro fusion (NFC) adds 51e9e8de037 [X86] Turn setne X, signedmax into setgt signedmax, X in Lo [...] adds 28f8634b6ed [GISel]: Fix base case for m_any_of PatternMatcher. adds fc177d34de6 Revert r325128 ("[X86] Reduce Store Forward Block issues in HW"). adds 7217c2e7b4b Remove file missed by r325852 due to merge conflict. adds d5784797c66 [WebAssembly] Add first claass symbol table to wasm objects adds 5b880f8d07b [Mips] Return true in enableMultipleCopyHints(). adds 0c0db7175b6 Mark MergedLoadStoreMotion as not preserving MemDep results adds d9086c893cc StructurizeCFG: Test for branch divergence correctly adds 02e435715e5 AMDGPU: Track physreg uses in SILoadStoreOptimizer adds c34350228ef TableGen: Add !size operation adds 01724121ace TableGen: Fix typeIsConvertibleTo for record types adds 69ccda272dd TableGen: BitInit and VarBitInit are typed adds c374065b04c TableGen: Avoid using resolveListElementReference in TGParser adds 581db4c3f69 [MIPS GlobalISel] Adding GlobalISel adds aba588d701f Revert "TableGen: Fix typeIsConvertibleTo for record types" adds d76d0bdf823 [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in [...] adds f998d9c0655 [WebAssembly] NDEBUG is spelled without a leading underscore. adds ae91444dd14 llvm-config: Add advapi32 to --system-libs on Windows (PR36372) adds faead677c9c [X86][F16C] Regenerate half conversion tests adds 09bdb6323c7 [SystemZ] Fix VPDI argument in test. adds c2a1fb84de7 [SystemZ] Also update the CHECK line for VPDI adds 54a2a8a3dff Support for the mno-stack-arg-probe flag adds 1977d05ab44 [mips] remove unused fields in MipsInstructionSelector adds 406f2e505de [mips] finish removal of unused fields in MipsInstructionSelector adds 38bd4c9f6df [PowerPC] Code cleanup. Remove instructions that were withd [...] adds 3b0acd6c80f [X86] Regenerate i128 multiply tests adds 69e8988b65f [InstCombine] use FMF-copying functions to reduce code; NFCI adds 02d9ce74616 [InstCombine] refactor fmul with negated op folds; NFCI adds 6ed382f4f6a [BPI] Detect branches in loops that make themselves not taken adds 799e36774a9 [Debug] Add dbg.value intrinsics for PHIs created during LCSSA. adds 13357c96d2d [MachineOperand][Target] MachineOperand::isRenamable semant [...] adds 1c89a6ff631 [X86] Custom split v32i16/v64i8 bitcasts when AVX512F is av [...] adds 186f988a8d3 [MemorySSA] Reduce padding in MemoryDefs. NFC adds c329c0d9347 [MemorySSA] Use fewer magic numbers. NFC adds b18516a660b [X86][SSE] Add x > C-1 ? x+-C : 0 --> subus x, C test caaes [...] adds 67633697a83 [Test] Fix the test to output to /dev/null instead of redirecting. adds 5ed988c074d Fix compiler warning introduced in r325931. NFC. adds 629f07faf15 [PATCH] [AArch64] Add new target feature to fuse conditiona [...] adds 9de0bdbba70 Shrink various scheduling tables by using narrower types. adds bb5430c4a4c [X86][SSE] Generalize x > C-1 ? x+-C : 0 --> subus x, C com [...] adds a4a3d378317 Because of CVE-2018-6574, some compiler options and linker [...] adds 04f110e6350 [WebAssembly] Fix macro metaprogram to not duplicate code as much. adds bf0d2f98638 [X86] Add DAG combine to remove (and X, 1) from in front of [...] adds 48d3197227f Fixed unused variable warning. NFCI. adds 0eff8491870 [Hexagon] Recognize non-immediate constants in HexagonConst [...] adds 2a24e8ec540 [Power9] Add missing instructions to the Power 9 scheduler adds ad86b544408 [X86] Add assembler/disassembler support for blendm with ze [...] adds 66a69087796 Simplify a DEBUG statement to remove a set but not used var [...] adds 9d9603f80e6 [InstCombine] allow fmul-sqrt folds with less than full -ff [...] adds 11fc5bbdc73 Intrinsics calls should avoid the PLT when "RtLibUseGOT" me [...] adds 4b957aaea87 [InstSimplify] sqrt(X) * sqrt(X) --> X adds b4be365a0af Sink the verification code around the assert where it's han [...] adds f021d3eee1a [InstCombine] simplify code for fabs(X) * fabs(X) -> X * X; NFC adds 5e4b515c4bb [DebugInfo] Support DWARF v5 source code embedding extension adds 3d238821f12 [MemorySSA] Fix a cache invalidation bug with removed accesses adds f41b0c1dff5 [PowerPC] Disable shrink-wrapping when getting PC address t [...] adds 2ed4ddeb742 [DebugInfo] Add remaining files to r325970 adds f7d53809c16 bpf: Use markSuperRegs to mark reserved registers adds 4aaa0b2af40 bpf: Tighten the immediate predication for 32-bit alu instructions adds 3cd876e906d bpf: Define instruction patterns for extensions and truncat [...] adds ead0a5d4bfb bpf: New target attribute "alu32" for 32-bit subregister support adds e3694b14f28 bpf: New calling convention for 32-bit subregisters adds e776173462b bpf: Handle i32 for ALU operations without ISA support adds 56af0c94dd2 bpf: Support condition comparison on i32 adds 91229ae9e7f bpf: Support i32 in getScalarShiftAmountTy method adds 9b683c79201 bpf: New instruction patterns for 32-bit subregister load a [...] adds 7beb63a0de2 bpf: Support 32-bit subregister in various InstrInfo hooks adds 01d04feb88f bpf: Enable 32-bit subregister support for -mattr=+alu32 adds c5cb13fb0df bpf: New decoder namespace for 32-bit subregister load/store adds 626c6f65428 bpf: New optimization pass for eliminating unnecessary i32 [...] adds be8bc4f620c bpf: New codegen testcases for 32-bit subregister support adds 249517dbb6f bpf: New disassembler testcases for 32-bit subregister support adds 2d1e0695fb7 [AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC. adds 516e483cb00 [X86] Remove checks for '(scalar_to_vector (i8 (trunc GR32: [...] adds 2ac6ed69e45 [MemorySSA] Remove a redundant dyn_cast. adds 0999c7ce090 Implement equal_range for the DWARF v5 accelerator table adds 62779f87d52 [WebAssembly] Add exception handling option and feature adds b4ef46d3c75 [llvm-objcopy] Fix typo in setSymTab adds 39821cc14f7 Fix build breakage from r326003 adds 7fead298976 [AMDGPU] Shrinking V_SUBBREV_U32 adds a48c00f3cd6 [X86] Use SelectionDAG::getNot instead of implementing manu [...] adds 4e224d83a44 [X86] Remove GCCBuiltin from some intrinsics that are no lo [...] adds ac191b66125 [Sparc] Return true in enableMultipleCopyHints(). adds 8bf1dd6e6c3 Fix spelling in comment. NFCI. adds 15304d05535 [X86][SSE] combineSubToSubus - begun generalizing to work w [...] adds 1c4ef1a42c1 [X86][SSE] combineSubToSubus - support v8i32 handling from [...] adds e1ebc3762f0 [X86][SSE] combineSubToSubus - support v8i64 handling from SSSE3 adds 29d038b31c8 [DebugInfo] Fix buildbot failure on non-X86 targets adds 796005d4a19 Revert "StructurizeCFG: Test for branch divergence correctly" adds a722c841ff6 [X86] Remove GCCBuiltin from some intrinsics that are no lo [...] adds 525aa021156 [X86] Allow int_x86_sse2_cvtps2dq and int_x86_avx_cvt_ps2dq [...] adds ad53ca98c6b [X86] Add cvt tests to avx512vl-intrinsics-fast-isel.ll adds abdbbd51857 [TargetLowering] SimplifyDemandedVectorElts - pass demanded [...] adds 5c1e879c2ea [TargetLowering] SimplifyDemandedVectorElts - pass demanded [...] adds 2e0c67b3afc [X86] Use SDNode instead of SDPatternOperator. NFC adds d2f46f5fc11 [InstSimplify] Remove unused parameter from test cases. adds 1cb64026709 [InstSimplify] Add test cases for removal of vector fabs on [...] adds 5d5077be881 [DebugInfo] Stable sort symbols to remove non-deterministic [...] adds 748f3558aea TableGen: Remove Init::resolveListElementReference adds a410bf62830 TableGen: Get rid of Init::getFieldInit adds 45020d1ff38 TableGen: Remove VarInit::getFieldType adds 9db7d1d7a5d [X86] Remove VT.isSimple() check from detectAVGPattern. adds e700b0d6508 [X86] Simplify the ReplaceNodeResults code for X86ISD::AVG. adds 160e60e1800 [X86] Use SelectionDAG::SplitVectorOperand to simplify some [...] adds 6c409226e67 [X86] Don't use getZExtValue when we have no idea how large [...] adds f7e09e372b5 [SCEV] Extends the SCEVInitRewriter adds e47aa68291a [X86] Add avx1 command line to madd.ll to show splitting an [...] adds ae31e8edc87 [XCore] Return true in enableMultipleCopyHints(). adds edde6812b42 [SCEV] Introduce SCEVPostIncRewriter adds ac0361ce6be [SCEV] Factor out getUsedLoops adds 07ea57a569f The final step to close D41278 [MachineCombiner] Improve de [...] adds ae9a8b01c3a [LoopInterchange] Loops with empty dependency matrix are safe. adds 7d8797ce69b [LoopInterchange] Add test case for D43236. adds 3f10059feb4 [LV] Move isLegalMasked* functions from Legality to CostModel adds ecfbbe9f5fe [WebAssembly] Relax constexpr for old standard libraries. adds 3abbc00c8f0 [Support] Replace HashString with djbHash. adds 8f7bcdf3c65 Revert "[Support] Replace HashString with djbHash." adds cb87bd5252c Test commit adds 27467f8301d [LiveIntervals] Handle moving up dead partial write adds f157381aa28 [AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader adds d0a7e290599 Re-land: "[Support] Replace HashString with djbHash." adds d76cd98cbe8 [gtest] Add PrintTo overload for StringRef. adds bf0378a7115 [X86][SSE] Regenerate PSAD tests adds 454e6dcd0d7 [CodeGen] Don't omit any redundant information in -debug output adds ccc0e67691e Revert r326092: [gtest] Add PrintTo overload for StringRef. adds d403336ea9c [X86][AVX] Add AVX1 PSAD tests adds 1516d0af245 [InstCombine] allow fdiv folds with less than fully 'fast' ops adds ca0bccecf59 AMDGPU/GlobalISel: Make f64 constants legal adds b1af701a7ae [X86][AVX] createPSADBW - support 256-bit cases on AVX1 via [...] adds cc03b6aaf8d [LTO] Support filtering by hotness threshold adds 3d8b511bc0d [ADT] Simplify and optimize StringSwitch adds f1f02e34556 [InstCombine] Switch to using FileCheck instead of grep. Au [...] adds e1ded312c92 [InstCombine] Add test cases with vector constants to fpextend.ll adds b4efe59b693 [SLP] Added new test + fixed some checks, NFC. adds ca6758faef6 [X86] Add a custom legalization for (i16 (bitcast v16i1)) a [...] adds 26256319f9b opt-viewer: output index first adds 5b857c139e5 opt-viewer: also find thinlto opt.yaml files adds 2ee19a308fd [opt-viewer] Set title for the source pages adds bd8ae82c637 opt-diff: Support splitting to multiple output files adds 177552c699e [opt-viewer] Kill parser processes before moving onto rendering adds ddeb8816496 [X86] Add constant folding to combineMOVMSK. adds 35b540858f9 [DebugInfo] Remove target-specific instructions in test adds 0eea35a6ef0 [X86][SSE] Reduce FADD/FSUB/FMUL costs on later targets (PR36280) adds b3dee20a05b [ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to ha [...] adds beeab253916 [GISel]: Don't assert when constraining RegisterOperands wh [...] adds c826b828a4b [AArch64] Harden test cases adds 6555592c60a [InstCombine, InstSimplify] add tests with undef elements i [...] adds e3edb330501 [SelectionDAG] Remove code from PromoteIntRes_CONCAT_VECTOR [...] adds e47bd78db11 Fix PR36032, PR35432 adds f0454dcc5c8 Fix r326154 buildbots test fail adds 90543537f8e [X86] Replace an impossible if condition with an assert. adds c5865b79828 Make test agnostic to cost model adds 99b10edc6bd [X86] Simplify if condition. NFC adds 8734c750f55 [SCEV] Cleanup SCEVInitRewriter. NFC. adds 5e3523b0c8a [MemorySSA] Call the correct dtors adds cbd8b040ccb [MemorySSA] Invalidate def caches on deletion adds f7530a8f19e [SystemZ] Make sure SelectCode() is not called on a target [...] adds 832f2bf0d89 [NewGVN] Update phi-of-ops def block when updating existing [...] adds 2fe27c3ceb0 [ADT] Recognize ppc as valid architecture in target triple. adds c4c59c309ef [dsymutil][test] Add PowerPC test adds a886e2f85a0 Don't output bitcode to stdout in 2002-07-31-SlashInString.ll test adds b0b9884d4b3 Make the LLParser accept call instructions of variables in [...] adds 7a69936ceee [X86][AVX] combineLoopMAddPattern - support 256-bit cases o [...] adds 1bfec906a8c Re-enable "[MachineCopyPropagation] Extend pass to do COPY [...] adds f3fd5aef8cd [GISel]: Print more fallback information when aborting adds dcf9b1dd5ec [AArch64] add SLP test based on TSVC; NFC adds 1dedb741f3e [Hexagon] Add patterns for compares of i1 values adds 69cad521774 [ARM] add loop vectorizer test based on 482.sphinx3 from SP [...] adds 5b43e9e5b83 [X86] Move the load folding tables to a separate .inc file adds 8933ad2b9a2 ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the a [...] adds 94aeacc62f8 Revert r326225 "[X86] Move the load folding tables to a sep [...] adds f521abc300c [dsymutil] Skip DW_AT_sibling attributes. adds 575b2908bc3 [ARM] Another f16 litpool fix adds 3c6e03477e5 [ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to lo [...] adds e7253558054 [InstSimplify] add tests for FP with undef operand; NFC adds b6648311d7d llvm-cvtres: Mention ARM64 as a supported machine type in t [...] adds baca9518bc3 [llvm-cvtres] Update the help test after SVN r326244. adds 3ec0e3212d9 AMDGPU: Add fast fmaf feature to gfx702 adds b4b791692a1 [codeview] Remove unused variable adds a2dabad6511 [AsmPrinter] Handle qualified unnamed types in CodeView printer adds 3f9418b9626 [Pipeliner] Drop memrefs instead of creating ones with size [...] adds c1836df55e5 Revert "[Pipeliner] Drop memrefs instead of creating ones w [...] adds 0ecafe8f605 [CodeView] Lower __restrict and other pointer qualifiers correctly adds 48acebcee02 [Pipeliner] Drop memrefs instead of creating ones with size [...] adds 6981292f43e [Hexagon] Recognize more sign-extensions as inputs to 32x32 [...] adds e14b24839ce [WebAssembly] Remove DataSize from linking metadata section adds ddf3aca34a1 update_mir_test_checks: Drop support for vreg block checks adds 60285814ddb update_mir_test_checks: Use the regexes from UpdateTestChec [...] adds d53cdbf4cc5 [RuntimeDyld][MachO] Support ARM64_RELOC_BRANCH26 for BL in [...] adds 820fd02e9a6 [SLP] Added new tests and updated existing for jumbled load, NFC. adds 92bb38f3945 [ARM] Cortex-A57 scheduler fix for ARM backend (missed 16-b [...] adds d8df57d5ede [X86] Change the masked FPCLASS implementation to use AND i [...] adds 88a555f700e [X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 resul [...] adds 58f8c5d01d2 [RISCV] Update two tests after r326208 adds 9a6e78e4adc [GlobalIsel][X86] Support G_PTRTOINT instruction. adds dfc9aa7f4ed [Dominators] Remove verifyDomTree and add some verifying fo [...] adds 33f95e74032 [IR] - Make User construction exception safe adds 5de243758f7 [MergeICmp] Fix a bug in MergeICmp that can lead to a block [...] adds ed2b4e5df90 Fix typo. NFC adds a03f4fad0d7 [GlobalIsel][X86] Support G_INTTOPTR instruction. adds a11745b7711 [mips] Begin reworking instruction predicates for ISAs/enco [...] adds c28e9497695 [WebAssembly] Fix copy-paste error in debugging string adds 61e1774e4ed [DEBUGINFO] Add flag for DWARF2 or less to use sections as [...] adds 2f11a75319f [InstCombine] move constant check into foldBinOpIntoSelectO [...] adds 8053b777d69 [InstCombine] move invariant call out of loop; NFC adds 548f25596d8 [InstCombine] auto-generate complete checks; NFC adds efd80a619fd [ARM] Lower lower saturate to 0 and lower saturate to -1 us [...] adds 15d6598bc2c [WebAssembly] Reorder symbol table to match MC order adds 70716e54e03 [TLS] use emulated TLS if the target supports only this mode adds 8e63a838087 [GlobalISel] Print/Parse FailedISel MachineFunction property adds 0cbbf04d215 [NVPTX] Removed always-true predicates in NVPTX. adds 4ed7d96c887 [InstrProfiling] Emit the runtime hook when no counters are [...] adds 06a2673a69d Fixed spelling mistake in comments of LLVM Analysis passes adds e24854a5622 [AMDGPU] added writelane intrinsic adds daf29462238 Fix llvm-config --system-libs output on FreeBSD and NetBSD adds 0b9902149c5 Losen time contraint to accommodate system loads adds fb3a6289fbb [InstCombine] Split the FP constant code out of lookThrough [...] adds 48f2182b78c [Hexagon] Implement target feature +reserved-r19 adds a0a6553f0e8 [X86][AVX512] Improve support for signed saturation truncat [...] adds 26e70a7a840 [X86] Lower extract_element from k-registers by bitcasting [...] adds ad4af60b673 [GlobalOpt] don't change CC of musttail calle(e|r) adds 31904278251 [InstCombine] simplify code for X * -1.0 --> -X; NFC adds 98acc6a7132 [X86] Regenerate cmpxchg tests adds 9b622654711 build: add the ability to create a symlink for dsymutil adds 870be0c8823 [MIRParser] Accept overloaded intrinsic names w/o type suffixes adds 1d2683f5a07 [NVPTX] Use addrspacecast instead of target-specific intrin [...] adds 5ee5a7c21e9 [NVPTX] Lower loads from global constants using ld.global.n [...] adds 2d3c0b9d281 [X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a [...] adds b3505fe2661 [DAE] don't remove args of musttail target/caller adds 9161b0eb011 [DWARF] Emit a split line table only if there are split typ [...] adds 4bd2f44130d [GlobalISel][AArch64] Adding -disable-gisel-legality-check [...] adds bb55f795cb9 [IPSCCP] do not break musttail invariant (PR36485) adds 7db8ad4adc1 [RuntimeDyld][MachO] Fix assertion in encodeAddend, add mis [...] adds 26e6f68bfc3 [XRay] cache symbolized function names for a repeatedly que [...] adds 8c1abc4ccbe [Support] Fix comments for handleAllErrors: it calls llvm_u [...] adds 0cd046c5f10 [X86] Stop passing two arguments by reference. NFC adds 1eba8752d75 [SCEV] Smart range calculation for SCEVUnknown Phis adds e993fb5d704 [dsymutil] Move string pool into its own implementatino file. NFC. adds fba557f60d5 [SCCP] Fix unused variable warning in release builds. adds 1575cf3f594 [CodeGen] fix argument attribute in lowering statepoint/patchpoint adds 496a36b4ec5 Revert "[DEBUGINFO] Add flag for DWARF2 or less to use sect [...] adds 196ad9c0b6a [InstCombine] auto-generate full checks; NFC adds 6d9b2bf0a78 [InstCombine] move/add tests for fmul reassociation; NFC adds 85e3087c68c [AArch64] generate vuzp instead of mov adds 2648a57b6f0 [InstCombine] simplify code for (X*Y) * X => (X*X) * Y ; NFCI adds 2d7eccead16 [WebAssembly] Update pre-generated test files to match late [...] adds 275248c058e [Power9] Add missing instructions to the Power 9 scheduler adds 9658ecff60f [InstCombine] remove stale comments for tests; NFC adds 4c5d04911d0 [Hexagon] Add guest registers adds 4a773acdd6b [AMDGPU] : fix for the crash in SIRegisterInfo when the reg [...] adds 92024e8c0f2 [PDB] Defer writing the build id until the rest of the PDB [...] adds 9f474dee9e0 [WebAssembly] Use uint8_t for single byte values to match the spec adds 94fae94e42d [NVPTX] use pattern matching to lower int_nvvm_match_all_sync*. adds 182921352f0 [WebAssembly] Fix broken gcc build after rL326454 adds 41f826cda5c AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal adds 7537e26848d AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal adds 5b58d668a10 AMDGPU/GlobalISel: Make i32 xor legal adds 3e435c46b5a AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copies adds e4d2cea91d0 AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANT adds 435d0a8937c AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF adds 78411cf8946 AMDGPU/GlobalISel: Make i32 mul legal adds 92b4d60ae07 AMDGPU/GlobalISel: Define InstrMappings for G_ICMP adds da1bb1955d8 [InstCombine] Auto-generate complete checks. NFC adds 1169a4ba3e6 [SimplifyLibCalls] Update an obviously copy and pasted head [...] adds bc5e95e9a99 AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.exp adds e82f69197bc AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr adds 8c77607fcb9 [AArch64] Add support for secrel add/load/store relocations [...] adds df1563c1768 AMDGPU/GlobalISel: Mark i32->i64 zext as legal adds e9e42e8917b AMDGPU/GlobalISel: Define instruction mapping for G_BITCAST adds d585dc129e5 AMDGPU/GlobalISel: Use a more correct getValueMapping adds c60a6dbbb16 [X86][SSE] Regenerate odd sized sext/zext tests adds f633076fd1a [AArch64] Clean up code (NFC) adds 72d58f8a940 AMDGPU/GlobalISel: Remove default register mapping adds 679df750a90 [X86][SSE] Regenerate float to/from i8/i16 vector tests adds 9fcecef7269 AMDGPU/GlobalISel: Define instruction mapping for G_OR adds 05580dd9e5a AMDGPU/GlobalISel: Define instruction mapping for @llvm.amd [...] adds 47ab8607496 Add an llc testcase analogous to test/LTO/X86/strip-debug-info.ll adds 00ee23b31fb [Hexagon] Add trap1 instruction adds c921f23f8e4 [X86][AVX] Add v2f32 <-> v2i8/v2i16/v2i32 vector tests adds c5a680a5cc6 [SelectionDAG] Support some SimplifySetCC cases for compari [...] adds b755ca31087 [X86][MMX] Improve handling of 64-bit MMX constants adds 5af2fadb044 [DAGCombiner] When combining zero_extend of a truncate, onl [...] adds 5bd1ce0c5d6 [InstCombine] allow fmul fold with less than 'fast' adds 0e0047f8c9a bpf: introduce -mattr=dwarfris to disable DwarfUsesRelocati [...] adds 76263322b9b revert r326502: [InstCombine] allow fmul fold with less tha [...] adds d79d6661eea [Reassociate] regenerate checks; NFC adds 49894f87477 [InstCombine] allow fmul fold with less than 'fast' adds 185ee30a67b [InstCombine] Simplify test cases by removing loads/stores [...] adds a8353210f05 Utility functions for checked arithmetic adds 6842a7cf3be [ArgumentPromotion] don't break musttail invariant PR36543 adds c6e497a44fa [WebAssembly] Gather EH instructions in one place. NFC. adds 8f583a24ce7 AMDGPU/GlobalISel: Define instruction mapping for G_AND adds 95f12ebe5c1 AMDGPU/GlobalISel: Define instruction mapping for G_XOR adds 52088d0a5fb AMDGPU/GlobalISel: Define instruction mapping for G_SHL adds 6f9952dce35 AMDGPU/GlobalISel: Define instruction mapping for G_FADD adds 24a5c742865 [InstCombine] Add more test case to fpextend.ll. adds f3dbef61bdc AMDGPU/GlobalISel: Define instruction mapping for G_FMUL adds 3ec91dfb663 AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUI adds 0e5b4bc59ce AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSI adds 738d9f98592 AMDGPU/GCN: Promote i16 ctpop adds 76899c61ced [ThinLTO] Added a couple of C LTO API interfaces to control [...] adds 587a2e31eca [WebAssembly] More uses of uint8_t for single byte values adds 28835ca04aa [X86] Remove old UNIMPLEMENTED list adds de514539f2c AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnum adds 9b9abcabb25 [LV][CFG] Add irreducible CFG detection for outer loops adds 98079e294f7 [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB adds 193aea37823 [WebAssembly] Update tests after r326541 adds 56748f70fc0 Revert "[WebAssembly] More uses of uint8_t" and "[WebAssemb [...] adds ad02fe3ca59 Test commit: Remove an extraneous space. NFC adds b4acd1e0d7f [MergeIcmps] Add the test case from PR36557. adds af45cfce8be [MergeICmps] Revert 324317 "Enable the MergeICmps Pass by d [...] adds de074060947 [Docs] Add LLVM for Grad Students to Contributing page. adds 22b62dafe43 [WebAssembly] Check function type indexes adds 133ed5ce589 [Power9] Add missing instructions to the Power 9 scheduler adds c2b8dd7e70b [MergeICmps] Revert accidentally submitted failing test case. adds 435d2bb58b6 [ARM] Fix access to stack arguments when re-aligning SP in Armv6m adds a0af6ca70c1 LoopUnroll: respect pragma unroll when AllowRemainder is disabled adds 78bc395115c AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnum adds 8030f1eaa30 AMDGPU/GlobalISel: Define InstrMappings for G_FCMP adds 4f133997d74 AMDGPU/GlobalISel: InstrMapping for G_TRUNC adds 73675f1a18c AMDGPU/GlobalISel: InstrMapping for G_ZEXT adds 94497ced3c5 [utils] Add utils/update_cc_test_checks.py adds d4f9b5813a2 [ARM] Fold variable into assert. adds 442f953b4e2 [X86][x32] Save callee-save register used as base pointer f [...] adds 5391b3c8a02 [InstCombine] Allow fptrunc (fpext X)) to be reduced to a s [...] adds 5227b3b7225 [X86] Reject xmm16-31 in inline asm constraints when AVX512 [...] adds b24d041bc8b [X86][BTVER2] Fix throughput of YMM bitwise instructions adds c796919b068 [Hexagon] Handle VACOPY in isel lowering adds 1629c23be73 [PatternMatch, InstSimplify] fix m_NaN to work with vector [...] adds d9244421860 Fix more spelling mistakes in comments of LLVM Analysis passes adds 70e6111d373 [InstCombine] add tests for rL169025; NFC adds a1ef0f7b4bc [InstCombine] partly fix FMF for fmul+log2 fold adds 43f4824b432 [SystemZ] Support vector registers in inline asm adds 47485670fc5 [SystemZ] Fix common-code users of stack size adds 12d84e5a682 [SystemZ] Support stackmaps and patchpoints adds a8eca2749c3 [SystemZ] Add support for anyregcc calling convention adds 612391f666a [SystemZ] Allow LRV/STRV with volatile memory accesses adds 53612a9f2c8 Reland "[WebAssembly] More uses of uint8_t for single byte values" adds 04291dcce7f [SystemZ] Fix test cases after r326613 adds 693cdb0ab50 [InstCombine] Rewrite the binary op shrinking in visitFPTru [...] adds b9e93872df3 [WebAssembly] Avoid cast ExprType to wasm::ValType adds 3ca5091556a [unittests] Make some parseIR calls more readable, NFC adds 40131a7149e [Utils] Salvage debug info in recursive inst deletion adds 88bc91ded96 Make llvm::djbHash an inline function. adds 4959ec1bd35 [RISCV] Implement MC relaxations for compressed instructions. adds 8d87916e25e [Hexagon] Generate valignb for shifting shuffles (instead o [...] adds a931186c9a3 [Utils] Salvage debug info in block simplification adds d92be751358 [llvm-symbolizer] Use correct path when resolving .gnu_debu [...] adds 03749de4b04 Add DBG_VALUE support to the linear DAG scheduler adds 027535e24a3 [InstCombine] rearrange visitFMul; NFCI adds 5106e83eebc [AggressiveInstCombine] Use use_empty() instead of !getNumU [...] adds d94dad6774c Implementation of MRI "delete" command. adds c6318cb943b [LegalizeVectorTypes] When scalarizing the operand of a una [...] adds b19562565e4 [ThinLTO] Revert r325320: Import global variables adds 01fcdec33ed [X86] Remove 'else' after return. NFC adds 097c341c342 [X86] This bit-test TODO has been moved in PR36551 adds 66b954c4b45 [InstCombine] add tests for notnotsub; NFC adds 80d9b90c340 [InstCombine] (~X) - (~Y) --> Y - X adds 71890c251a4 [InstCombine] add test for vectors with undef elts; NFC adds 03afaa3e4e0 [CallSiteSplitting] properly split musttail calls adds 5833be28b66 [CallSiteSplitting] fix use after-free adds 607f701c178 [X86] Lower v1i1/v2i1/v4i1/v8i1 load/stores to i8 load/stor [...] adds b22968f52c8 [X86] Combine (store (v1i1 (scalar_to_vector (i8 X)))) -> ( [...] adds fbeb5d7e1a8 [X86] Fix unused variable in release builds. adds b50f782465c [X86][MMX] Remove completed _mm_cvtsi32_si64 todo adds 465d3cf9d78 [X86][X87] Add X87 folded integer arithmetic tests adds bc41688d2c2 [DAGCombiner] Add a peekThroughBitcast to MergeStoresOfCons [...] adds 158b2d646dd [X86] Add a 32-bit mode command line to avx512-mask-op.ll. [...] adds c3854cbc57a [X86] Add a DAG combine to turn stores of vXi1 constants in [...] adds 82c499e4327 [X86] Replace usages of X86Subtarget::hasFp256 with hasAVX. [...] adds a6e171db6c2 [MergeICmps][NFC] Improve logging. adds fce2d38e397 [Bash-autocompletion] Pass all flags in shell command-line [...] adds 17209fa8d77 Fix location of comment in EmitPopInst adds 54767673da1 [WebAssembly] Attach a name to globals similarly to functio [...] adds a60bc625ceb [WebAssembly] Fix tests with invalid yaml (required CODE se [...] adds 022e5fa26f9 [WebAssembly] Reorder reloc sections to come between symtab [...] adds 4a9afc559e4 [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers adds e0316ce24e5 [WebAssembly] Add validation to reloc section adds ec1d1788ce5 [MergeICmp] We can discard initial blocks that do other work adds 8cb107dbb81 TableGen: Use DefInit::getDef() instead of the type's getRecord() adds f3b54ef25c0 TableGen: Allow NAME in template arguments in defm in multiclass adds 9355e1b3893 [Power9] Add more missing instructions to the Power 9 scheduler adds 77d8d0a7e72 Pass Divergence Analysis data to Selection DAG to drive div [...] adds efff70ac28a TableGen: Introduce an abstract variable resolver interface adds d5cc0e077d6 TableGen: Reimplement !foreach using the resolving mechanism adds 73eed0f1afd TableGen: Resolve all template args simultaneously in AddSubClass adds 83f929b89a9 TableGen: Resolve all template args simultaneously in AddSu [...] adds 1e9feb80869 TableGen: Resolve all template args simultaneously in Resol [...] adds 0bc0dbe2f14 Fuzzer: remove temporary files after we're done with them. adds f74e20351f9 [CVP] fix formatting; NFC adds 14281925243 AMDGPU: Fix build warning about override adds 4e77263fcb9 AMDGPU/GlobalISel: Make some G_EXTRACTs legal adds f246669c105 AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT adds 31f34398092 [MachineScheduler] Dump SUnits before calling SchedImpl->in [...] adds da323855eb8 [AArch64] Improve code generation of constant vectors adds dafcef6848c [IPSCCP] Add getCompare which returns either true, false, u [...] adds c29d5318975 fix PR36582 adds 0caccbe952f Make STATISTIC() values available programmatically adds eafb434169f [AArch64] Harden test case adds 233963b1b3b Revert r326723: Make STATISTIC() values available programmatically adds 0ea46fcd2e7 [InstCombine] Add constant vector support to getMinimumFPTy [...] adds cd60d849598 [InstCombine] Don't blow up in foldICmpWithCastAndCast on v [...] adds d894b748801 [llvm-pdbdump] Dump restrict type qualifier adds 17efee5afa0 Fix an unused variable warning introduced by rr326703. NFC adds bf9c7d5f95f On Windows expansion of regex file name patterns is the res [...] adds d56c255db74 [x86] auto-generate full checks for fabs tests adds 8ddeb60876d [PowerPC] Do not emit record-form rotates when record-form [...] adds 21cc5d93b2a On Windows we need to be able to process response files wit [...] adds a3170b6798c Re-commit: Make STATISTIC() values available programmatically adds 7c6f31a848f [SLP] Additional tests for stores vectorization, NFC. adds 1a5e5a74909 [AVR] Fix the test suite after r326500. adds d4a52d5d0c3 [AMDGPU] Remove unused AMDOpenCL triple environment adds c637af82e01 [X86] Add silvermont fp arithmetic cost model tests adds 21f9a71326f [RewriteStatepoints] Fix stale parse points adds a55b77d1b55 GlobalISel: IRTranslate llvm.fabs.* intrinsic adds 6ee3582153e [InstSimplify] remove redundant folds adds b0a61e889c1 [X86] cvttpd2dq lowering has been supported for some time adds 5ac350a859c Disable llvm-opt-fuzzer/exec-options.ll on Windows, it is t [...] adds 13c8f235f10 [DWARFv5] Emit file 0 to the line table. adds 806f65e3f52 [MergeICmp] Fix printing. NFC adds 434547e0c59 [MergeICmp] Simplify how BCECmpBlock instructions are blacklisted adds bc322249805 Revert "[DWARFv5] Emit file 0 to the line table." Caused an [...] adds 6dbdbdd86ab Updated docs in CrashRecoveryContext.h adds ea4dd0b9197 [X86] Handle EAX being live when calling chkstk for x86_64 adds 068c05aeb45 [WebAssebmly] Remove reloc ordering constraint adds 783006ec198 [DebugInfo] Discard invalid DBG_VALUE instructions in LiveD [...] adds d45c0f1adf5 [AVR] Remove the earlyclobber flag from LDDWRdYQ adds 6fdde843d64 [CloneFunction] Support BB == PredBB in DuplicateInstructio [...] adds 866cf8f3afa Fixup for rL326769 (RegState::Debug is being truncated to a bool) adds c1dad069688 TableGen: Generalize record types to fix typeIsConvertibleT [...] adds c1b25e68566 TableGen: Simplify BitsInit::resolveReferences adds a9e8c1d6098 TableGen: Allow !cast of records, cleanup conversion machinery adds 19ebaa70e52 TableGen: Explicitly check whether a record has been resolved adds ea80ae41c7c TableGen: Move getNewAnonymousName into RecordKeeper adds 1f3e2338d93 TableGen: Delay instantiating inline anonymous records adds 33774b4ded5 TableGen: Remove the ResolveFirst mechanism adds 8498a493c81 TableGen: Add !foldl operation adds dc7756a32cd [CallSiteSplitting] Do not crash when BB's terminator changes. adds 3c24f8abd86 [Asm] Refactor debug printing of AsmToken adds 2fb672c0b90 [Asm] Add debug printing for assembler macros adds 2a9d5b1b030 test commit: fix typo in comment adds 0cf7d296a2f [ARM]Decoding MSR with unpredictable destination register c [...] adds fc942931a47 [ARM][Asm] Fix layering violation introduced by r326795 adds 2d74623e2e1 [AMDGPU] Fix lowering OpenCL enqueue_kernel adds 751bada62c8 [Pipeliner] Test commit: fixed spelling mistake in comments adds 193fdf67307 [Asm] Fix another layering violation in assmebly macro dumping adds b3f3c6b474d [AArch64] define isExtractSubvectorCheap adds 3c992c643ca [ValueTracking] move helpers for SelectPatterns from InstCo [...] adds da57ded77c9 Refactor check for dllimport in the Verifier. adds c63c5c660f4 [PatternMatch] define m_Not using m_Xor and cst_pred_ty adds 9ac1b3521a5 [CodeView] Emit UdtSourceLine information for enums adds 0dc2b94c4e9 [AMDGPU] Add default ISA version targets adds 6a7d6881f0a [X86] Reject registers that require a REX prefix in inline [...] adds a05c22c9e81 [InstCombine] simplify min/max canonicalization; NFCI adds 195a164675a [Hexagon] Remove {{ *}} from testcases new fb4ee0d83c5 Creating branches/google/stable and tags/google/stable/2018 [...]

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .arcconfig | 1 + CMakeLists.txt | 28 +- CREDITS.TXT | 7 +- bindings/go/README.txt | 8 + bindings/go/llvm/ir.go | 2 +- bindings/ocaml/llvm/llvm.mli | 2 +- cmake/modules/AddLLVM.cmake | 4 +- cmake/modules/CrossCompile.cmake | 3 + cmake/modules/HandleLLVMOptions.cmake | 24 + cmake/modules/LLVMConfig.cmake.in | 2 + cmake/modules/LLVMExternalProjectUtils.cmake | 14 +- cmake/modules/LLVMInstallSymlink.cmake | 2 +- cmake/modules/LLVMProcessSources.cmake | 2 +- docs/AMDGPUUsage.rst | 268 +- docs/AdvancedBuilds.rst | 2 +- docs/BitCodeFormat.rst | 17 +- docs/CMake.rst | 12 + docs/CodeGenerator.rst | 2 +- docs/CodingStandards.rst | 65 +- docs/CommandGuide/dsymutil.rst | 15 + docs/CommandGuide/llc.rst | 2 +- docs/Contributing.rst | 15 +- docs/ExceptionHandling.rst | 63 + docs/Extensions.rst | 63 + docs/GettingStarted.rst | 4 +- docs/HowToSubmitABug.rst | 2 +- docs/LangRef.rst | 181 +- docs/LibFuzzer.rst | 6 +- docs/MIRLangRef.rst | 23 +- docs/MemorySSA.rst | 2 +- docs/PDB/MsfFile.rst | 82 +- docs/Passes.rst | 15 + docs/Phabricator.rst | 16 +- docs/ReleaseNotes.rst | 4 + docs/ReleaseProcess.rst | 139 +- docs/TableGen/LangIntro.rst | 47 +- docs/TableGen/LangRef.rst | 2 +- docs/Vectorizers.rst | 9 - docs/doxygen.cfg.in | 2 +- docs/tutorial/BuildingAJIT1.rst | 5 + docs/tutorial/BuildingAJIT2.rst | 5 + docs/tutorial/BuildingAJIT3.rst | 5 + docs/tutorial/LangImpl04.rst | 2 +- docs/tutorial/LangImpl08.rst | 2 +- docs/tutorial/OCamlLangImpl1.rst | 2 +- examples/BrainF/BrainFDriver.cpp | 2 +- .../BuildingAJIT/Chapter1/CMakeLists.txt | 1 + .../BuildingAJIT/Chapter1/KaleidoscopeJIT.h | 57 +- .../BuildingAJIT/Chapter2/CMakeLists.txt | 1 + .../BuildingAJIT/Chapter2/KaleidoscopeJIT.h | 64 +- .../BuildingAJIT/Chapter3/KaleidoscopeJIT.h | 69 +- .../BuildingAJIT/Chapter4/KaleidoscopeJIT.h | 69 +- .../BuildingAJIT/Chapter5/KaleidoscopeJIT.h | 74 +- examples/Kaleidoscope/Chapter4/CMakeLists.txt | 1 + examples/Kaleidoscope/Chapter5/CMakeLists.txt | 1 + examples/Kaleidoscope/Chapter6/CMakeLists.txt | 1 + examples/Kaleidoscope/Chapter7/CMakeLists.txt | 1 + examples/Kaleidoscope/Chapter9/CMakeLists.txt | 1 + examples/Kaleidoscope/include/KaleidoscopeJIT.h | 56 +- examples/ModuleMaker/ModuleMaker.cpp | 2 +- include/llvm-c/Core.h | 23 +- include/llvm-c/OrcBindings.h | 2 +- include/llvm-c/Types.h | 2 +- include/llvm-c/lto.h | 28 +- include/llvm/ADT/APInt.h | 2 +- include/llvm/ADT/BitVector.h | 7 +- include/llvm/ADT/GraphTraits.h | 20 + include/llvm/ADT/Optional.h | 176 +- include/llvm/ADT/STLExtras.h | 6 + include/llvm/ADT/ScopeExit.h | 16 +- include/llvm/ADT/SmallVector.h | 9 +- include/llvm/ADT/SparseMultiSet.h | 2 +- include/llvm/ADT/SparseSet.h | 3 +- include/llvm/ADT/Statistic.h | 27 +- include/llvm/ADT/StringExtras.h | 13 - include/llvm/ADT/StringMap.h | 20 +- include/llvm/ADT/StringRef.h | 10 + include/llvm/ADT/StringSwitch.h | 173 +- include/llvm/ADT/Triple.h | 10 +- include/llvm/Analysis/CFG.h | 67 + include/llvm/Analysis/CGSCCPassManager.h | 2 +- include/llvm/Analysis/CallGraph.h | 9 + include/llvm/Analysis/DivergenceAnalysis.h | 4 + include/llvm/Analysis/InlineCost.h | 2 +- include/llvm/Analysis/LazyValueInfo.h | 7 + include/llvm/Analysis/LoopIterator.h | 19 + include/llvm/Analysis/MemorySSA.h | 28 +- include/llvm/Analysis/PostDominators.h | 5 +- include/llvm/Analysis/PtrUseVisitor.h | 2 +- include/llvm/Analysis/RegionInfo.h | 2 +- include/llvm/Analysis/ScalarEvolution.h | 19 +- include/llvm/Analysis/ScalarEvolutionExpressions.h | 4 +- include/llvm/Analysis/SyntheticCountsUtils.h | 52 + include/llvm/Analysis/TargetTransformInfo.h | 20 +- include/llvm/Analysis/TargetTransformInfoImpl.h | 4 + include/llvm/Analysis/ValueLattice.h | 123 +- include/llvm/Analysis/ValueTracking.h | 20 +- include/llvm/AsmParser/Parser.h | 16 +- include/llvm/BinaryFormat/COFF.h | 3 + include/llvm/BinaryFormat/Dwarf.def | 37 +- include/llvm/BinaryFormat/Dwarf.h | 17 +- include/llvm/BinaryFormat/ELF.h | 146 +- include/llvm/BinaryFormat/Wasm.h | 126 +- include/llvm/Bitcode/BitcodeWriter.h | 8 +- include/llvm/Bitcode/LLVMBitCodes.h | 28 +- include/llvm/CodeGen/AccelTable.h | 373 + include/llvm/CodeGen/AsmPrinter.h | 16 +- include/llvm/CodeGen/BasicTTIImpl.h | 4 +- include/llvm/CodeGen/CommandFlags.def | 25 +- include/llvm/CodeGen/DwarfStringPoolEntry.h | 2 + include/llvm/CodeGen/ExecutionDepsFix.h | 230 - include/llvm/CodeGen/ExecutionDomainFix.h | 213 + include/llvm/CodeGen/FunctionLoweringInfo.h | 11 + include/llvm/CodeGen/GlobalISel/Combiner.h | 43 + include/llvm/CodeGen/GlobalISel/CombinerHelper.h | 44 + include/llvm/CodeGen/GlobalISel/CombinerInfo.h | 48 + .../llvm/CodeGen/GlobalISel/InstructionSelector.h | 32 +- .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 74 +- .../GlobalISel/LegalizationArtifactCombiner.h | 20 +- include/llvm/CodeGen/GlobalISel/LegalizerInfo.h | 591 +- include/llvm/CodeGen/GlobalISel/MIPatternMatch.h | 314 + include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 45 + include/llvm/CodeGen/GlobalISel/RegBankSelect.h | 2 +- include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 2 + include/llvm/CodeGen/GlobalISel/Utils.h | 16 +- include/llvm/CodeGen/ISDOpcodes.h | 1 + include/llvm/CodeGen/LiveRangeEdit.h | 14 +- include/llvm/CodeGen/LiveRegMatrix.h | 7 + include/llvm/CodeGen/LoopTraversal.h | 116 + include/llvm/CodeGen/MIRYamlMapping.h | 2 + include/llvm/CodeGen/MachineBasicBlock.h | 7 +- include/llvm/CodeGen/MachineDominators.h | 6 - include/llvm/CodeGen/MachineInstr.h | 14 +- include/llvm/CodeGen/MachineInstrBuilder.h | 7 + include/llvm/CodeGen/MachineOperand.h | 80 +- include/llvm/CodeGen/MachineRegisterInfo.h | 30 +- include/llvm/CodeGen/Passes.h | 16 +- include/llvm/CodeGen/ReachingDefAnalysis.h | 118 + include/llvm/CodeGen/RuntimeLibcalls.def | 32 + include/llvm/CodeGen/SelectionDAG.h | 40 +- include/llvm/CodeGen/SelectionDAGAddressAnalysis.h | 2 +- include/llvm/CodeGen/SelectionDAGNodes.h | 24 +- include/llvm/CodeGen/TargetInstrInfo.h | 26 +- include/llvm/CodeGen/TargetLowering.h | 73 +- include/llvm/CodeGen/TargetLoweringObjectFile.h | 3 + .../llvm/CodeGen/TargetLoweringObjectFileImpl.h | 3 + include/llvm/CodeGen/TargetOpcodes.def | 3 + include/llvm/CodeGen/TargetPassConfig.h | 27 +- include/llvm/CodeGen/TargetRegisterInfo.h | 3 + include/llvm/CodeGen/TargetSubtargetInfo.h | 6 + include/llvm/Config/llvm-config.h.cmake | 5 + include/llvm/DebugInfo/CodeView/CVRecord.h | 24 + include/llvm/DebugInfo/CodeView/CVTypeVisitor.h | 2 +- include/llvm/DebugInfo/CodeView/CodeView.h | 2 +- .../DebugInfo/CodeView/GlobalTypeTableBuilder.h | 17 +- include/llvm/DebugInfo/CodeView/TypeRecord.h | 4 + include/llvm/DebugInfo/DIContext.h | 1 + .../llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h | 413 +- include/llvm/DebugInfo/DWARF/DWARFAddressRange.h | 66 + include/llvm/DebugInfo/DWARF/DWARFContext.h | 29 +- include/llvm/DebugInfo/DWARF/DWARFDebugArangeSet.h | 1 + include/llvm/DebugInfo/DWARF/DWARFDebugLine.h | 42 +- include/llvm/DebugInfo/DWARF/DWARFDebugRangeList.h | 43 +- include/llvm/DebugInfo/DWARF/DWARFDebugRnglists.h | 59 + include/llvm/DebugInfo/DWARF/DWARFDie.h | 2 +- include/llvm/DebugInfo/DWARF/DWARFFormValue.h | 16 +- include/llvm/DebugInfo/DWARF/DWARFObject.h | 3 + include/llvm/DebugInfo/DWARF/DWARFUnit.h | 45 +- include/llvm/DebugInfo/DWARF/DWARFVerifier.h | 22 +- include/llvm/DebugInfo/PDB/DIA/DIARawSymbol.h | 21 + include/llvm/DebugInfo/PDB/DIA/DIASession.h | 2 +- include/llvm/DebugInfo/PDB/IPDBRawSymbol.h | 21 + include/llvm/DebugInfo/PDB/IPDBSession.h | 2 +- include/llvm/DebugInfo/PDB/Native/HashTable.h | 165 +- include/llvm/DebugInfo/PDB/Native/InfoStream.h | 2 +- .../llvm/DebugInfo/PDB/Native/InfoStreamBuilder.h | 6 +- include/llvm/DebugInfo/PDB/Native/NamedStreamMap.h | 25 +- .../llvm/DebugInfo/PDB/Native/NativeRawSymbol.h | 21 + include/llvm/DebugInfo/PDB/Native/NativeSession.h | 2 +- .../llvm/DebugInfo/PDB/PDBSymbolTypeFunctionSig.h | 2 + include/llvm/DebugInfo/PDB/PDBTypes.h | 4 +- include/llvm/ExecutionEngine/ExecutionEngine.h | 21 +- include/llvm/ExecutionEngine/JITSymbol.h | 59 +- .../ExecutionEngine/Orc/CompileOnDemandLayer.h | 209 +- include/llvm/ExecutionEngine/Orc/CompileUtils.h | 64 +- include/llvm/ExecutionEngine/Orc/Core.h | 341 + include/llvm/ExecutionEngine/Orc/ExecutionUtils.h | 25 +- include/llvm/ExecutionEngine/Orc/IRCompileLayer.h | 32 +- .../llvm/ExecutionEngine/Orc/IRTransformLayer.h | 30 +- include/llvm/ExecutionEngine/Orc/LambdaResolver.h | 2 +- .../llvm/ExecutionEngine/Orc/LazyEmittingLayer.h | 81 +- include/llvm/ExecutionEngine/Orc/Legacy.h | 138 + include/llvm/ExecutionEngine/Orc/NullResolver.h | 12 +- .../ExecutionEngine/Orc/ObjectTransformLayer.h | 38 +- .../ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h | 244 +- .../llvm/ExecutionEngine/Orc/RemoteObjectLayer.h | 49 +- .../llvm/ExecutionEngine/Orc/SymbolStringPool.h | 41 +- include/llvm/ExecutionEngine/RTDyldMemoryManager.h | 2 +- include/llvm/FuzzMutate/FuzzerCLI.h | 6 + include/llvm/FuzzMutate/OpDescriptor.h | 6 +- include/llvm/IR/Constant.h | 16 + include/llvm/IR/Constants.h | 5 + include/llvm/IR/DIBuilder.h | 67 +- include/llvm/IR/DataLayout.h | 28 +- include/llvm/IR/DebugInfoFlags.def | 3 +- include/llvm/IR/DebugInfoMetadata.h | 213 +- include/llvm/IR/DiagnosticInfo.h | 1 + include/llvm/IR/Dominators.h | 108 +- include/llvm/IR/Function.h | 43 +- include/llvm/IR/GlobalValue.h | 15 +- include/llvm/IR/GlobalVariable.h | 13 +- include/llvm/IR/IRBuilder.h | 225 +- include/llvm/IR/InstrTypes.h | 60 + include/llvm/IR/Instruction.h | 8 + include/llvm/IR/Instructions.h | 1089 +- include/llvm/IR/IntrinsicInst.h | 88 +- include/llvm/IR/Intrinsics.td | 6 +- include/llvm/IR/IntrinsicsAArch64.td | 9 +- include/llvm/IR/IntrinsicsAMDGPU.td | 58 +- include/llvm/IR/IntrinsicsWebAssembly.td | 16 +- include/llvm/IR/IntrinsicsX86.td | 230 +- include/llvm/IR/MDBuilder.h | 9 +- include/llvm/IR/Mangler.h | 3 + include/llvm/IR/Module.h | 7 + include/llvm/IR/ModuleSummaryIndex.h | 323 +- include/llvm/IR/ModuleSummaryIndexYAML.h | 3 +- include/llvm/IR/PatternMatch.h | 340 +- include/llvm/IR/Statepoint.h | 2 +- include/llvm/IR/User.h | 24 +- include/llvm/IRReader/IRReader.h | 9 +- include/llvm/InitializePasses.h | 10 +- include/llvm/LTO/Caching.h | 7 +- include/llvm/LTO/Config.h | 4 + include/llvm/LTO/LTO.h | 20 +- include/llvm/LTO/legacy/ThinLTOCodeGenerator.h | 27 +- include/llvm/MC/MCAsmBackend.h | 2 +- include/llvm/MC/MCAsmMacro.h | 45 + include/llvm/MC/MCCodePadder.h | 2 +- include/llvm/MC/MCCodeView.h | 48 +- include/llvm/MC/MCContext.h | 24 +- include/llvm/MC/MCDwarf.h | 52 +- include/llvm/MC/MCFragment.h | 21 +- include/llvm/MC/MCInstrItineraries.h | 14 +- include/llvm/MC/MCObjectFileInfo.h | 4 + include/llvm/MC/MCObjectStreamer.h | 4 +- include/llvm/MC/MCParser/MCAsmLexer.h | 4 + include/llvm/MC/MCParser/MCTargetAsmParser.h | 1 + include/llvm/MC/MCSchedule.h | 35 +- include/llvm/MC/MCSectionWasm.h | 14 +- include/llvm/MC/MCStreamer.h | 39 +- include/llvm/MC/MCSymbol.h | 27 +- include/llvm/MC/MCSymbolWasm.h | 27 +- include/llvm/MC/MCTargetOptions.h | 1 + include/llvm/MC/MCWinCOFFStreamer.h | 1 + include/llvm/MC/StringTableBuilder.h | 2 +- include/llvm/Object/COFFImportFile.h | 3 +- include/llvm/Object/ELF.h | 8 +- include/llvm/Object/ELFObjectFile.h | 46 +- include/llvm/Object/ELFTypes.h | 45 +- include/llvm/Object/MachO.h | 2 +- include/llvm/Object/ObjectFile.h | 6 - include/llvm/Object/Wasm.h | 103 +- include/llvm/ObjectYAML/WasmYAML.h | 50 +- include/llvm/Option/ArgList.h | 2 + include/llvm/PassAnalysisSupport.h | 2 +- include/llvm/Passes/PassBuilder.h | 13 + include/llvm/ProfileData/InstrProfData.inc | 2 +- include/llvm/ProfileData/SampleProf.h | 15 + include/llvm/Support/Allocator.h | 35 +- include/llvm/Support/BinaryStreamWriter.h | 6 +- include/llvm/Support/CMakeLists.txt | 14 +- include/llvm/Support/CachePruning.h | 4 +- include/llvm/Support/CheckedArithmetic.h | 83 + include/llvm/Support/CrashRecoveryContext.h | 92 +- include/llvm/Support/DJB.h | 33 + include/llvm/Support/Error.h | 20 +- include/llvm/Support/ErrorHandling.h | 4 +- include/llvm/Support/FileSystem.h | 2 + include/llvm/Support/GenericDomTree.h | 35 +- include/llvm/Support/GenericDomTreeConstruction.h | 154 +- include/llvm/Support/MemoryBuffer.h | 13 +- include/llvm/Support/OnDiskHashTable.h | 5 +- include/llvm/Support/ScopedPrinter.h | 6 +- include/llvm/Support/Signals.h | 2 +- include/llvm/Support/TargetParser.h | 4 +- include/llvm/Support/ToolOutputFile.h | 2 +- include/llvm/Support/Unicode.h | 4 + include/llvm/Support/YAMLTraits.h | 9 +- include/llvm/TableGen/Record.h | 482 +- include/llvm/Target/GenericOpcodes.td | 6 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 6 + include/llvm/Target/GlobalISel/Target.td | 13 + include/llvm/Target/Target.td | 6 + include/llvm/Target/TargetItinerary.td | 6 +- include/llvm/Target/TargetMachine.h | 4 + include/llvm/Target/TargetOptions.h | 11 +- include/llvm/Target/TargetSchedule.td | 3 +- include/llvm/Target/TargetSelectionDAG.td | 3 + .../AggressiveInstCombine/AggressiveInstCombine.h | 34 + include/llvm/Transforms/IPO.h | 8 +- include/llvm/Transforms/IPO/AlwaysInliner.h | 8 +- include/llvm/Transforms/IPO/ArgumentPromotion.h | 4 + include/llvm/Transforms/IPO/FunctionImport.h | 16 +- .../Transforms/IPO/SyntheticCountsPropagation.h | 19 + include/llvm/Transforms/InstrProfiling.h | 3 +- include/llvm/Transforms/Scalar.h | 7 + .../Transforms/Scalar/AlignmentFromAssumptions.h | 6 - include/llvm/Transforms/Scalar/JumpThreading.h | 6 +- include/llvm/Transforms/Utils/BasicBlockUtils.h | 3 +- include/llvm/Transforms/Utils/BuildLibCalls.h | 7 + include/llvm/Transforms/Utils/Cloning.h | 6 +- include/llvm/Transforms/Utils/Local.h | 24 +- include/llvm/Transforms/Utils/LoopUtils.h | 41 +- include/llvm/Transforms/Vectorize/SLPVectorizer.h | 9 +- lib/Analysis/AliasAnalysis.cpp | 148 +- lib/Analysis/AliasAnalysisSummary.h | 2 +- lib/Analysis/BasicAliasAnalysis.cpp | 12 +- lib/Analysis/BlockFrequencyInfoImpl.cpp | 2 +- lib/Analysis/BranchProbabilityInfo.cpp | 151 +- lib/Analysis/CFLAndersAliasAnalysis.cpp | 4 +- lib/Analysis/CGSCCPassManager.cpp | 8 +- lib/Analysis/CMakeLists.txt | 1 + lib/Analysis/ConstantFolding.cpp | 40 +- lib/Analysis/GlobalsModRef.cpp | 4 + lib/Analysis/InlineCost.cpp | 35 +- lib/Analysis/InstructionSimplify.cpp | 194 +- lib/Analysis/LazyCallGraph.cpp | 12 +- lib/Analysis/LazyValueInfo.cpp | 32 +- lib/Analysis/Lint.cpp | 10 +- lib/Analysis/Loads.cpp | 4 +- lib/Analysis/LoopAccessAnalysis.cpp | 6 +- lib/Analysis/LoopAnalysisManager.cpp | 2 +- lib/Analysis/LoopPass.cpp | 8 +- lib/Analysis/MemoryBuiltins.cpp | 20 +- lib/Analysis/MemoryDependenceAnalysis.cpp | 12 +- lib/Analysis/MemorySSA.cpp | 12 +- lib/Analysis/ModuleSummaryAnalysis.cpp | 15 +- lib/Analysis/PostDominators.cpp | 13 + lib/Analysis/ProfileSummaryInfo.cpp | 8 +- lib/Analysis/ScalarEvolution.cpp | 296 +- lib/Analysis/ScalarEvolutionExpander.cpp | 6 +- lib/Analysis/SyntheticCountsUtils.cpp | 113 + lib/Analysis/TargetLibraryInfo.cpp | 97 +- lib/Analysis/TargetTransformInfo.cpp | 8 + lib/Analysis/TypeBasedAliasAnalysis.cpp | 313 +- lib/Analysis/ValueTracking.cpp | 186 +- lib/Analysis/VectorUtils.cpp | 2 +- lib/AsmParser/LLParser.cpp | 264 +- lib/AsmParser/LLParser.h | 17 +- lib/AsmParser/Parser.cpp | 35 +- lib/BinaryFormat/Dwarf.cpp | 33 +- lib/Bitcode/Reader/BitcodeReader.cpp | 137 +- lib/Bitcode/Reader/MetadataLoader.cpp | 57 +- lib/Bitcode/Writer/BitWriter.cpp | 6 +- lib/Bitcode/Writer/BitcodeWriter.cpp | 164 +- lib/Bitcode/Writer/BitcodeWriterPass.cpp | 4 +- lib/CodeGen/AggressiveAntiDepBreaker.cpp | 8 +- lib/CodeGen/AsmPrinter/ARMException.cpp | 5 +- lib/CodeGen/AsmPrinter/AccelTable.cpp | 431 + lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 66 +- lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 26 +- lib/CodeGen/AsmPrinter/CMakeLists.txt | 3 +- lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 169 +- lib/CodeGen/AsmPrinter/CodeViewDebug.h | 10 +- lib/CodeGen/AsmPrinter/DIE.cpp | 59 +- lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp | 293 - lib/CodeGen/AsmPrinter/DwarfAccelTable.h | 261 - lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 110 +- lib/CodeGen/AsmPrinter/DwarfCompileUnit.h | 2 +- lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 125 +- lib/CodeGen/AsmPrinter/DwarfDebug.h | 47 +- lib/CodeGen/AsmPrinter/DwarfException.h | 2 +- lib/CodeGen/AsmPrinter/DwarfExpression.cpp | 24 +- lib/CodeGen/AsmPrinter/DwarfFile.cpp | 64 +- lib/CodeGen/AsmPrinter/DwarfFile.h | 33 +- lib/CodeGen/AsmPrinter/DwarfStringPool.cpp | 7 +- lib/CodeGen/AsmPrinter/DwarfStringPool.h | 5 +- lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 146 +- lib/CodeGen/AsmPrinter/DwarfUnit.h | 24 +- lib/CodeGen/AsmPrinter/EHStreamer.cpp | 144 +- lib/CodeGen/AsmPrinter/EHStreamer.h | 10 +- lib/CodeGen/AsmPrinter/WinCFGuard.cpp | 45 + lib/CodeGen/AsmPrinter/WinCFGuard.h | 54 + lib/CodeGen/BreakFalseDeps.cpp | 271 + lib/CodeGen/CMakeLists.txt | 6 +- lib/CodeGen/CodeGen.cpp | 5 +- lib/CodeGen/CodeGenPrepare.cpp | 60 +- lib/CodeGen/CriticalAntiDepBreaker.cpp | 8 +- lib/CodeGen/ExecutionDepsFix.cpp | 755 - lib/CodeGen/ExecutionDomainFix.cpp | 473 + lib/CodeGen/GlobalISel/CMakeLists.txt | 6 +- lib/CodeGen/GlobalISel/Combiner.cpp | 81 + lib/CodeGen/GlobalISel/CombinerHelper.cpp | 41 + lib/CodeGen/GlobalISel/IRTranslator.cpp | 32 + lib/CodeGen/GlobalISel/InstructionSelect.cpp | 68 +- lib/CodeGen/GlobalISel/InstructionSelector.cpp | 44 - lib/CodeGen/GlobalISel/LegalityPredicates.cpp | 78 + lib/CodeGen/GlobalISel/LegalizeMutations.cpp | 44 + lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 168 +- lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 162 +- lib/CodeGen/GlobalISel/RegBankSelect.cpp | 19 +- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 18 +- lib/CodeGen/GlobalISel/Utils.cpp | 73 +- lib/CodeGen/GlobalMerge.cpp | 6 +- lib/CodeGen/ImplicitNullChecks.cpp | 4 +- lib/CodeGen/IndirectBrExpandPass.cpp | 221 + lib/CodeGen/InterferenceCache.cpp | 4 +- lib/CodeGen/LLVMTargetMachine.cpp | 7 + lib/CodeGen/LiveDebugValues.cpp | 39 +- lib/CodeGen/LiveDebugVariables.cpp | 43 +- lib/CodeGen/LiveInterval.cpp | 1 + lib/CodeGen/LiveIntervalUnion.cpp | 2 +- lib/CodeGen/LiveIntervals.cpp | 30 + lib/CodeGen/LivePhysRegs.cpp | 31 +- lib/CodeGen/LiveRangeEdit.cpp | 28 +- lib/CodeGen/LiveRegMatrix.cpp | 16 + lib/CodeGen/LoopTraversal.cpp | 77 + lib/CodeGen/LowerEmuTLS.cpp | 2 +- lib/CodeGen/MIRParser/MILexer.cpp | 27 +- lib/CodeGen/MIRParser/MILexer.h | 2 + lib/CodeGen/MIRParser/MIParser.cpp | 19 + lib/CodeGen/MIRParser/MIRParser.cpp | 6 +- lib/CodeGen/MIRPrinter.cpp | 19 +- lib/CodeGen/MachineBasicBlock.cpp | 172 +- lib/CodeGen/MachineCSE.cpp | 13 +- lib/CodeGen/MachineCombiner.cpp | 178 +- lib/CodeGen/MachineCopyPropagation.cpp | 207 +- lib/CodeGen/MachineDominators.cpp | 35 +- lib/CodeGen/MachineFunction.cpp | 3 +- lib/CodeGen/MachineInstr.cpp | 168 +- lib/CodeGen/MachineLICM.cpp | 128 +- lib/CodeGen/MachineOperand.cpp | 40 +- lib/CodeGen/MachineOptimizationRemarkEmitter.cpp | 3 +- lib/CodeGen/MachineOutliner.cpp | 97 +- lib/CodeGen/MachinePipeliner.cpp | 14 +- lib/CodeGen/MachineRegisterInfo.cpp | 57 +- lib/CodeGen/MachineScheduler.cpp | 9 +- lib/CodeGen/MachineVerifier.cpp | 56 +- lib/CodeGen/ParallelCG.cpp | 4 +- lib/CodeGen/PeepholeOptimizer.cpp | 868 +- lib/CodeGen/PrologEpilogInserter.cpp | 13 +- lib/CodeGen/ReachingDefAnalysis.cpp | 195 + lib/CodeGen/RegAllocFast.cpp | 15 +- lib/CodeGen/RegAllocGreedy.cpp | 84 +- lib/CodeGen/RegAllocPBQP.cpp | 38 +- lib/CodeGen/RegisterClassInfo.cpp | 9 +- lib/CodeGen/RegisterPressure.cpp | 4 +- lib/CodeGen/ResetMachineFunctionPass.cpp | 12 +- lib/CodeGen/SafeStack.cpp | 54 +- lib/CodeGen/SafeStackLayout.cpp | 1 + lib/CodeGen/SafeStackLayout.h | 4 + lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 834 +- lib/CodeGen/SelectionDAG/FastISel.cpp | 3 +- lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 10 + lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 17 +- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 147 +- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 27 +- lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp | 2 +- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 31 +- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 79 +- lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 15 +- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 20 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 401 +- .../SelectionDAG/SelectionDAGAddressAnalysis.cpp | 64 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 84 +- lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 23 + lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 49 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 725 +- lib/CodeGen/ShrinkWrap.cpp | 49 +- lib/CodeGen/SplitKit.cpp | 53 +- lib/CodeGen/SplitKit.h | 6 +- lib/CodeGen/TailDuplication.cpp | 59 +- lib/CodeGen/TailDuplicator.cpp | 18 +- lib/CodeGen/TargetInstrInfo.cpp | 20 + lib/CodeGen/TargetLoweringBase.cpp | 43 +- lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 53 +- lib/CodeGen/TargetPassConfig.cpp | 56 +- lib/CodeGen/TargetRegisterInfo.cpp | 28 +- lib/CodeGen/TargetSubtargetInfo.cpp | 7 + lib/CodeGen/VirtRegMap.cpp | 2 +- lib/DebugInfo/CodeView/GlobalTypeTableBuilder.cpp | 37 +- lib/DebugInfo/CodeView/RecordName.cpp | 19 +- lib/DebugInfo/CodeView/TypeDumpVisitor.cpp | 1 + lib/DebugInfo/CodeView/TypeStreamMerger.cpp | 179 +- lib/DebugInfo/DWARF/CMakeLists.txt | 2 + lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp | 769 +- lib/DebugInfo/DWARF/DWARFAddressRange.cpp | 26 + lib/DebugInfo/DWARF/DWARFContext.cpp | 87 +- lib/DebugInfo/DWARF/DWARFDebugArangeSet.cpp | 13 +- lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 175 +- lib/DebugInfo/DWARF/DWARFDebugLoc.cpp | 6 +- lib/DebugInfo/DWARF/DWARFDebugRangeList.cpp | 6 - lib/DebugInfo/DWARF/DWARFDebugRnglists.cpp | 194 + lib/DebugInfo/DWARF/DWARFDie.cpp | 6 +- lib/DebugInfo/DWARF/DWARFFormValue.cpp | 81 +- lib/DebugInfo/DWARF/DWARFUnit.cpp | 386 +- lib/DebugInfo/DWARF/DWARFVerifier.cpp | 51 +- lib/DebugInfo/DWARF/SyntaxHighlighting.cpp | 10 +- lib/DebugInfo/DWARF/SyntaxHighlighting.h | 2 + lib/DebugInfo/PDB/DIA/DIARawSymbol.cpp | 96 + lib/DebugInfo/PDB/DIA/DIASession.cpp | 4 +- lib/DebugInfo/PDB/Native/HashTable.cpp | 94 +- lib/DebugInfo/PDB/Native/InfoStream.cpp | 3 +- lib/DebugInfo/PDB/Native/InfoStreamBuilder.cpp | 19 +- lib/DebugInfo/PDB/Native/NamedStreamMap.cpp | 146 +- lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp | 44 + lib/DebugInfo/PDB/Native/NativeSession.cpp | 2 +- lib/DebugInfo/PDB/Native/PDBFileBuilder.cpp | 17 + lib/DebugInfo/PDB/PDBSymbolTypeFunctionSig.cpp | 19 + lib/DebugInfo/Symbolize/Symbolize.cpp | 2 +- lib/ExecutionEngine/ExecutionEngine.cpp | 16 +- lib/ExecutionEngine/Interpreter/Execution.cpp | 2 +- lib/ExecutionEngine/MCJIT/MCJIT.cpp | 9 +- lib/ExecutionEngine/MCJIT/MCJIT.h | 17 +- lib/ExecutionEngine/Orc/CMakeLists.txt | 2 + lib/ExecutionEngine/Orc/Core.cpp | 356 + lib/ExecutionEngine/Orc/Legacy.cpp | 89 + lib/ExecutionEngine/Orc/NullResolver.cpp | 17 +- lib/ExecutionEngine/Orc/OrcCBindingsStack.h | 293 +- lib/ExecutionEngine/Orc/OrcMCJITReplacement.h | 146 +- lib/ExecutionEngine/RuntimeDyld/JITSymbol.cpp | 50 + lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp | 303 +- .../RuntimeDyld/RuntimeDyldChecker.cpp | 20 +- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 27 +- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h | 3 +- .../RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h | 115 +- .../RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h | 10 +- lib/ExecutionEngine/TargetSelect.cpp | 2 + lib/FuzzMutate/FuzzerCLI.cpp | 42 +- lib/FuzzMutate/IRMutator.cpp | 13 +- lib/IR/AsmWriter.cpp | 63 +- lib/IR/Attributes.cpp | 47 +- lib/IR/AutoUpgrade.cpp | 268 +- lib/IR/Constants.cpp | 63 + lib/IR/Core.cpp | 9 + lib/IR/DIBuilder.cpp | 49 +- lib/IR/DataLayout.cpp | 78 +- lib/IR/DebugInfoMetadata.cpp | 93 +- lib/IR/DiagnosticInfo.cpp | 6 +- lib/IR/Dominators.cpp | 244 +- lib/IR/Function.cpp | 40 +- lib/IR/IRBuilder.cpp | 73 +- lib/IR/Instruction.cpp | 5 + lib/IR/Instructions.cpp | 305 +- lib/IR/LLVMContextImpl.h | 70 +- lib/IR/MDBuilder.cpp | 35 +- lib/IR/Mangler.cpp | 10 + lib/IR/Metadata.cpp | 24 +- lib/IR/Module.cpp | 9 + lib/IR/ModuleSummaryIndex.cpp | 278 + lib/IR/Operator.cpp | 4 +- lib/IR/TypeFinder.cpp | 50 +- lib/IR/Value.cpp | 4 +- lib/IR/ValueTypes.cpp | 4 +- lib/IR/Verifier.cpp | 91 +- lib/IRReader/IRReader.cpp | 13 +- lib/LTO/Caching.cpp | 4 +- lib/LTO/LLVMBuild.txt | 1 + lib/LTO/LTO.cpp | 121 +- lib/LTO/LTOBackend.cpp | 36 +- lib/LTO/LTOCodeGenerator.cpp | 11 +- lib/LTO/LTOModule.cpp | 20 +- lib/LTO/ThinLTOCodeGenerator.cpp | 69 +- lib/Linker/IRMover.cpp | 30 +- lib/MC/CMakeLists.txt | 1 + lib/MC/MCAsmMacro.cpp | 42 + lib/MC/MCAsmStreamer.cpp | 72 +- lib/MC/MCAssembler.cpp | 24 +- lib/MC/MCCodeView.cpp | 71 +- lib/MC/MCContext.cpp | 17 +- lib/MC/MCDisassembler/Disassembler.cpp | 2 +- lib/MC/MCDwarf.cpp | 225 +- lib/MC/MCExpr.cpp | 7 +- lib/MC/MCMachOStreamer.cpp | 28 +- lib/MC/MCObjectFileInfo.cpp | 19 +- lib/MC/MCObjectStreamer.cpp | 54 +- lib/MC/MCParser/AsmParser.cpp | 125 +- lib/MC/MCParser/COFFAsmParser.cpp | 19 +- lib/MC/MCParser/ELFAsmParser.cpp | 2 + lib/MC/MCParser/MCAsmLexer.cpp | 93 + lib/MC/MCSectionELF.cpp | 2 + lib/MC/MCStreamer.cpp | 57 +- lib/MC/MCWasmStreamer.cpp | 10 +- lib/MC/MCWinCOFFStreamer.cpp | 30 +- lib/MC/MachObjectWriter.cpp | 8 +- lib/MC/StringTableBuilder.cpp | 2 + lib/MC/WasmObjectWriter.cpp | 707 +- lib/Object/COFFImportFile.cpp | 15 +- lib/Object/ELF.cpp | 1 + lib/Object/ELFObjectFile.cpp | 16 +- lib/Object/Object.cpp | 2 +- lib/Object/WasmObjectFile.cpp | 490 +- lib/Object/WindowsResource.cpp | 6 +- lib/ObjectYAML/CodeViewYAMLSymbols.cpp | 51 +- lib/ObjectYAML/ELFYAML.cpp | 34 +- lib/ObjectYAML/WasmYAML.cpp | 55 +- lib/Option/OptTable.cpp | 8 +- lib/Passes/LLVMBuild.txt | 2 +- lib/Passes/PassBuilder.cpp | 26 +- lib/Passes/PassRegistry.def | 2 + lib/ProfileData/SampleProf.cpp | 27 + lib/Support/APInt.cpp | 3 +- lib/Support/ARMAttributeParser.cpp | 1 - lib/Support/CMakeLists.txt | 14 +- lib/Support/CommandLine.cpp | 6 +- lib/Support/DJB.cpp | 86 + lib/Support/ErrorHandling.cpp | 33 + lib/Support/Host.cpp | 5 +- lib/Support/LockFileManager.cpp | 26 +- lib/Support/MemoryBuffer.cpp | 18 +- lib/Support/NativeFormatting.cpp | 2 + lib/Support/PrettyStackTrace.cpp | 4 + lib/Support/RWMutex.cpp | 3 +- lib/Support/Statistic.cpp | 38 +- lib/Support/StringExtras.cpp | 10 + lib/Support/StringMap.cpp | 50 +- lib/Support/TargetParser.cpp | 20 +- lib/Support/Timer.cpp | 12 +- lib/Support/Triple.cpp | 10 +- lib/Support/UnicodeCaseFold.cpp | 742 + lib/Support/Unix/Path.inc | 16 +- lib/Support/Unix/Process.inc | 15 + lib/Support/Unix/Signals.inc | 2 +- lib/Support/Unix/Threading.inc | 5 +- lib/Support/Windows/Path.inc | 16 +- lib/Support/Windows/RWMutex.inc | 4 +- lib/Support/Windows/Signals.inc | 2 +- lib/TableGen/Record.cpp | 1084 +- lib/TableGen/TGLexer.cpp | 2 + lib/TableGen/TGLexer.h | 2 +- lib/TableGen/TGParser.cpp | 517 +- lib/TableGen/TGParser.h | 6 +- lib/Target/AArch64/AArch64.td | 52 +- lib/Target/AArch64/AArch64AsmPrinter.cpp | 23 - lib/Target/AArch64/AArch64CallLowering.cpp | 3 +- lib/Target/AArch64/AArch64CallingConvention.td | 4 + lib/Target/AArch64/AArch64FastISel.cpp | 24 +- lib/Target/AArch64/AArch64FrameLowering.cpp | 35 +- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 39 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 989 +- lib/Target/AArch64/AArch64ISelLowering.h | 17 + lib/Target/AArch64/AArch64InstrAtomics.td | 7 +- lib/Target/AArch64/AArch64InstrFormats.td | 38 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 308 +- lib/Target/AArch64/AArch64InstrInfo.h | 152 +- lib/Target/AArch64/AArch64InstrInfo.td | 53 +- lib/Target/AArch64/AArch64InstructionSelector.cpp | 178 +- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 554 +- lib/Target/AArch64/AArch64MacroFusion.cpp | 357 +- lib/Target/AArch64/AArch64RegisterInfo.cpp | 16 +- lib/Target/AArch64/AArch64RegisterInfo.h | 5 + lib/Target/AArch64/AArch64SVEInstrInfo.td | 11 + lib/Target/AArch64/AArch64SchedExynosM1.td | 847 + lib/Target/AArch64/AArch64SchedExynosM3.td | 845 + lib/Target/AArch64/AArch64SchedM1.td | 849 - lib/Target/AArch64/AArch64SchedThunderX2T99.td | 9 +- lib/Target/AArch64/AArch64Subtarget.cpp | 25 +- lib/Target/AArch64/AArch64Subtarget.h | 13 +- lib/Target/AArch64/AArch64SystemOperands.td | 33 +- lib/Target/AArch64/AArch64TargetMachine.cpp | 10 +- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 215 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 26 +- .../AArch64/InstPrinter/AArch64InstPrinter.cpp | 29 +- .../AArch64/InstPrinter/AArch64InstPrinter.h | 10 +- .../AArch64/MCTargetDesc/AArch64AddressingModes.h | 14 +- .../AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp | 3 +- lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp | 2 + lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h | 3 + .../MCTargetDesc/AArch64WinCOFFObjectWriter.cpp | 14 + lib/Target/AArch64/SVEInstrFormats.td | 270 +- lib/Target/AArch64/Utils/AArch64BaseInfo.cpp | 7 + lib/Target/AArch64/Utils/AArch64BaseInfo.h | 9 + lib/Target/AMDGPU/AMDGPU.h | 5 +- lib/Target/AMDGPU/AMDGPU.td | 44 +- lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 9 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 33 +- lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 2 +- lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 3 +- lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def | 76 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 61 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 186 +- lib/Target/AMDGPU/AMDGPUISelLowering.h | 99 + lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 30 +- lib/Target/AMDGPU/AMDGPUInstrInfo.h | 2 + lib/Target/AMDGPU/AMDGPUInstrInfo.td | 8 + lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 +- lib/Target/AMDGPU/AMDGPUInstructions.td | 48 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 40 +- .../AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp | 52 +- lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 27 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 273 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 19 +- lib/Target/AMDGPU/AMDGPURegisterBanks.td | 2 + lib/Target/AMDGPU/AMDGPURegisterInfo.cpp | 7 + lib/Target/AMDGPU/AMDGPURegisterInfo.h | 4 + lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 2 + lib/Target/AMDGPU/AMDGPUSubtarget.h | 25 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 17 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 56 +- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 217 +- lib/Target/AMDGPU/BUFInstructions.td | 426 +- lib/Target/AMDGPU/DSInstructions.td | 17 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 79 +- lib/Target/AMDGPU/EvergreenInstructions.td | 2 +- lib/Target/AMDGPU/GCNIterativeScheduler.cpp | 2 +- lib/Target/AMDGPU/GCNProcessors.td | 12 +- lib/Target/AMDGPU/GCNSchedStrategy.cpp | 2 +- .../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 14 +- .../AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp | 24 - lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h | 3 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 4 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 77 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h | 5 +- lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 23 +- lib/Target/AMDGPU/MIMGInstructions.td | 633 +- lib/Target/AMDGPU/R600InstrInfo.cpp | 7 +- lib/Target/AMDGPU/R600InstrInfo.h | 3 +- lib/Target/AMDGPU/R600Instructions.td | 1 + lib/Target/AMDGPU/R600RegisterInfo.cpp | 32 +- lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 6 +- lib/Target/AMDGPU/SIDefines.h | 9 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 1 + lib/Target/AMDGPU/SIFrameLowering.cpp | 15 +- lib/Target/AMDGPU/SIISelLowering.cpp | 638 +- lib/Target/AMDGPU/SIISelLowering.h | 4 + lib/Target/AMDGPU/SIInsertSkips.cpp | 54 +- lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 157 +- lib/Target/AMDGPU/SIInsertWaits.cpp | 4 +- lib/Target/AMDGPU/SIInstrFormats.td | 10 + lib/Target/AMDGPU/SIInstrInfo.cpp | 91 +- lib/Target/AMDGPU/SIInstrInfo.h | 13 +- lib/Target/AMDGPU/SIInstrInfo.td | 359 +- lib/Target/AMDGPU/SIInstructions.td | 9 +- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 84 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 8 +- lib/Target/AMDGPU/SIMachineFunctionInfo.h | 22 +- lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 111 +- lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 70 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 35 +- lib/Target/AMDGPU/SIRegisterInfo.h | 1 - lib/Target/AMDGPU/SIRegisterInfo.td | 14 +- lib/Target/AMDGPU/SIShrinkInstructions.cpp | 3 +- lib/Target/AMDGPU/SMInstructions.td | 6 +- lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 10 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 128 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 13 +- lib/Target/AMDGPU/VOP1Instructions.td | 1 + lib/Target/AMDGPU/VOP2Instructions.td | 22 +- lib/Target/AMDGPU/VOP3Instructions.td | 2 - lib/Target/AMDGPU/VOPCInstructions.td | 1 + lib/Target/AMDGPU/VOPInstructions.td | 1 + lib/Target/ARC/ARCInstrInfo.cpp | 4 + lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp | 4 + lib/Target/ARC/MCTargetDesc/ARCInfo.h | 2 + lib/Target/ARM/ARM.td | 4 +- lib/Target/ARM/ARMAsmPrinter.cpp | 41 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 168 +- lib/Target/ARM/ARMBaseInstrInfo.h | 2 + lib/Target/ARM/ARMBaseRegisterInfo.h | 1 + lib/Target/ARM/ARMCallLowering.cpp | 2 +- lib/Target/ARM/ARMCallingConv.td | 3 +- lib/Target/ARM/ARMConstantIslandPass.cpp | 12 +- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 7 +- lib/Target/ARM/ARMFastISel.cpp | 7 +- lib/Target/ARM/ARMFrameLowering.cpp | 13 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 86 +- lib/Target/ARM/ARMISelLowering.cpp | 520 +- lib/Target/ARM/ARMISelLowering.h | 7 + lib/Target/ARM/ARMInstrFormats.td | 9 +- lib/Target/ARM/ARMInstrInfo.cpp | 28 + lib/Target/ARM/ARMInstrInfo.h | 7 + lib/Target/ARM/ARMInstrInfo.td | 28 +- lib/Target/ARM/ARMInstrThumb2.td | 12 +- lib/Target/ARM/ARMInstrVFP.td | 217 +- lib/Target/ARM/ARMLegalizerInfo.cpp | 185 +- lib/Target/ARM/ARMRegisterBankInfo.cpp | 63 +- lib/Target/ARM/ARMRegisterInfo.td | 12 + lib/Target/ARM/ARMScheduleA57.td | 38 +- lib/Target/ARM/ARMTargetMachine.cpp | 24 +- lib/Target/ARM/ARMTargetObjectFile.cpp | 3 - lib/Target/ARM/ARMTargetObjectFile.h | 3 - lib/Target/ARM/ARMTargetTransformInfo.cpp | 6 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 57 +- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 23 +- lib/Target/ARM/Disassembler/LLVMBuild.txt | 2 +- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 3 +- lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h | 4 +- lib/Target/ARM/README.txt | 2 +- lib/Target/ARM/Thumb1FrameLowering.cpp | 19 +- lib/Target/ARM/Thumb1InstrInfo.cpp | 17 +- lib/Target/ARM/Thumb1InstrInfo.h | 1 + lib/Target/ARM/Thumb2InstrInfo.cpp | 17 +- lib/Target/ARM/ThumbRegisterInfo.cpp | 20 +- lib/Target/AVR/AVRISelDAGToDAG.cpp | 3 - lib/Target/AVR/AVRISelLowering.cpp | 10 +- lib/Target/AVR/AVRInstrInfo.td | 18 +- lib/Target/AVR/AVRTargetMachine.cpp | 2 +- lib/Target/BPF/BPF.h | 3 + lib/Target/BPF/BPF.td | 6 + lib/Target/BPF/BPFCallingConv.td | 20 + lib/Target/BPF/BPFISelDAGToDAG.cpp | 63 +- lib/Target/BPF/BPFISelLowering.cpp | 194 +- lib/Target/BPF/BPFISelLowering.h | 10 + lib/Target/BPF/BPFInstrInfo.cpp | 10 + lib/Target/BPF/BPFInstrInfo.td | 159 +- lib/Target/BPF/BPFMIPeephole.cpp | 175 + lib/Target/BPF/BPFRegisterInfo.cpp | 4 +- lib/Target/BPF/BPFRegisterInfo.h | 2 + lib/Target/BPF/BPFSubtarget.cpp | 3 + lib/Target/BPF/BPFSubtarget.h | 8 + lib/Target/BPF/BPFTargetMachine.cpp | 22 + lib/Target/BPF/CMakeLists.txt | 1 + lib/Target/BPF/Disassembler/BPFDisassembler.cpp | 45 +- lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h | 4 + lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 11 + lib/Target/Hexagon/BitTracker.cpp | 22 +- lib/Target/Hexagon/BitTracker.h | 12 +- lib/Target/Hexagon/CMakeLists.txt | 2 + .../Hexagon/Disassembler/HexagonDisassembler.cpp | 58 + lib/Target/Hexagon/Hexagon.td | 5 + lib/Target/Hexagon/HexagonBitSimplify.cpp | 10 +- lib/Target/Hexagon/HexagonBitTracker.cpp | 2 +- lib/Target/Hexagon/HexagonCallingConv.td | 134 + lib/Target/Hexagon/HexagonConstExtenders.cpp | 93 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 15 +- lib/Target/Hexagon/HexagonDepIICScalar.td | 70 + lib/Target/Hexagon/HexagonDepInstrInfo.td | 62 + lib/Target/Hexagon/HexagonDepMappings.td | 1 + lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 2 + lib/Target/Hexagon/HexagonFrameLowering.cpp | 2 +- lib/Target/Hexagon/HexagonGenInsert.cpp | 23 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 199 +- lib/Target/Hexagon/HexagonISelDAGToDAG.h | 5 + lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 200 +- lib/Target/Hexagon/HexagonISelLowering.cpp | 1493 +- lib/Target/Hexagon/HexagonISelLowering.h | 85 +- lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 1309 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 50 + lib/Target/Hexagon/HexagonInstrInfo.h | 18 +- lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 93 +- lib/Target/Hexagon/HexagonNewValueJump.cpp | 16 + lib/Target/Hexagon/HexagonPatterns.td | 340 +- lib/Target/Hexagon/HexagonPatternsHVX.td | 384 + lib/Target/Hexagon/HexagonPseudo.td | 8 + lib/Target/Hexagon/HexagonRegisterInfo.cpp | 15 + lib/Target/Hexagon/HexagonRegisterInfo.h | 6 + lib/Target/Hexagon/HexagonRegisterInfo.td | 91 +- lib/Target/Hexagon/HexagonSubtarget.h | 3 + lib/Target/Hexagon/HexagonTargetMachine.cpp | 21 +- lib/Target/Hexagon/HexagonVExtract.cpp | 166 + .../Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp | 2 +- lib/Target/Hexagon/RDFCopy.cpp | 5 +- lib/Target/Hexagon/RDFLiveness.cpp | 2 +- lib/Target/Lanai/LanaiISelDAGToDAG.cpp | 3 - lib/Target/Lanai/LanaiInstrFormats.td | 2 +- lib/Target/Lanai/LanaiInstrInfo.h | 1 + lib/Target/Lanai/LanaiTargetObjectFile.cpp | 12 +- lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 5 - lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 3 +- lib/Target/Mips/CMakeLists.txt | 4 + lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 46 - lib/Target/Mips/LLVMBuild.txt | 1 + .../Mips/MCTargetDesc/MipsELFObjectWriter.cpp | 2 + lib/Target/Mips/MicroMips32r6InstrFormats.td | 82 +- lib/Target/Mips/MicroMips32r6InstrInfo.td | 189 +- lib/Target/Mips/MicroMipsInstrFPU.td | 131 +- lib/Target/Mips/MicroMipsInstrFormats.td | 3 +- lib/Target/Mips/MicroMipsInstrInfo.td | 34 +- lib/Target/Mips/Mips.h | 8 + lib/Target/Mips/Mips.td | 5 + lib/Target/Mips/Mips16InstrInfo.td | 2 +- lib/Target/Mips/Mips32r6InstrInfo.td | 39 + lib/Target/Mips/Mips64InstrInfo.td | 34 +- lib/Target/Mips/Mips64r6InstrInfo.td | 30 + lib/Target/Mips/MipsAsmPrinter.cpp | 29 +- lib/Target/Mips/MipsCallLowering.cpp | 47 + lib/Target/Mips/MipsCallLowering.h | 40 + lib/Target/Mips/MipsDSPInstrFormats.td | 2 +- lib/Target/Mips/MipsDelaySlotFiller.cpp | 2 +- lib/Target/Mips/MipsEVAInstrInfo.td | 29 +- lib/Target/Mips/MipsFastISel.cpp | 4 +- lib/Target/Mips/MipsISelDAGToDAG.cpp | 3 - lib/Target/Mips/MipsISelLowering.cpp | 20 +- lib/Target/Mips/MipsISelLowering.h | 6 - lib/Target/Mips/MipsInstrFPU.td | 108 +- lib/Target/Mips/MipsInstrFormats.td | 4 +- lib/Target/Mips/MipsInstrInfo.cpp | 21 +- lib/Target/Mips/MipsInstrInfo.td | 153 +- lib/Target/Mips/MipsInstructionSelector.cpp | 63 + lib/Target/Mips/MipsLegalizerInfo.cpp | 24 + lib/Target/Mips/MipsLegalizerInfo.h | 29 + lib/Target/Mips/MipsLongBranch.cpp | 19 +- lib/Target/Mips/MipsMSAInstrInfo.td | 72 +- lib/Target/Mips/MipsRegisterBankInfo.cpp | 26 + lib/Target/Mips/MipsRegisterBankInfo.h | 35 + lib/Target/Mips/MipsRegisterInfo.h | 2 + lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 +- lib/Target/Mips/MipsSEISelLowering.cpp | 61 +- lib/Target/Mips/MipsSEInstrInfo.cpp | 27 +- lib/Target/Mips/MipsSEInstrInfo.h | 6 +- lib/Target/Mips/MipsSERegisterInfo.cpp | 2 - lib/Target/Mips/MipsScheduleP5600.td | 3 +- lib/Target/Mips/MipsSubtarget.cpp | 81 +- lib/Target/Mips/MipsSubtarget.h | 30 + lib/Target/Mips/MipsTargetMachine.cpp | 31 + lib/Target/Mips/MipsTargetObjectFile.cpp | 7 + lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 7 +- lib/Target/NVPTX/NVPTXGenericToNVVM.cpp | 60 +- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 66 +- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 1 - lib/Target/NVPTX/NVPTXISelLowering.cpp | 21 +- lib/Target/NVPTX/NVPTXInstrInfo.td | 29 +- lib/Target/NVPTX/NVPTXIntrinsics.td | 286 +- lib/Target/NVPTX/NVPTXSubtarget.h | 20 - lib/Target/NVPTX/NVPTXTargetMachine.cpp | 4 +- lib/Target/Nios2/Nios2ISelDAGToDAG.cpp | 3 - lib/Target/Nios2/Nios2ISelLowering.cpp | 29 + lib/Target/Nios2/Nios2InstrFormats.td | 66 +- lib/Target/Nios2/Nios2InstrInfo.cpp | 11 + lib/Target/Nios2/Nios2InstrInfo.h | 4 + lib/Target/Nios2/Nios2InstrInfo.td | 39 +- lib/Target/PowerPC/P9InstrResources.td | 554 +- lib/Target/PowerPC/PPC.td | 1 + lib/Target/PowerPC/PPCBranchCoalescing.cpp | 4 +- lib/Target/PowerPC/PPCCTRLoops.cpp | 39 +- lib/Target/PowerPC/PPCCallingConv.td | 53 + lib/Target/PowerPC/PPCFastISel.cpp | 4 +- lib/Target/PowerPC/PPCFrameLowering.cpp | 16 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 10 + lib/Target/PowerPC/PPCISelLowering.cpp | 81 +- lib/Target/PowerPC/PPCISelLowering.h | 6 + lib/Target/PowerPC/PPCInstrInfo.cpp | 31 + lib/Target/PowerPC/PPCInstrInfo.td | 14 +- lib/Target/PowerPC/PPCInstrVSX.td | 21 - lib/Target/PowerPC/PPCMachineBasicBlockUtils.h | 198 - lib/Target/PowerPC/PPCMachineFunctionInfo.h | 11 + lib/Target/PowerPC/PPCReduceCRLogicals.cpp | 183 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 18 + lib/Target/PowerPC/PPCRegisterInfo.h | 2 + lib/Target/PowerPC/PPCRegisterInfo.td | 8 +- lib/Target/PowerPC/PPCScheduleP9.td | 19 + lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 13 + lib/Target/PowerPC/PPCTargetTransformInfo.h | 2 +- lib/Target/PowerPC/PPCVSXSwapRemoval.cpp | 2 + lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 43 +- .../RISCV/Disassembler/RISCVDisassembler.cpp | 11 + lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 8 +- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h | 19 +- lib/Target/RISCV/MCTargetDesc/CMakeLists.txt | 2 + lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 135 +- .../RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp | 4 + lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 39 + lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h | 24 + lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h | 6 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 17 +- lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 5 +- lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h | 1 + .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 12 + .../RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 18 + .../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 22 + lib/Target/RISCV/RISCV.td | 6 + lib/Target/RISCV/RISCVAsmPrinter.cpp | 55 + lib/Target/RISCV/RISCVFrameLowering.cpp | 97 +- lib/Target/RISCV/RISCVFrameLowering.h | 3 + lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 22 +- lib/Target/RISCV/RISCVISelLowering.cpp | 245 +- lib/Target/RISCV/RISCVISelLowering.h | 12 +- lib/Target/RISCV/RISCVInstrInfo.cpp | 291 + lib/Target/RISCV/RISCVInstrInfo.h | 33 + lib/Target/RISCV/RISCVInstrInfoC.td | 117 +- lib/Target/RISCV/RISCVInstrInfoM.td | 15 + lib/Target/RISCV/RISCVMCInstLower.cpp | 8 +- lib/Target/RISCV/RISCVMachineFunctionInfo.h | 44 + lib/Target/RISCV/RISCVRegisterInfo.cpp | 31 +- lib/Target/RISCV/RISCVRegisterInfo.h | 12 + lib/Target/RISCV/RISCVTargetMachine.cpp | 3 + lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp | 16 +- lib/Target/Sparc/Sparc.td | 1 + lib/Target/Sparc/SparcFrameLowering.cpp | 29 +- lib/Target/Sparc/SparcISelLowering.cpp | 2 +- lib/Target/Sparc/SparcRegisterInfo.h | 2 + lib/Target/SystemZ/SystemZ.td | 1 + lib/Target/SystemZ/SystemZAsmPrinter.cpp | 129 + lib/Target/SystemZ/SystemZAsmPrinter.h | 17 +- lib/Target/SystemZ/SystemZCallingConv.td | 9 + lib/Target/SystemZ/SystemZElimCompare.cpp | 138 +- lib/Target/SystemZ/SystemZFrameLowering.cpp | 92 +- lib/Target/SystemZ/SystemZFrameLowering.h | 5 - lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 189 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 413 +- lib/Target/SystemZ/SystemZISelLowering.h | 13 + lib/Target/SystemZ/SystemZInstrInfo.td | 12 - lib/Target/SystemZ/SystemZLongBranch.cpp | 2 +- lib/Target/SystemZ/SystemZRegisterInfo.cpp | 8 + lib/Target/SystemZ/SystemZRegisterInfo.td | 2 +- lib/Target/TargetLoweringObjectFile.cpp | 15 +- lib/Target/TargetMachine.cpp | 33 +- .../InstPrinter/WebAssemblyInstPrinter.cpp | 4 +- .../MCTargetDesc/WebAssemblyMCAsmInfo.cpp | 6 - .../MCTargetDesc/WebAssemblyMCCodeEmitter.cpp | 2 +- .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 26 +- .../MCTargetDesc/WebAssemblyTargetStreamer.cpp | 70 +- .../MCTargetDesc/WebAssemblyTargetStreamer.h | 11 +- lib/Target/WebAssembly/README.txt | 54 +- lib/Target/WebAssembly/WebAssembly.td | 9 + lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 12 +- lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 1 + .../WebAssemblyFixIrreducibleControlFlow.cpp | 2 +- lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 5 - lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 3 +- lib/Target/WebAssembly/WebAssemblyInstrControl.td | 30 +- lib/Target/WebAssembly/WebAssemblyInstrConv.td | 4 +- lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 18 + lib/Target/WebAssembly/WebAssemblyInstrMemory.td | 9 + lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp | 18 +- .../WebAssemblyRuntimeLibcallSignatures.cpp | 1379 +- lib/Target/WebAssembly/WebAssemblySubtarget.cpp | 6 +- lib/Target/WebAssembly/WebAssemblySubtarget.h | 4 + .../WebAssembly/WebAssemblyTargetMachine.cpp | 3 +- lib/Target/WebAssembly/known_gcc_test_failures.txt | 54 +- lib/Target/X86/AsmParser/X86AsmParser.cpp | 163 +- lib/Target/X86/AsmParser/X86Operand.h | 50 +- lib/Target/X86/CMakeLists.txt | 8 +- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 45 +- .../X86/Disassembler/X86DisassemblerDecoder.h | 3 +- .../Disassembler/X86DisassemblerDecoderCommon.h | 6 +- lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp | 4 +- lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp | 4 +- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 96 +- lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp | 3 + lib/Target/X86/MCTargetDesc/X86FixupKinds.h | 1 + lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 42 +- .../X86/MCTargetDesc/X86MachObjectWriter.cpp | 1 + .../X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp | 1 + lib/Target/X86/README-MMX.txt | 29 - lib/Target/X86/README-SSE.txt | 9 - lib/Target/X86/README-UNIMPLEMENTED.txt | 14 - lib/Target/X86/README.txt | 24 - lib/Target/X86/X86.h | 8 + lib/Target/X86/X86.td | 136 +- lib/Target/X86/X86AsmPrinter.cpp | 34 +- lib/Target/X86/X86AsmPrinter.h | 1 + lib/Target/X86/X86CallLowering.cpp | 43 +- lib/Target/X86/X86CallingConv.td | 6 +- lib/Target/X86/X86DomainReassignment.cpp | 12 +- lib/Target/X86/X86EvexToVex.cpp | 29 +- lib/Target/X86/X86ExpandPseudo.cpp | 6 +- lib/Target/X86/X86FastISel.cpp | 10 +- lib/Target/X86/X86FixupBWInsts.cpp | 19 +- lib/Target/X86/X86FixupLEAs.cpp | 3 +- lib/Target/X86/X86FrameLowering.cpp | 142 +- lib/Target/X86/X86FrameLowering.h | 2 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 339 +- lib/Target/X86/X86ISelLowering.cpp | 4038 ++- lib/Target/X86/X86ISelLowering.h | 33 +- lib/Target/X86/X86IndirectBranchTracking.cpp | 152 + lib/Target/X86/X86Instr3DNow.td | 9 +- lib/Target/X86/X86InstrAVX512.td | 937 +- lib/Target/X86/X86InstrArithmetic.td | 22 +- lib/Target/X86/X86InstrCompiler.td | 84 +- lib/Target/X86/X86InstrControl.td | 31 +- lib/Target/X86/X86InstrExtension.td | 8 +- lib/Target/X86/X86InstrFragmentsSIMD.td | 23 +- lib/Target/X86/X86InstrInfo.cpp | 474 +- lib/Target/X86/X86InstrInfo.h | 13 +- lib/Target/X86/X86InstrInfo.td | 154 +- lib/Target/X86/X86InstrMMX.td | 94 +- lib/Target/X86/X86InstrSSE.td | 143 +- lib/Target/X86/X86InstrSVM.td | 4 +- lib/Target/X86/X86InstrSystem.td | 39 +- lib/Target/X86/X86InstrVecCompiler.td | 83 +- lib/Target/X86/X86InstrXOP.td | 97 +- lib/Target/X86/X86InstructionSelector.cpp | 83 +- lib/Target/X86/X86IntrinsicsInfo.h | 51 +- lib/Target/X86/X86LegalizerInfo.cpp | 32 +- lib/Target/X86/X86MCInstLower.cpp | 26 + lib/Target/X86/X86MacroFusion.cpp | 1 - lib/Target/X86/X86RegisterBankInfo.cpp | 21 + lib/Target/X86/X86RegisterInfo.cpp | 2 +- lib/Target/X86/X86RegisterInfo.td | 5 - lib/Target/X86/X86RetpolineThunks.cpp | 265 + lib/Target/X86/X86SchedBroadwell.td | 388 +- lib/Target/X86/X86SchedHaswell.td | 376 +- lib/Target/X86/X86SchedSandyBridge.td | 238 +- lib/Target/X86/X86SchedSkylakeClient.td | 396 +- lib/Target/X86/X86SchedSkylakeServer.td | 446 +- lib/Target/X86/X86ScheduleBtVer2.td | 194 +- lib/Target/X86/X86ScheduleZnver1.td | 123 +- lib/Target/X86/X86Subtarget.cpp | 29 +- lib/Target/X86/X86Subtarget.h | 81 +- lib/Target/X86/X86TargetMachine.cpp | 74 +- lib/Target/X86/X86TargetTransformInfo.cpp | 56 +- lib/Target/X86/X86TargetTransformInfo.h | 1 + lib/Target/X86/X86WinAllocaExpander.cpp | 26 +- lib/Target/XCore/XCoreRegisterInfo.h | 2 + lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp | 2 +- .../AggressiveInstCombine.cpp | 116 + .../AggressiveInstCombineInternal.h | 122 + .../AggressiveInstCombine/CMakeLists.txt | 11 + lib/Transforms/AggressiveInstCombine/LLVMBuild.txt | 22 + .../AggressiveInstCombine/TruncInstCombine.cpp | 417 + lib/Transforms/CMakeLists.txt | 1 + lib/Transforms/Coroutines/CoroFrame.cpp | 3 +- lib/Transforms/Coroutines/CoroSplit.cpp | 18 +- lib/Transforms/IPO/AlwaysInliner.cpp | 3 +- lib/Transforms/IPO/ArgumentPromotion.cpp | 18 +- lib/Transforms/IPO/BlockExtractor.cpp | 174 + lib/Transforms/IPO/CMakeLists.txt | 2 + lib/Transforms/IPO/DeadArgumentElimination.cpp | 46 +- lib/Transforms/IPO/FunctionAttrs.cpp | 6 +- lib/Transforms/IPO/FunctionImport.cpp | 90 +- lib/Transforms/IPO/GlobalOpt.cpp | 335 +- lib/Transforms/IPO/IPO.cpp | 2 +- lib/Transforms/IPO/LLVMBuild.txt | 2 +- lib/Transforms/IPO/LoopExtractor.cpp | 152 - lib/Transforms/IPO/LowerTypeTests.cpp | 62 +- lib/Transforms/IPO/PartialInlining.cpp | 8 +- lib/Transforms/IPO/PassManagerBuilder.cpp | 4 + lib/Transforms/IPO/SampleProfile.cpp | 46 +- lib/Transforms/IPO/SyntheticCountsPropagation.cpp | 140 + lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 97 +- lib/Transforms/IPO/WholeProgramDevirt.cpp | 2 +- lib/Transforms/InstCombine/InstCombineAddSub.cpp | 52 +- lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 97 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 49 +- lib/Transforms/InstCombine/InstCombineCasts.cpp | 253 +- lib/Transforms/InstCombine/InstCombineCompares.cpp | 72 +- lib/Transforms/InstCombine/InstCombineInternal.h | 3 +- .../InstCombine/InstCombineMulDivRem.cpp | 984 +- lib/Transforms/InstCombine/InstCombineSelect.cpp | 237 +- lib/Transforms/InstCombine/InstCombineShifts.cpp | 10 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 3 +- .../InstCombine/InstructionCombining.cpp | 72 +- .../Instrumentation/AddressSanitizer.cpp | 7 +- .../Instrumentation/DataFlowSanitizer.cpp | 122 +- .../Instrumentation/HWAddressSanitizer.cpp | 286 +- lib/Transforms/Instrumentation/InstrProfiling.cpp | 39 +- lib/Transforms/Instrumentation/MemorySanitizer.cpp | 43 +- .../Instrumentation/PGOInstrumentation.cpp | 3 +- lib/Transforms/LLVMBuild.txt | 2 +- lib/Transforms/ObjCARC/ObjCARC.h | 20 + lib/Transforms/ObjCARC/ObjCARCContract.cpp | 11 +- lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 5 + lib/Transforms/Scalar/AlignmentFromAssumptions.cpp | 58 +- lib/Transforms/Scalar/BDCE.cpp | 2 + lib/Transforms/Scalar/CallSiteSplitting.cpp | 312 +- .../Scalar/CorrelatedValuePropagation.cpp | 8 +- lib/Transforms/Scalar/DCE.cpp | 3 + lib/Transforms/Scalar/DeadStoreElimination.cpp | 135 +- lib/Transforms/Scalar/EarlyCSE.cpp | 1 + lib/Transforms/Scalar/GVN.cpp | 1 + lib/Transforms/Scalar/GVNHoist.cpp | 3 +- .../Scalar/InductiveRangeCheckElimination.cpp | 83 +- lib/Transforms/Scalar/InferAddressSpaces.cpp | 20 +- lib/Transforms/Scalar/JumpThreading.cpp | 300 +- lib/Transforms/Scalar/LICM.cpp | 68 +- lib/Transforms/Scalar/LLVMBuild.txt | 2 +- lib/Transforms/Scalar/LoopDataPrefetch.cpp | 4 +- lib/Transforms/Scalar/LoopDistribute.cpp | 2 +- lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 11 +- lib/Transforms/Scalar/LoopInterchange.cpp | 94 +- lib/Transforms/Scalar/LoopPredication.cpp | 36 +- lib/Transforms/Scalar/LoopRotation.cpp | 36 +- lib/Transforms/Scalar/LoopStrengthReduce.cpp | 11 +- lib/Transforms/Scalar/LoopUnrollPass.cpp | 2 +- lib/Transforms/Scalar/LoopVersioningLICM.cpp | 57 +- lib/Transforms/Scalar/MergeICmps.cpp | 65 +- lib/Transforms/Scalar/MergedLoadStoreMotion.cpp | 49 +- lib/Transforms/Scalar/NewGVN.cpp | 8 +- lib/Transforms/Scalar/RewriteStatepointsForGC.cpp | 53 +- lib/Transforms/Scalar/SCCP.cpp | 95 +- lib/Transforms/Scalar/SROA.cpp | 113 +- .../Scalar/SeparateConstOffsetFromGEP.cpp | 4 +- lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 11 +- lib/Transforms/Scalar/Sink.cpp | 2 +- lib/Transforms/Scalar/StructurizeCFG.cpp | 110 +- lib/Transforms/Utils/BasicBlockUtils.cpp | 37 +- lib/Transforms/Utils/BuildLibCalls.cpp | 13 + lib/Transforms/Utils/CloneFunction.cpp | 4 +- lib/Transforms/Utils/CloneModule.cpp | 35 +- lib/Transforms/Utils/CodeExtractor.cpp | 9 +- lib/Transforms/Utils/FunctionImportUtils.cpp | 12 +- lib/Transforms/Utils/GlobalStatus.cpp | 33 +- lib/Transforms/Utils/InlineFunction.cpp | 32 +- lib/Transforms/Utils/LCSSA.cpp | 9 +- lib/Transforms/Utils/LibCallsShrinkWrap.cpp | 5 +- lib/Transforms/Utils/Local.cpp | 346 +- lib/Transforms/Utils/LoopUnroll.cpp | 4 +- lib/Transforms/Utils/LoopUnrollPeel.cpp | 7 +- lib/Transforms/Utils/LoopUtils.cpp | 281 +- lib/Transforms/Utils/LowerMemIntrinsics.cpp | 14 +- lib/Transforms/Utils/SimplifyCFG.cpp | 45 +- lib/Transforms/Utils/SimplifyLibCalls.cpp | 69 +- lib/Transforms/Utils/SplitModule.cpp | 2 +- lib/Transforms/Utils/ValueMapper.cpp | 19 +- lib/Transforms/Vectorize/LoadStoreVectorizer.cpp | 35 +- .../Vectorize/LoopVectorizationPlanner.h | 3 + lib/Transforms/Vectorize/LoopVectorize.cpp | 318 +- lib/Transforms/Vectorize/SLPVectorizer.cpp | 703 +- lib/XRay/Trace.cpp | 7 +- runtimes/CMakeLists.txt | 3 + test/Analysis/AliasSet/memtransfer.ll | 20 +- test/Analysis/BasicAA/assume.ll | 12 +- test/Analysis/BasicAA/cs-cs.ll | 212 +- test/Analysis/BasicAA/gep-and-alias.ll | 4 +- test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll | 10 +- test/Analysis/BasicAA/guards.ll | 12 +- test/Analysis/BasicAA/modref.ll | 20 +- test/Analysis/BasicAA/pr35843.ll | 12 + test/Analysis/BranchProbabilityInfo/loop.ll | 88 + test/Analysis/CallGraph/no-intrinsics.ll | 4 +- .../ConstantFolding/gep-constanfolding-error.ll | 6 +- test/Analysis/CostModel/AMDGPU/addrspacecast.ll | 48 +- test/Analysis/CostModel/X86/arith-fp.ll | 241 +- test/Analysis/CostModel/X86/arith.ll | 14 +- test/Analysis/CostModel/X86/cast.ll | 12 +- test/Analysis/CostModel/X86/intrinsic-cost.ll | 2 +- test/Analysis/CostModel/X86/vshift-shl-cost.ll | 22 +- test/Analysis/DependenceAnalysis/Preliminary.ll | 2 +- test/Analysis/GlobalsModRef/memset-escape.ll | 4 +- test/Analysis/GlobalsModRef/no-escape.ll | 2 +- test/Analysis/GlobalsModRef/pr12351.ll | 4 +- test/Analysis/GlobalsModRef/pr35899-dbg-value.ll | 57 + test/Analysis/GlobalsModRef/volatile-instrs.ll | 6 +- .../LazyValueAnalysis/lvi-after-jumpthreading.ll | 3 + test/Analysis/Lint/memintrin.ll | 61 + test/Analysis/Lint/noalias-byval.ll | 8 +- test/Analysis/MemorySSA/basicaa-memcpy.ll | 6 +- test/Analysis/ScalarEvolution/avoid-smax-1.ll | 12 +- test/Analysis/ScalarEvolution/pr35890.ll | 44 + test/Analysis/ScalarEvolution/trip-count.ll | 4 +- test/Analysis/ScalarEvolution/trip-count3.ll | 6 +- test/Analysis/ScalarEvolution/unknown_phis.ll | 54 + test/Analysis/TypeBasedAliasAnalysis/aggregates.ll | 138 + .../TypeBasedAliasAnalysis/functionattrs.ll | 6 +- test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll | 8 +- .../TypeBasedAliasAnalysis/tbaa-path-new.ll | 306 + test/Analysis/ValueTracking/select-pattern.ll | 46 + test/Assembler/2002-07-31-SlashInString.ll | 2 +- test/Assembler/DIEnumerator.ll | 85 + test/Assembler/call-nonzero-program-addrspace-2.ll | 11 + test/Assembler/call-nonzero-program-addrspace.ll | 13 + .../datalayout-alloca-addrspace-mismatch-0.ll | 4 +- .../datalayout-alloca-addrspace-mismatch-1.ll | 4 +- .../datalayout-alloca-addrspace-mismatch-2.ll | 4 +- test/Assembler/datalayout-program-addrspace.ll | 5 + test/Assembler/debug-info.ll | 19 +- test/Assembler/drop-debug-info-nonzero-alloca.ll | 25 + test/Assembler/ifunc-dsolocal-daig.ll | 9 - test/Assembler/ifunc-dsolocal.ll | 9 + .../invalid-datalayout-alloca-addrspace.ll | 2 +- .../invalid-datalayout-program-addrspace.ll | 4 + test/Assembler/invalid-disubrange-count-node.ll | 4 + test/Assembler/invoke-nonzero-program-addrspace.ll | 18 + test/Bindings/llvm-c/echo.ll | 1 + test/Bitcode/compatibility-3.6.ll | 4 +- test/Bitcode/compatibility-3.7.ll | 4 +- test/Bitcode/compatibility-3.8.ll | 8 +- test/Bitcode/compatibility-3.9.ll | 8 +- test/Bitcode/compatibility-4.0.ll | 8 +- test/Bitcode/compatibility-5.0.ll | 8 +- test/Bitcode/compatibility.ll | 2 - test/Bitcode/disubrange-v0.ll | 41 + test/Bitcode/disubrange-v0.ll.bc | Bin 0 -> 1492 bytes test/Bitcode/disubrange.ll | 49 + test/Bitcode/dso_location.ll | 16 +- test/Bitcode/metadata-source.ll | 13 + test/Bitcode/metadata-source.ll.bc | Bin 0 -> 1028 bytes test/Bitcode/standardCIntrinsic.3.2.ll | 6 +- test/Bitcode/thinlto-alias.ll | 1 + test/Bitcode/thinlto-deadstrip-flag.ll | 20 + .../thinlto-function-summary-callgraph-pgo.ll | 1 + ...o-function-summary-callgraph-profile-summary.ll | 1 + .../thinlto-function-summary-callgraph-relbf.ll | 35 + ...ion-summary-callgraph-sample-profile-summary.ll | 1 + test/Bitcode/thinlto-function-summary-callgraph.ll | 1 + .../thinlto-function-summary-originalnames.ll | 1 + test/Bitcode/thinlto-function-summary-refgraph.ll | 2 +- test/Bitcode/thinlto-summary-linkage-types.ll | 4 +- test/Bitcode/thinlto-summary-section.ll | 6 +- test/Bitcode/upgrade-dbg-checksum.ll | 19 + test/Bitcode/upgrade-dbg-checksum.ll.bc | Bin 0 -> 1164 bytes test/Bitcode/upgrade-memory-intrinsics.ll | 36 + test/BugPoint/compile-custom.ll | 2 +- test/BugPoint/crash-narrowfunctiontest.ll | 2 +- test/BugPoint/invalid-debuginfo.ll | 2 +- test/BugPoint/metadata.ll | 6 +- test/BugPoint/named-md.ll | 2 +- test/BugPoint/remove_arguments_test.ll | 2 +- test/BugPoint/replace-funcs-with-null.ll | 2 +- test/BugPoint/unsymbolized.ll | 2 + .../AArch64/GlobalISel/arm64-callingconv-ios.ll | 6 +- .../AArch64/GlobalISel/arm64-callingconv.ll | 74 +- test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 32 +- .../GlobalISel/arm64-irtranslator-fmuladd.ll | 34 + .../AArch64/GlobalISel/arm64-irtranslator.ll | 585 +- .../AArch64/GlobalISel/arm64-regbankselect.mir | 286 +- .../AArch64/GlobalISel/call-translator-ios.ll | 22 +- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 114 +- test/CodeGen/AArch64/GlobalISel/debug-insts.ll | 12 +- test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll | 24 +- .../AArch64/GlobalISel/fallback-nofastisel.ll | 11 + .../GlobalISel/fp128-legalize-crash-pr35690.mir | 8 +- test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir | 127 + .../AArch64/GlobalISel/gisel-commandline-option.ll | 3 + .../AArch64/GlobalISel/irtranslator-bitcast.ll | 2 +- .../AArch64/GlobalISel/irtranslator-exceptions.ll | 22 +- .../irtranslator-volatile-load-pr36018.ll | 14 + test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 110 +- test/CodeGen/AArch64/GlobalISel/legalize-and.mir | 18 +- .../AArch64/GlobalISel/legalize-atomicrmw.mir | 40 +- test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 22 +- .../GlobalISel/legalize-cmpxchg-with-success.mir | 20 +- .../AArch64/GlobalISel/legalize-cmpxchg.mir | 40 +- .../AArch64/GlobalISel/legalize-combines.mir | 34 +- .../AArch64/GlobalISel/legalize-constant.mir | 42 +- test/CodeGen/AArch64/GlobalISel/legalize-div.mir | 18 +- .../AArch64/GlobalISel/legalize-exceptions.ll | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-ext.mir | 78 +- .../AArch64/GlobalISel/legalize-extracts.mir | 46 +- test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir | 18 +- test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir | 20 +- test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir | 131 +- test/CodeGen/AArch64/GlobalISel/legalize-gep.mir | 14 +- .../GlobalISel/legalize-ignore-non-generic.mir | 10 +- .../AArch64/GlobalISel/legalize-inserts.mir | 68 +- test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir | 112 +- .../AArch64/GlobalISel/legalize-load-store.mir | 26 +- .../AArch64/GlobalISel/legalize-merge-values.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-mul.mir | 50 +- .../GlobalISel/legalize-nonpowerof2eltsvec.mir | 10 +- test/CodeGen/AArch64/GlobalISel/legalize-or.mir | 47 +- test/CodeGen/AArch64/GlobalISel/legalize-phi.mir | 122 +- test/CodeGen/AArch64/GlobalISel/legalize-pow.mir | 30 +- test/CodeGen/AArch64/GlobalISel/legalize-rem.mir | 84 +- test/CodeGen/AArch64/GlobalISel/legalize-shift.mir | 22 +- .../CodeGen/AArch64/GlobalISel/legalize-simple.mir | 94 +- test/CodeGen/AArch64/GlobalISel/legalize-sub.mir | 14 +- test/CodeGen/AArch64/GlobalISel/legalize-undef.mir | 2 +- .../AArch64/GlobalISel/legalize-unmerge-values.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-xor.mir | 14 +- .../GlobalISel/localizer-in-O0-pipeline.mir | 10 +- test/CodeGen/AArch64/GlobalISel/localizer.mir | 8 +- .../GlobalISel/machine-cse-mid-pipeline.mir | 181 + test/CodeGen/AArch64/GlobalISel/no-regclass.mir | 12 +- .../CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir | 10 +- .../AArch64/GlobalISel/regbankselect-dbg-value.mir | 12 +- .../AArch64/GlobalISel/regbankselect-default.mir | 262 +- .../GlobalISel/regbankselect-reg_sequence.mir | 4 +- .../AArch64/GlobalISel/select-atomicrmw.mir | 112 +- test/CodeGen/AArch64/GlobalISel/select-binop.mir | 462 +- .../GlobalISel/select-bitcast-bigendian.mir | 13 +- test/CodeGen/AArch64/GlobalISel/select-bitcast.mir | 106 +- test/CodeGen/AArch64/GlobalISel/select-br.mir | 8 +- test/CodeGen/AArch64/GlobalISel/select-bswap.mir | 20 +- test/CodeGen/AArch64/GlobalISel/select-cbz.mir | 24 +- test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir | 20 +- .../CodeGen/AArch64/GlobalISel/select-constant.mir | 24 +- .../AArch64/GlobalISel/select-dbg-value.mir | 22 +- test/CodeGen/AArch64/GlobalISel/select-fma.mir | 18 +- .../CodeGen/AArch64/GlobalISel/select-fp-casts.mir | 220 +- .../AArch64/GlobalISel/select-gv-cmodel-large.mir | 61 + test/CodeGen/AArch64/GlobalISel/select-imm.mir | 12 +- .../AArch64/GlobalISel/select-implicit-def.mir | 23 +- .../AArch64/GlobalISel/select-insert-extract.mir | 102 +- test/CodeGen/AArch64/GlobalISel/select-int-ext.mir | 122 +- .../AArch64/GlobalISel/select-int-ptr-casts.mir | 62 +- .../GlobalISel/select-intrinsic-aarch64-hint.mir | 2 +- .../GlobalISel/select-intrinsic-aarch64-sdiv.mir | 14 +- .../GlobalISel/select-intrinsic-crypto-aesmc.mir | 14 +- test/CodeGen/AArch64/GlobalISel/select-load.mir | 206 +- test/CodeGen/AArch64/GlobalISel/select-mul.mir | 34 + test/CodeGen/AArch64/GlobalISel/select-muladd.mir | 18 +- .../AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir | 10 +- test/CodeGen/AArch64/GlobalISel/select-phi.mir | 20 +- test/CodeGen/AArch64/GlobalISel/select-pr32733.mir | 12 +- test/CodeGen/AArch64/GlobalISel/select-store.mir | 164 +- test/CodeGen/AArch64/GlobalISel/select-trunc.mir | 33 +- .../GlobalISel/select-with-no-legality-check.mir | 4543 +++ test/CodeGen/AArch64/GlobalISel/select-xor.mir | 64 +- test/CodeGen/AArch64/GlobalISel/select.mir | 108 +- test/CodeGen/AArch64/GlobalISel/translate-gep.ll | 58 +- .../AArch64/GlobalISel/varargs-ios-translator.ll | 2 +- test/CodeGen/AArch64/GlobalISel/vastart.ll | 2 +- .../AArch64/GlobalISel/verify-regbankselected.mir | 4 +- .../CodeGen/AArch64/GlobalISel/verify-selected.mir | 6 +- test/CodeGen/AArch64/PBQP-csr.ll | 4 +- ...64-DAGCombine-findBetterNeighborChains-crash.ll | 6 +- test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir | 86 +- test/CodeGen/AArch64/aarch64-fold-lslfast.ll | 9 +- test/CodeGen/AArch64/aarch64-stp-cluster.ll | 56 +- test/CodeGen/AArch64/aarch64-vuzp.ll | 60 + .../AArch64/arm64-2012-05-07-MemcpyAlignBug.ll | 4 +- test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll | 16 +- test/CodeGen/AArch64/arm64-aapcs.ll | 22 +- test/CodeGen/AArch64/arm64-abi-varargs.ll | 7 +- test/CodeGen/AArch64/arm64-abi_align.ll | 18 +- test/CodeGen/AArch64/arm64-addr-type-promotion.ll | 1 + test/CodeGen/AArch64/arm64-arith.ll | 3 +- .../AArch64/arm64-big-endian-bitconverts.ll | 270 +- test/CodeGen/AArch64/arm64-cse.ll | 2 +- test/CodeGen/AArch64/arm64-csldst-mmo.ll | 4 +- test/CodeGen/AArch64/arm64-ext.ll | 13 - test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll | 24 +- test/CodeGen/AArch64/arm64-ldp-cluster.ll | 69 +- .../AArch64/arm64-ldst-unscaled-pre-post.mir | 106 +- test/CodeGen/AArch64/arm64-memcpy-inline.ll | 20 +- test/CodeGen/AArch64/arm64-memset-inline.ll | 8 +- test/CodeGen/AArch64/arm64-memset-to-bzero.ll | 8 +- .../AArch64/arm64-misaligned-memcpy-inline.ll | 4 +- test/CodeGen/AArch64/arm64-misched-basic-A53.ll | 6 +- test/CodeGen/AArch64/arm64-misched-basic-A57.ll | 6 +- .../AArch64/arm64-misched-forwarding-A53.ll | 2 +- test/CodeGen/AArch64/arm64-misched-memdep-bug.ll | 8 +- test/CodeGen/AArch64/arm64-misched-multimmo.ll | 4 +- test/CodeGen/AArch64/arm64-neon-2velem.ll | 59 + .../AArch64/arm64-neon-compare-instructions.ll | 87 +- test/CodeGen/AArch64/arm64-regress-opt-cmp.mir | 14 +- test/CodeGen/AArch64/arm64-stp-aa.ll | 2 +- test/CodeGen/AArch64/arm64-stp.ll | 10 +- test/CodeGen/AArch64/arm64-stur.ll | 6 +- test/CodeGen/AArch64/arm64-vector-insertion.ll | 9 +- test/CodeGen/AArch64/arm64-virtual_base.ll | 4 +- test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll | 6 +- test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll | 70 +- test/CodeGen/AArch64/atomic-ops-lse.ll | 313 +- test/CodeGen/AArch64/big-callframe.ll | 16 + test/CodeGen/AArch64/bitfield-extract.ll | 17 + test/CodeGen/AArch64/bitfield-insert.ll | 17 + test/CodeGen/AArch64/bitfield.ll | 4 +- test/CodeGen/AArch64/build-one-lane.ll | 226 +- test/CodeGen/AArch64/ccmp-successor-probs.mir | 18 +- test/CodeGen/AArch64/cfi_restore.mir | 30 +- test/CodeGen/AArch64/cmpxchg-idioms.ll | 3 +- test/CodeGen/AArch64/copy-zero-reg.ll | 47 + test/CodeGen/AArch64/copyprop.mir | 104 + test/CodeGen/AArch64/dllexport.ll | 57 +- test/CodeGen/AArch64/dllimport.ll | 18 +- test/CodeGen/AArch64/emutls.ll | 2 + test/CodeGen/AArch64/emutls_generic.ll | 12 + test/CodeGen/AArch64/expand-select.ll | 61 + test/CodeGen/AArch64/f16-instructions.ll | 32 +- test/CodeGen/AArch64/falkor-hwpf-fix.mir | 306 +- test/CodeGen/AArch64/fast-isel-memcpy.ll | 4 +- .../fast-regalloc-empty-bb-with-liveins.mir | 26 + test/CodeGen/AArch64/flags-multiuse.ll | 5 +- test/CodeGen/AArch64/fp16-v4-instructions.ll | 261 +- test/CodeGen/AArch64/func-argpassing.ll | 8 +- test/CodeGen/AArch64/i128-fast-isel-fallback.ll | 2 +- test/CodeGen/AArch64/illegal-float-ops.ll | 53 + .../AArch64/ldp-stp-scaled-unscaled-pairs.ll | 4 +- test/CodeGen/AArch64/ldst-opt-aa.mir | 16 +- test/CodeGen/AArch64/ldst-opt-zr-clobber.mir | 16 +- test/CodeGen/AArch64/ldst-opt.ll | 2 +- test/CodeGen/AArch64/ldst-opt.mir | 144 +- test/CodeGen/AArch64/ldst-paired-aliasing.ll | 4 +- test/CodeGen/AArch64/ldst-zero.ll | 4 +- test/CodeGen/AArch64/live-interval-analysis.mir | 10 +- test/CodeGen/AArch64/loh.mir | 206 +- test/CodeGen/AArch64/machine-combiner-madd.ll | 5 +- test/CodeGen/AArch64/machine-combiner.ll | 2 +- test/CodeGen/AArch64/machine-combiner.mir | 24 +- test/CodeGen/AArch64/machine-copy-remove.mir | 374 +- test/CodeGen/AArch64/machine-dead-copy.mir | 42 +- test/CodeGen/AArch64/machine-outliner.mir | 181 +- test/CodeGen/AArch64/machine-scheduler.mir | 18 +- test/CodeGen/AArch64/machine-sink-zr.mir | 14 +- test/CodeGen/AArch64/machine-zero-copy-remove.mir | 424 +- test/CodeGen/AArch64/max-jump-table.ll | 11 +- test/CodeGen/AArch64/memcpy-f128.ll | 4 +- test/CodeGen/AArch64/merge-store-dependency.ll | 6 +- test/CodeGen/AArch64/merge-store.ll | 12 +- .../CodeGen/AArch64/mergestores_noimplicitfloat.ll | 4 +- test/CodeGen/AArch64/minmax-of-minmax.ll | 1413 +- test/CodeGen/AArch64/misched-fusion-addr.ll | 114 + test/CodeGen/AArch64/misched-fusion-aes.ll | 1 + test/CodeGen/AArch64/misched-fusion-csel.ll | 30 + test/CodeGen/AArch64/misched-fusion-lit.ll | 1 + test/CodeGen/AArch64/misched-stp.ll | 6 +- test/CodeGen/AArch64/movimm-wzr.mir | 8 +- test/CodeGen/AArch64/neg-imm.ll | 4 +- test/CodeGen/AArch64/neon-bitwise-instructions.ll | 313 +- test/CodeGen/AArch64/neon-compare-instructions.ll | 87 +- test/CodeGen/AArch64/neon-extract.ll | 2 + test/CodeGen/AArch64/neon-scalar-copy.ll | 8 +- test/CodeGen/AArch64/no-quad-ldp-stp.ll | 19 +- test/CodeGen/AArch64/phi-dbg.ll | 2 +- test/CodeGen/AArch64/pr33172.ll | 4 +- .../AArch64/preferred-function-alignment.ll | 3 +- test/CodeGen/AArch64/reg-scavenge-frame.mir | 136 +- test/CodeGen/AArch64/regcoal-physreg.mir | 108 +- test/CodeGen/AArch64/scheduledag-constreg.mir | 16 +- test/CodeGen/AArch64/spill-fold.mir | 82 + test/CodeGen/AArch64/spill-undef.mir | 16 +- test/CodeGen/AArch64/sqrt-fastmath.ll | 575 +- test/CodeGen/AArch64/strqro.ll | 5 +- test/CodeGen/AArch64/strqu.ll | 28 + test/CodeGen/AArch64/sub1.ll | 16 + test/CodeGen/AArch64/swifterror.ll | 15 +- test/CodeGen/AArch64/tailcall-mem-intrinsics.ll | 12 +- test/CodeGen/AArch64/tailcall-string-rvo.ll | 4 +- test/CodeGen/AArch64/tailcall_misched_graph.ll | 2 +- test/CodeGen/AArch64/taildup-cfi.ll | 96 + test/CodeGen/AArch64/win-alloca.ll | 23 + test/CodeGen/AArch64/win64_vararg.ll | 33 +- .../AMDGPU/GlobalISel/inst-select-load-flat.mir | 8 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 44 +- .../AMDGPU/GlobalISel/inst-select-store-flat.mir | 10 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 32 +- test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir | 12 +- test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 12 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 8 +- .../AMDGPU/GlobalISel/legalize-constant.mir | 65 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 105 + test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir | 8 +- test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir | 35 + test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir | 12 +- test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir | 14 + test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir | 22 + test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 10 +- test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir | 18 + test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 12 +- test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 8 +- test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 12 +- test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 18 + test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 14 + .../GlobalISel/regbankselect-amdgcn-exp-compr.mir | 67 + .../AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir | 77 + .../GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir | 66 + .../AMDGPU/GlobalISel/regbankselect-and.mir | 68 + .../AMDGPU/GlobalISel/regbankselect-bitcast.mir | 31 + .../AMDGPU/GlobalISel/regbankselect-default.mir | 52 + .../AMDGPU/GlobalISel/regbankselect-extract.mir | 31 + .../AMDGPU/GlobalISel/regbankselect-fadd.mir | 69 + .../AMDGPU/GlobalISel/regbankselect-fcmp.mir | 69 + .../AMDGPU/GlobalISel/regbankselect-fmul.mir | 69 + .../AMDGPU/GlobalISel/regbankselect-fptosi.mir | 31 + .../AMDGPU/GlobalISel/regbankselect-fptoui.mir | 31 + .../AMDGPU/GlobalISel/regbankselect-icmp.mir | 67 + .../AMDGPU/GlobalISel/regbankselect-maxnum.mir | 66 + .../AMDGPU/GlobalISel/regbankselect-minnum.mir | 66 + .../CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir | 68 + .../AMDGPU/GlobalISel/regbankselect-shl.mir | 68 + .../AMDGPU/GlobalISel/regbankselect-trunc.mir | 31 + .../AMDGPU/GlobalISel/regbankselect-xor.mir | 68 + .../AMDGPU/GlobalISel/regbankselect-zext.mir | 31 + test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir | 14 +- test/CodeGen/AMDGPU/GlobalISel/smrd.ll | 36 +- test/CodeGen/AMDGPU/InlineAsmCrash.ll | 4 +- test/CodeGen/AMDGPU/add.v2i16.ll | 10 +- test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll | 4 +- test/CodeGen/AMDGPU/addrspacecast.ll | 86 +- test/CodeGen/AMDGPU/alloca.ll | 12 + test/CodeGen/AMDGPU/amdgcn.bitcast.ll | 4 +- test/CodeGen/AMDGPU/amdgcn.private-memory.ll | 14 +- test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 4 +- test/CodeGen/AMDGPU/amdgpu-inline.ll | 102 +- test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 347 +- test/CodeGen/AMDGPU/amdpal.ll | 32 +- test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll | 34 + .../AMDGPU/annotate-kernel-features-hsa-call.ll | 40 +- .../CodeGen/AMDGPU/annotate-kernel-features-hsa.ll | 76 +- test/CodeGen/AMDGPU/array-ptr-calc-i32.ll | 10 +- test/CodeGen/AMDGPU/bfi_int.ll | 158 +- test/CodeGen/AMDGPU/bitreverse.ll | 13 +- test/CodeGen/AMDGPU/branch-relaxation.ll | 13 +- test/CodeGen/AMDGPU/break-smem-soft-clauses.mir | 252 +- test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir | 360 +- test/CodeGen/AMDGPU/bswap.ll | 125 +- test/CodeGen/AMDGPU/buffer-schedule.ll | 53 + test/CodeGen/AMDGPU/byval-frame-setup.ll | 130 +- test/CodeGen/AMDGPU/call-argument-types.ll | 50 +- test/CodeGen/AMDGPU/call-graph-register-usage.ll | 16 +- test/CodeGen/AMDGPU/callee-frame-setup.ll | 10 +- test/CodeGen/AMDGPU/callee-special-input-sgprs.ll | 172 +- test/CodeGen/AMDGPU/callee-special-input-vgprs.ll | 20 +- test/CodeGen/AMDGPU/captured-frame-index.ll | 136 +- test/CodeGen/AMDGPU/cf-loop-on-constant.ll | 2 +- test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll | 90 +- test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 106 +- test/CodeGen/AMDGPU/clamp-omod-special-case.mir | 162 +- test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir | 26 +- test/CodeGen/AMDGPU/cluster-flat-loads.mir | 6 +- test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll | 2 - test/CodeGen/AMDGPU/coalescer-subreg-join.mir | 18 +- test/CodeGen/AMDGPU/collapse-endcf.ll | 4 +- test/CodeGen/AMDGPU/combine-cond-add-sub.ll | 8 +- test/CodeGen/AMDGPU/commute-compares.ll | 6 +- test/CodeGen/AMDGPU/concat_vectors.ll | 12 + .../CodeGen/AMDGPU/constant-address-space-32bit.ll | 288 + test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 366 +- test/CodeGen/AMDGPU/copy-to-reg.ll | 10 +- test/CodeGen/AMDGPU/ctpop16.ll | 334 + test/CodeGen/AMDGPU/cttz_zero_undef.ll | 3 +- test/CodeGen/AMDGPU/dead_copy.mir | 20 +- test/CodeGen/AMDGPU/debug-value2.ll | 436 + test/CodeGen/AMDGPU/detect-dead-lanes.mir | 26 +- test/CodeGen/AMDGPU/ds-combine-large-stride.ll | 44 +- test/CodeGen/AMDGPU/ds_read2.ll | 42 + test/CodeGen/AMDGPU/early-if-convert-cost.ll | 4 +- test/CodeGen/AMDGPU/early-if-convert.ll | 24 +- test/CodeGen/AMDGPU/elf-header-flags-mach.ll | 88 + test/CodeGen/AMDGPU/elf-header-flags-xnack.ll | 15 + test/CodeGen/AMDGPU/elf-header-osabi.ll | 21 + test/CodeGen/AMDGPU/elf-header.ll | 49 - test/CodeGen/AMDGPU/elf-notes.ll | 30 +- test/CodeGen/AMDGPU/endpgm-dce.mir | 130 +- test/CodeGen/AMDGPU/enqueue-kernel.ll | 97 +- test/CodeGen/AMDGPU/extload-align.ll | 2 +- test/CodeGen/AMDGPU/extload-private.ll | 16 +- test/CodeGen/AMDGPU/extract_vector_elt-f16.ll | 12 +- test/CodeGen/AMDGPU/extract_vector_elt-i16.ll | 12 +- test/CodeGen/AMDGPU/fence-barrier.ll | 123 +- test/CodeGen/AMDGPU/fix-vgpr-copies.mir | 30 +- test/CodeGen/AMDGPU/fix-wwm-liveness.mir | 44 +- test/CodeGen/AMDGPU/flat-address-space.ll | 108 +- .../AMDGPU/flat-for-global-subtarget-feature.ll | 8 +- test/CodeGen/AMDGPU/flat-load-clustering.mir | 38 +- test/CodeGen/AMDGPU/flat_atomics.ll | 684 +- test/CodeGen/AMDGPU/flat_atomics_i64.ll | 678 +- test/CodeGen/AMDGPU/fmuladd.f16.ll | 4 - test/CodeGen/AMDGPU/fold-cndmask.mir | 20 +- test/CodeGen/AMDGPU/fold-imm-f16-f32.mir | 709 + test/CodeGen/AMDGPU/fold-immediate-output-mods.mir | 112 +- test/CodeGen/AMDGPU/fold-implicit-operand.mir | 14 + test/CodeGen/AMDGPU/fold-multiple.mir | 40 + test/CodeGen/AMDGPU/fold-operands-order.mir | 8 +- test/CodeGen/AMDGPU/frame-index-elimination.ll | 98 +- test/CodeGen/AMDGPU/function-args.ll | 16 +- test/CodeGen/AMDGPU/function-returns.ll | 32 +- test/CodeGen/AMDGPU/global-constant.ll | 18 +- test/CodeGen/AMDGPU/gv-const-addrspace.ll | 30 +- test/CodeGen/AMDGPU/hazard-inlineasm.mir | 4 +- test/CodeGen/AMDGPU/hazard.mir | 32 +- test/CodeGen/AMDGPU/hsa-func-align.ll | 4 +- test/CodeGen/AMDGPU/hsa-func.ll | 8 +- .../AMDGPU/hsa-metadata-from-llvm-ir-full.ll | 58 +- test/CodeGen/AMDGPU/hsa-metadata-images.ll | 2 +- .../AMDGPU/hsa-metadata-kernel-debug-props.ll | 4 +- test/CodeGen/AMDGPU/hsa-note-no-func.ll | 2 - test/CodeGen/AMDGPU/huge-private-buffer.ll | 12 +- test/CodeGen/AMDGPU/image-schedule.ll | 56 + test/CodeGen/AMDGPU/indirect-addressing-si.ll | 62 +- test/CodeGen/AMDGPU/indirect-private-64.ll | 36 +- test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir | 10 +- test/CodeGen/AMDGPU/insert-waits-callee.mir | 8 +- test/CodeGen/AMDGPU/insert-waits-exp.mir | 32 +- test/CodeGen/AMDGPU/insert_subreg.ll | 4 +- test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 46 +- test/CodeGen/AMDGPU/inserted-wait-states.mir | 204 +- test/CodeGen/AMDGPU/invalid-alloca.ll | 16 + .../AMDGPU/invariant-load-no-alias-store.ll | 4 +- test/CodeGen/AMDGPU/invert-br-undef-vcc.mir | 38 +- test/CodeGen/AMDGPU/kernarg-stack-alignment.ll | 20 +- test/CodeGen/AMDGPU/kernel-args.ll | 12 +- test/CodeGen/AMDGPU/large-alloca-compute.ll | 12 +- test/CodeGen/AMDGPU/large-alloca-graphics.ll | 20 +- .../AMDGPU/large-work-group-promote-alloca.ll | 4 +- test/CodeGen/AMDGPU/lds-alignment.ll | 130 +- test/CodeGen/AMDGPU/lds_atomic_f32.ll | 69 + test/CodeGen/AMDGPU/limit-coalesce.mir | 16 +- test/CodeGen/AMDGPU/liveness.mir | 2 +- test/CodeGen/AMDGPU/llvm.SI.load.dword.ll | 6 +- test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll | 92 +- test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll | 92 +- .../AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll | 41 + .../AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll | 50 + test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll | 84 + test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll | 84 + test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll | 164 + test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll | 164 + test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll | 8 +- test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.ll | 125 + .../AMDGPU/llvm.amdgcn.image.gather4.d16.ll | 137 + test/CodeGen/AMDGPU/llvm.amdgcn.image.ll | 24 +- .../CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.ll | 135 + .../AMDGPU/llvm.amdgcn.implicit.buffer.ptr.hsa.ll | 14 +- .../AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll | 22 +- test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll | 59 +- test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll | 34 +- .../AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll | 34 +- test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll | 17 + test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll | 8 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll | 3 +- .../CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll | 41 + .../AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll | 53 + test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll | 82 + test/CodeGen/AMDGPU/llvm.dbg.value.ll | 2 +- test/CodeGen/AMDGPU/llvm.memcpy.ll | 36 +- test/CodeGen/AMDGPU/load-constant-f64.ll | 4 +- test/CodeGen/AMDGPU/load-constant-i1.ll | 176 +- test/CodeGen/AMDGPU/load-constant-i16.ll | 160 +- test/CodeGen/AMDGPU/load-constant-i32.ll | 80 +- test/CodeGen/AMDGPU/load-constant-i64.ll | 24 +- test/CodeGen/AMDGPU/load-constant-i8.ll | 224 +- test/CodeGen/AMDGPU/load-hi16.ll | 132 +- test/CodeGen/AMDGPU/load-lo16.ll | 118 +- test/CodeGen/AMDGPU/local-stack-slot-offset.ll | 20 +- test/CodeGen/AMDGPU/lower-mem-intrinsics.ll | 42 +- .../AMDGPU/macro-fusion-cluster-vcc-uses.mir | 170 +- test/CodeGen/AMDGPU/mad24-get-global-id.ll | 10 +- test/CodeGen/AMDGPU/madak.ll | 78 +- .../AMDGPU/memory-legalizer-atomic-cmpxchg.ll | 806 +- .../AMDGPU/memory-legalizer-atomic-fence.ll | 50 +- .../AMDGPU/memory-legalizer-atomic-insert-end.mir | 122 + test/CodeGen/AMDGPU/memory-legalizer-atomic-rmw.ll | 354 +- .../AMDGPU/memory-legalizer-invalid-syncscope.ll | 28 +- test/CodeGen/AMDGPU/memory-legalizer-load.ll | 308 +- ...ory-legalizer-multiple-mem-operands-atomics.mir | 163 + ...galizer-multiple-mem-operands-nontemporal-1.mir | 161 + ...galizer-multiple-mem-operands-nontemporal-2.mir | 161 + test/CodeGen/AMDGPU/memory-legalizer-store.ll | 228 +- test/CodeGen/AMDGPU/merge-load-store-physreg.mir | 116 + test/CodeGen/AMDGPU/merge-load-store-vreg.mir | 60 + test/CodeGen/AMDGPU/merge-load-store.mir | 81 +- test/CodeGen/AMDGPU/merge-m0.mir | 74 +- test/CodeGen/AMDGPU/misched-killflags.mir | 62 +- test/CodeGen/AMDGPU/missing-store.ll | 8 +- test/CodeGen/AMDGPU/move-to-valu-worklist.ll | 2 +- test/CodeGen/AMDGPU/movrels-bug.mir | 12 +- test/CodeGen/AMDGPU/mubuf-offset-private.ll | 40 +- test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll | 24 +- test/CodeGen/AMDGPU/mubuf.ll | 12 +- test/CodeGen/AMDGPU/multi-divergent-exit-region.ll | 4 +- test/CodeGen/AMDGPU/multilevel-break.ll | 5 +- test/CodeGen/AMDGPU/nested-calls.ll | 10 +- test/CodeGen/AMDGPU/nested-loop-conditions.ll | 130 +- .../AMDGPU/no-initializer-constant-addrspace.ll | 8 +- test/CodeGen/AMDGPU/no-shrink-extloads.ll | 4 +- test/CodeGen/AMDGPU/nullptr.ll | 10 +- test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 94 +- test/CodeGen/AMDGPU/optimize-if-exec-masking.mir | 438 +- test/CodeGen/AMDGPU/pack.v2f16.ll | 14 +- test/CodeGen/AMDGPU/pack.v2i16.ll | 14 +- test/CodeGen/AMDGPU/parallelandifcollapse.ll | 38 +- test/CodeGen/AMDGPU/postra-norename.mir | 13 + test/CodeGen/AMDGPU/private-access-no-objects.ll | 8 +- test/CodeGen/AMDGPU/private-element-size.ll | 70 +- test/CodeGen/AMDGPU/private-memory-atomics.ll | 28 +- test/CodeGen/AMDGPU/private-memory-r600.ll | 9 +- .../AMDGPU/promote-alloca-bitcast-function.ll | 10 +- test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll | 72 +- test/CodeGen/AMDGPU/promote-alloca-globals.ll | 20 +- .../AMDGPU/promote-alloca-mem-intrinsics.ll | 30 +- test/CodeGen/AMDGPU/promote-alloca-no-opts.ll | 28 +- .../AMDGPU/promote-alloca-padding-size-estimate.ll | 56 +- .../AMDGPU/promote-alloca-stored-pointer-value.ll | 64 +- test/CodeGen/AMDGPU/r600-constant-array-fixup.ll | 6 +- test/CodeGen/AMDGPU/r600.alu-limits.ll | 6 +- test/CodeGen/AMDGPU/r600.private-memory.ll | 14 +- test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll | 15 +- test/CodeGen/AMDGPU/readcyclecounter.ll | 4 +- test/CodeGen/AMDGPU/readlane_exec0.mir | 20 +- test/CodeGen/AMDGPU/reduce-saveexec.mir | 92 +- test/CodeGen/AMDGPU/regcoal-subrange-join.mir | 44 +- test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 18 +- test/CodeGen/AMDGPU/regcoalesce-prune.mir | 8 +- .../rename-independent-subregs-mac-operands.mir | 66 +- test/CodeGen/AMDGPU/rename-independent-subregs.mir | 2 +- test/CodeGen/AMDGPU/ret.ll | 48 +- test/CodeGen/AMDGPU/sad.ll | 12 +- test/CodeGen/AMDGPU/salu-to-valu.ll | 110 +- .../AMDGPU/scalar-branch-missing-and-exec.ll | 54 + test/CodeGen/AMDGPU/scalar-store-cache-flush.mir | 16 +- test/CodeGen/AMDGPU/sched-crash-dbg-value.mir | 198 +- test/CodeGen/AMDGPU/schedule-regpressure.mir | 14 +- test/CodeGen/AMDGPU/scratch-buffer.ll | 62 +- test/CodeGen/AMDGPU/sdwa-gfx9.mir | 60 +- test/CodeGen/AMDGPU/sdwa-peephole-instr.mir | 468 +- test/CodeGen/AMDGPU/sdwa-peephole.ll | 2 +- test/CodeGen/AMDGPU/sdwa-preserve.mir | 44 +- test/CodeGen/AMDGPU/sdwa-scalar-ops.mir | 96 +- test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir | 42 +- test/CodeGen/AMDGPU/select-opt.ll | 4 +- test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir | 24 +- test/CodeGen/AMDGPU/setcc.ll | 6 +- test/CodeGen/AMDGPU/sext-in-reg.ll | 8 +- test/CodeGen/AMDGPU/sgpr-copy.ll | 72 +- test/CodeGen/AMDGPU/shl_add_ptr.ll | 24 +- test/CodeGen/AMDGPU/shrink-carry.mir | 24 +- test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir | 170 +- test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 14 +- .../si-instr-info-correct-implicit-operands.ll | 2 +- test/CodeGen/AMDGPU/si-lod-bias.ll | 14 +- test/CodeGen/AMDGPU/si-scheduler.ll | 10 +- test/CodeGen/AMDGPU/si-sgpr-spill.ll | 148 +- test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll | 32 +- test/CodeGen/AMDGPU/sibling-call.ll | 2 +- test/CodeGen/AMDGPU/skip-if-dead.ll | 6 +- test/CodeGen/AMDGPU/smrd-vccz-bug.ll | 6 +- test/CodeGen/AMDGPU/smrd.ll | 188 +- test/CodeGen/AMDGPU/spill-empty-live-interval.mir | 24 +- test/CodeGen/AMDGPU/spill-m0.ll | 4 +- test/CodeGen/AMDGPU/split-smrd.ll | 6 +- test/CodeGen/AMDGPU/splitkit.mir | 36 +- test/CodeGen/AMDGPU/stack-size-overflow.ll | 8 +- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 16 +- test/CodeGen/AMDGPU/store-global.ll | 8 +- test/CodeGen/AMDGPU/store-hi16.ll | 98 +- test/CodeGen/AMDGPU/store-private.ll | 120 +- test/CodeGen/AMDGPU/store-vector-ptrs.ll | 6 +- test/CodeGen/AMDGPU/sub.v2i16.ll | 10 +- test/CodeGen/AMDGPU/subreg-intervals.mir | 2 +- test/CodeGen/AMDGPU/subreg_interference.mir | 12 +- test/CodeGen/AMDGPU/syncscopes.ll | 18 +- test/CodeGen/AMDGPU/target-cpu.ll | 48 +- test/CodeGen/AMDGPU/twoaddr-mad.mir | 62 +- test/CodeGen/AMDGPU/unaligned-load-store.ll | 44 +- .../AMDGPU/undefined-physreg-sgpr-spill.mir | 104 +- test/CodeGen/AMDGPU/uniform-cfg.ll | 2 +- test/CodeGen/AMDGPU/uniform-crash.ll | 2 +- test/CodeGen/AMDGPU/unpack-half.ll | 26 + .../CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | 84 +- test/CodeGen/AMDGPU/vertex-fetch-encoding.ll | 6 +- .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 10 +- test/CodeGen/AMDGPU/vop-shrink-frame-index.mir | 60 +- test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir | 20 +- test/CodeGen/AMDGPU/wait.ll | 22 +- test/CodeGen/AMDGPU/waitcnt-flat.ll | 8 +- test/CodeGen/AMDGPU/waitcnt-looptest.ll | 22 +- test/CodeGen/AMDGPU/waitcnt-no-redundant.mir | 25 + test/CodeGen/AMDGPU/waitcnt-permute.mir | 14 +- test/CodeGen/AMDGPU/waitcnt.mir | 40 +- .../CodeGen/AMDGPU/widen_extending_scalar_loads.ll | 74 +- test/CodeGen/AMDGPU/wqm.ll | 10 +- test/CodeGen/AMDGPU/wqm.mir | 30 +- test/CodeGen/ARM/2009-03-07-SpillerBug.ll | 4 +- test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll | 4 +- test/CodeGen/ARM/2011-10-26-memset-inline.ll | 4 +- test/CodeGen/ARM/2011-10-26-memset-with-neon.ll | 4 +- test/CodeGen/ARM/2011-11-14-EarlyClobber.ll | 2 +- test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll | 2 +- test/CodeGen/ARM/2013-07-29-vector-or-combine.ll | 2 +- .../ARM/2014-01-09-pseudo_expand_implicit_reg.ll | 4 +- test/CodeGen/ARM/2018-02-13-PR36079.ll | 23 + test/CodeGen/ARM/ARMLoadStoreDBG.mir | 96 +- test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll | 22 +- .../ARM/GlobalISel/arm-instruction-select-cmp.mir | 1140 +- .../GlobalISel/arm-instruction-select-combos.mir | 685 +- .../ARM/GlobalISel/arm-instruction-select.mir | 1188 +- test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 230 +- .../CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 336 +- test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 1958 +- test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir | 121 + test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 409 +- test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll | 412 +- test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 692 +- .../arm-select-copy_to_regclass-of-fptosi.mir | 30 + .../ARM/GlobalISel/arm-select-globals-pic.mir | 44 +- .../GlobalISel/arm-select-globals-ropi-rwpi.mir | 56 +- .../ARM/GlobalISel/arm-select-globals-static.mir | 24 +- test/CodeGen/ARM/GlobalISel/arm-unsupported.ll | 2 +- test/CodeGen/ARM/GlobalISel/select-pr35926.mir | 40 + .../ARM/PR32721_ifcvt_triangle_unanalyzable.mir | 23 + test/CodeGen/ARM/PR35379.ll | 52 + test/CodeGen/ARM/Windows/alloca.ll | 2 + test/CodeGen/ARM/Windows/dbzchk.ll | 14 +- test/CodeGen/ARM/Windows/dllexport.ll | 57 +- test/CodeGen/ARM/Windows/memset.ll | 4 +- test/CodeGen/ARM/Windows/no-aeabi.ll | 8 +- test/CodeGen/ARM/Windows/vla-cpsr.ll | 2 +- test/CodeGen/ARM/Windows/vla.ll | 5 +- test/CodeGen/ARM/and-load-combine.ll | 705 +- test/CodeGen/ARM/arm-eabi.ll | 14 +- test/CodeGen/ARM/atomic-cmpxchg.ll | 30 +- test/CodeGen/ARM/atomic-op.ll | 11 +- test/CodeGen/ARM/cmn.ll | 8 +- test/CodeGen/ARM/cmp.ll | 89 +- test/CodeGen/ARM/cmp1-peephole-thumb.mir | 30 +- test/CodeGen/ARM/cmp2-peephole-thumb.mir | 36 +- test/CodeGen/ARM/cmpxchg-O0.ll | 20 +- test/CodeGen/ARM/coff-no-dead-strip.ll | 13 + test/CodeGen/ARM/constant-islands-cfg.mir | 18 +- test/CodeGen/ARM/constantpool-promote-ldrh.ll | 4 +- test/CodeGen/ARM/constantpool-promote.ll | 14 +- test/CodeGen/ARM/crash-O0.ll | 6 +- test/CodeGen/ARM/dbg-range-extension.mir | 170 +- test/CodeGen/ARM/debug-info-arg.ll | 2 +- test/CodeGen/ARM/debug-info-blocks.ll | 10 +- test/CodeGen/ARM/debug-info-branch-folding.ll | 4 +- test/CodeGen/ARM/debug-info-sreg2.ll | 2 +- test/CodeGen/ARM/deps-fix.ll | 2 +- test/CodeGen/ARM/dsp-mlal.ll | 171 + test/CodeGen/ARM/dwarf-eh.ll | 4 +- test/CodeGen/ARM/dyn-stackalloc.ll | 4 +- test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll | 4 +- test/CodeGen/ARM/ehabi-handlerdata.ll | 11 +- test/CodeGen/ARM/emutls.ll | 2 + test/CodeGen/ARM/emutls_generic.ll | 11 + test/CodeGen/ARM/expand-pseudos.mir | 48 +- test/CodeGen/ARM/fast-isel-intrinsic.ll | 20 +- test/CodeGen/ARM/fmacs.ll | 12 +- test/CodeGen/ARM/fp16-instructions.ll | 803 + test/CodeGen/ARM/fp16-litpool-arm.mir | 91 + test/CodeGen/ARM/fp16-litpool-thumb.mir | 83 + test/CodeGen/ARM/fp16-litpool2-arm.mir | 107 + test/CodeGen/ARM/fp16-litpool3-arm.mir | 113 + test/CodeGen/ARM/fp16-promote.ll | 6 +- test/CodeGen/ARM/fpoffset_overflow.mir | 122 +- test/CodeGen/ARM/fpvcvtr.ll | 35 + test/CodeGen/ARM/global-merge-dllexport.ll | 21 + test/CodeGen/ARM/global-merge-external.ll | 29 +- test/CodeGen/ARM/ifcvt-branch-weight-bug.ll | 4 +- test/CodeGen/ARM/ifcvt-branch-weight.ll | 4 +- test/CodeGen/ARM/ifcvt-iter-indbr.ll | 8 +- test/CodeGen/ARM/ifcvt_canFallThroughTo.mir | 65 + test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir | 30 + .../ARM/ifcvt_forked_diamond_unanalyzable.mir | 48 + .../ARM/ifcvt_simple_bad_zero_prob_succ.mir | 33 + test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir | 25 + test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir | 52 + test/CodeGen/ARM/imm-peephole-arm.mir | 20 +- test/CodeGen/ARM/imm-peephole-thumb.mir | 20 +- test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll | 9 + test/CodeGen/ARM/inlineasm.ll | 32 + test/CodeGen/ARM/interval-update-remat.ll | 4 +- test/CodeGen/ARM/intrinsics-overflow.ll | 17 +- test/CodeGen/ARM/ldm-stm-base-materialization.ll | 10 +- test/CodeGen/ARM/load_store_opt_kill.mir | 10 +- test/CodeGen/ARM/long-setcc.ll | 5 +- test/CodeGen/ARM/longMAC.ll | 32 +- test/CodeGen/ARM/machine-copyprop.mir | 24 +- test/CodeGen/ARM/machine-cse-cmp.ll | 4 +- test/CodeGen/ARM/memcpy-inline.ll | 20 +- test/CodeGen/ARM/memcpy-ldm-stm.ll | 20 +- test/CodeGen/ARM/memcpy-no-inline.ll | 6 +- test/CodeGen/ARM/memfunc.ll | 96 +- test/CodeGen/ARM/memset-inline.ll | 12 +- test/CodeGen/ARM/misched-int-basic-thumb2.mir | 70 +- test/CodeGen/ARM/misched-int-basic.mir | 50 +- .../ARM/overflow-intrinsic-optimizations.ll | 238 + test/CodeGen/ARM/peephole-phi.mir | 103 + test/CodeGen/ARM/pei-swiftself.mir | 64 +- test/CodeGen/ARM/pr25838.ll | 2 +- test/CodeGen/ARM/prera-ldst-aliasing.mir | 20 +- test/CodeGen/ARM/prera-ldst-insertpt.mir | 84 +- test/CodeGen/ARM/sat-to-bitop.ll | 157 + test/CodeGen/ARM/scavenging.mir | 80 +- test/CodeGen/ARM/sched-it-debug-nodes.mir | 91 +- test/CodeGen/ARM/select-imm.ll | 186 +- test/CodeGen/ARM/select_xform.ll | 10 +- test/CodeGen/ARM/setcc-logic.ll | 12 +- test/CodeGen/ARM/shift-i64.ll | 15 + test/CodeGen/ARM/single-issue-r52.mir | 24 +- test/CodeGen/ARM/smml.ll | 2 + test/CodeGen/ARM/splitkit.ll | 245 + test/CodeGen/ARM/stack-protector-bmovpcb_call.ll | 4 +- test/CodeGen/ARM/stack-size-section.ll | 30 + test/CodeGen/ARM/struct-byval-frame-index.ll | 8 +- test/CodeGen/ARM/struct_byval_arm_t1_t2.ll | 192 +- test/CodeGen/ARM/su-addsub-overflow.ll | 135 - test/CodeGen/ARM/subreg-remat.ll | 4 +- test/CodeGen/ARM/swifterror.ll | 23 +- test/CodeGen/ARM/tail-dup-bundle.mir | 34 +- test/CodeGen/ARM/tail-merge-branch-weight.ll | 6 +- test/CodeGen/ARM/tailcall-mem-intrinsics.ll | 12 +- test/CodeGen/ARM/taildup-branch-weight.ll | 4 +- test/CodeGen/ARM/thumb1-ldst-opt.ll | 2 +- test/CodeGen/ARM/trap-unreachable.ll | 8 + test/CodeGen/ARM/v6-jumptable-clobber.mir | 60 +- test/CodeGen/ARM/v8m-tail-call.ll | 25 + .../CodeGen/ARM/virtregrewriter-subregliveness.mir | 30 +- test/CodeGen/ARM/vld3.ll | 13 + test/CodeGen/ARM/vld4.ll | 13 + test/CodeGen/ARM/vldm-liveness.mir | 20 +- test/CodeGen/ARM/vst3.ll | 12 + test/CodeGen/ARM/vst4.ll | 12 + ...sue-regalloc-stackframe-folding-earlyclobber.ll | 139 + test/CodeGen/AVR/pseudo/ADCWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/ADDWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/ANDIWRdK.mir | 6 +- test/CodeGen/AVR/pseudo/ANDWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/ASRWRd.mir | 6 +- test/CodeGen/AVR/pseudo/COMWRd.mir | 6 +- test/CodeGen/AVR/pseudo/CPCWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/CPWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/EORWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/FRMIDX.mir | 2 +- test/CodeGen/AVR/pseudo/INWRdA.mir | 6 +- .../CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir | 2 +- test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir | 2 +- test/CodeGen/AVR/pseudo/LDDWRdYQ.mir | 2 +- test/CodeGen/AVR/pseudo/LDIWRdK.mir | 6 +- test/CodeGen/AVR/pseudo/LDSWRdK.mir | 6 +- test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir | 2 +- test/CodeGen/AVR/pseudo/LDWRdPtr.mir | 6 +- test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir | 6 +- test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir | 6 +- test/CodeGen/AVR/pseudo/LSLWRd.mir | 6 +- test/CodeGen/AVR/pseudo/LSRWRd.mir | 6 +- test/CodeGen/AVR/pseudo/ORIWRdK.mir | 6 +- test/CodeGen/AVR/pseudo/ORWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/OUTWARr.mir | 6 +- test/CodeGen/AVR/pseudo/POPWRd.mir | 6 +- test/CodeGen/AVR/pseudo/PUSHWRr.mir | 6 +- test/CodeGen/AVR/pseudo/SBCIWRdK.mir | 6 +- test/CodeGen/AVR/pseudo/SBCWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/SEXT.mir | 10 +- test/CodeGen/AVR/pseudo/STDWPtrQRr.mir | 6 +- test/CodeGen/AVR/pseudo/STSWKRr.mir | 6 +- test/CodeGen/AVR/pseudo/STWPtrPdRr.mir | 6 +- test/CodeGen/AVR/pseudo/STWPtrPiRr.mir | 6 +- test/CodeGen/AVR/pseudo/STWPtrRr.mir | 6 +- test/CodeGen/AVR/pseudo/SUBIWRdK.mir | 6 +- test/CodeGen/AVR/pseudo/SUBWRdRr.mir | 6 +- test/CodeGen/AVR/pseudo/ZEXT.mir | 10 +- test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir | 18 +- .../AVR/select-must-add-unconditional-jump.ll | 10 +- test/CodeGen/AVR/std-ldd-immediate-overflow.ll | 4 +- test/CodeGen/AVR/zext.ll | 2 +- test/CodeGen/BPF/32-bit-subreg-alu.ll | 298 + test/CodeGen/BPF/32-bit-subreg-cond-select.ll | 100 + test/CodeGen/BPF/32-bit-subreg-load-store.ll | 107 + test/CodeGen/BPF/32-bit-subreg-peephole.ll | 36 + test/CodeGen/BPF/alu8.ll | 8 +- test/CodeGen/BPF/basictest.ll | 2 +- test/CodeGen/BPF/byval.ll | 4 +- test/CodeGen/BPF/cmp.ll | 16 +- test/CodeGen/BPF/dwarfdump.ll | 6 +- test/CodeGen/BPF/ex1.ll | 6 +- test/CodeGen/BPF/fi_ri.ll | 4 +- test/CodeGen/BPF/intrinsics.ll | 12 +- test/CodeGen/BPF/objdump_intrinsics.ll | 12 +- test/CodeGen/BPF/reloc.ll | 6 +- test/CodeGen/BPF/remove_truncate_3.ll | 8 +- test/CodeGen/BPF/remove_truncate_4.ll | 58 + test/CodeGen/BPF/remove_truncate_5.ll | 53 + test/CodeGen/BPF/rodata_1.ll | 6 +- test/CodeGen/BPF/rodata_2.ll | 4 +- test/CodeGen/BPF/rodata_3.ll | 4 +- test/CodeGen/BPF/rodata_4.ll | 4 +- test/CodeGen/BPF/sanity.ll | 20 +- test/CodeGen/BPF/select_ri.ll | 25 + test/CodeGen/BPF/shifts.ll | 26 +- test/CodeGen/BPF/sockex2.ll | 2 +- test/CodeGen/BPF/undef.ll | 4 +- test/CodeGen/BPF/warn-call.ll | 4 +- test/CodeGen/Generic/ForceStackAlign.ll | 4 +- test/CodeGen/Generic/MachineBranchProb.ll | 20 +- test/CodeGen/Generic/dwarf-md5.ll | 59 + test/CodeGen/Generic/dwarf-source.ll | 61 + test/CodeGen/Generic/invalid-memcpy.ll | 4 +- test/CodeGen/Hexagon/absaddr-store.ll | 8 +- test/CodeGen/Hexagon/absimm.ll | 4 +- test/CodeGen/Hexagon/addr-calc-opt.ll | 2 +- test/CodeGen/Hexagon/addrmode-globoff.mir | 10 +- test/CodeGen/Hexagon/addrmode-keepdeadphis.mir | 18 +- test/CodeGen/Hexagon/addrmode-rr-to-io.mir | 12 +- test/CodeGen/Hexagon/adjust-latency-stackST.ll | 6 +- test/CodeGen/Hexagon/always-ext.ll | 2 +- test/CodeGen/Hexagon/anti-dep-partial.mir | 26 +- test/CodeGen/Hexagon/autohvx/align2-128b.ll | 1706 + test/CodeGen/Hexagon/autohvx/align2-64b.ll | 842 + test/CodeGen/Hexagon/autohvx/arith.ll | 6 +- test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll | 20 + test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll | 25 + test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll | 14 +- test/CodeGen/Hexagon/autohvx/isel-build-undef.ll | 39 + .../Hexagon/autohvx/isel-concat-multiple.ll | 35 + .../Hexagon/autohvx/isel-concat-vectors-bool.ll | 21 + .../Hexagon/autohvx/isel-const-splat-bitcast.ll | 37 + test/CodeGen/Hexagon/autohvx/isel-const-splat.ll | 12 + test/CodeGen/Hexagon/autohvx/isel-const-vector.ll | 12 + .../Hexagon/autohvx/isel-expand-unaligned-loads.ll | 26 + test/CodeGen/Hexagon/autohvx/isel-qfalse.ll | 29 + test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll | 29 + test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll | 54 + test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll | 30 + test/CodeGen/Hexagon/autohvx/isel-truncate.ll | 5 +- test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll | 8 +- test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll | 22 + test/CodeGen/Hexagon/autohvx/reg-sequence.ll | 4 +- test/CodeGen/Hexagon/autohvx/shift-128b.ll | 376 + test/CodeGen/Hexagon/autohvx/shift-64b.ll | 232 + .../CodeGen/Hexagon/autohvx/vector-compare-128b.ll | 45 +- test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll | 45 +- test/CodeGen/Hexagon/bank-conflict-load.mir | 16 +- test/CodeGen/Hexagon/bit-addr-align.mir | 18 + test/CodeGen/Hexagon/bit-loop.ll | 3 +- test/CodeGen/Hexagon/branch-folder-hoist-kills.mir | 46 +- .../CodeGen/Hexagon/branchfolder-insert-impdef.mir | 66 +- test/CodeGen/Hexagon/branchfolder-keep-impdef.ll | 4 +- test/CodeGen/Hexagon/builtin-prefetch-offset.ll | 4 +- test/CodeGen/Hexagon/cext-check.ll | 16 +- test/CodeGen/Hexagon/cext-opt-basic.mir | 20 +- test/CodeGen/Hexagon/cext-opt-numops.mir | 8 +- test/CodeGen/Hexagon/cext-opt-range-assert.mir | 54 + test/CodeGen/Hexagon/cext-opt-range-offset.mir | 4 +- test/CodeGen/Hexagon/cext-opt-shifted-range.mir | 34 + test/CodeGen/Hexagon/cext-valid-packet2.ll | 4 +- test/CodeGen/Hexagon/cext.ll | 2 +- test/CodeGen/Hexagon/cexti16.ll | 2 +- test/CodeGen/Hexagon/cmp-to-genreg.ll | 8 +- test/CodeGen/Hexagon/cmp-to-predreg.ll | 8 +- test/CodeGen/Hexagon/common-gep-inbounds.ll | 4 +- test/CodeGen/Hexagon/constp-andir-global.mir | 25 + test/CodeGen/Hexagon/duplex-addi-global-imm.mir | 6 +- test/CodeGen/Hexagon/early-if-conversion-bug1.ll | 12 +- test/CodeGen/Hexagon/early-if-debug.mir | 30 +- test/CodeGen/Hexagon/early-if-low8.mir | 27 + test/CodeGen/Hexagon/expand-condsets-def-undef.mir | 14 +- test/CodeGen/Hexagon/expand-condsets-imm.mir | 2 +- test/CodeGen/Hexagon/expand-condsets-impuse.mir | 18 +- test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 20 +- .../Hexagon/expand-condsets-same-inputs.mir | 10 +- test/CodeGen/Hexagon/expand-vselect-kill.ll | 8 +- test/CodeGen/Hexagon/gp-plus-offset-load.ll | 6 +- test/CodeGen/Hexagon/gp-plus-offset-store.ll | 4 +- test/CodeGen/Hexagon/gp-rel.ll | 6 +- test/CodeGen/Hexagon/hwloop-redef-imm.mir | 8 +- test/CodeGen/Hexagon/idxload-with-zero-offset.ll | 12 +- test/CodeGen/Hexagon/ifcvt-common-kill.mir | 24 +- test/CodeGen/Hexagon/ifcvt-edge-weight.ll | 4 +- test/CodeGen/Hexagon/ifcvt-impuse-livein.mir | 24 +- test/CodeGen/Hexagon/ifcvt-live-subreg.mir | 34 +- test/CodeGen/Hexagon/invalid-dotnew-attempt.mir | 6 +- .../Hexagon/isel-global-offset-alignment.ll | 33 + test/CodeGen/Hexagon/isel-setcc-i1.ll | 27 + test/CodeGen/Hexagon/isel-simplify-crash.ll | 9 +- test/CodeGen/Hexagon/isel-vacopy.ll | 18 + .../CodeGen/Hexagon/livephysregs-add-pristines.mir | 22 +- test/CodeGen/Hexagon/livephysregs-lane-masks.mir | 28 +- test/CodeGen/Hexagon/livephysregs-lane-masks2.mir | 44 +- test/CodeGen/Hexagon/mem-fi-add.ll | 4 +- test/CodeGen/Hexagon/memcpy-likely-aligned.ll | 4 +- test/CodeGen/Hexagon/memops.ll | 252 +- test/CodeGen/Hexagon/memops1.ll | 4 +- test/CodeGen/Hexagon/memops2.ll | 4 +- test/CodeGen/Hexagon/memops3.ll | 4 +- test/CodeGen/Hexagon/mul64-sext.ll | 32 +- test/CodeGen/Hexagon/multi-cycle.ll | 6 +- test/CodeGen/Hexagon/mux-kill1.mir | 10 +- test/CodeGen/Hexagon/mux-kill2.mir | 14 +- test/CodeGen/Hexagon/mux-kill3.mir | 40 +- test/CodeGen/Hexagon/newvaluejump-c4.mir | 30 +- test/CodeGen/Hexagon/newvaluejump-float.mir | 19 + test/CodeGen/Hexagon/newvaluejump-kill.ll | 7 +- test/CodeGen/Hexagon/newvaluejump-kill2.mir | 16 +- test/CodeGen/Hexagon/newvaluejump-solo.mir | 8 +- .../Hexagon/packetize-load-store-aliasing.mir | 16 +- test/CodeGen/Hexagon/packetize-nvj-no-prune.mir | 12 +- test/CodeGen/Hexagon/pic-jumptables.ll | 6 +- test/CodeGen/Hexagon/pic-regusage.ll | 6 +- test/CodeGen/Hexagon/post-inc-aa-metadata.ll | 2 +- test/CodeGen/Hexagon/post-ra-kill-update.mir | 20 +- test/CodeGen/Hexagon/postinc-baseoffset.mir | 6 +- test/CodeGen/Hexagon/postinc-load.ll | 2 +- test/CodeGen/Hexagon/postinc-offset.ll | 4 +- test/CodeGen/Hexagon/postinc-store.ll | 2 +- test/CodeGen/Hexagon/pred-absolute-store.ll | 2 +- test/CodeGen/Hexagon/pred-gp.ll | 4 +- test/CodeGen/Hexagon/pred-instrs.ll | 4 +- .../Hexagon/rdf-copy-renamable-reserved.mir | 19 + test/CodeGen/Hexagon/rdf-ehlabel-live.mir | 2 +- test/CodeGen/Hexagon/rdf-filter-defs.ll | 10 +- test/CodeGen/Hexagon/regalloc-bad-undef.mir | 46 +- test/CodeGen/Hexagon/regalloc-block-overlap.ll | 11 +- test/CodeGen/Hexagon/regalloc-liveout-undef.mir | 6 +- test/CodeGen/Hexagon/select-instr-align.ll | 26 +- test/CodeGen/Hexagon/store-imm-stack-object.ll | 6 +- test/CodeGen/Hexagon/swp-epilog-reuse-1.ll | 2 +- test/CodeGen/Hexagon/swp-stages4.ll | 10 +- test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll | 12 +- test/CodeGen/Hexagon/tail-dup-subreg-map.ll | 8 +- test/CodeGen/Hexagon/target-flag-ext.mir | 12 +- test/CodeGen/Hexagon/trap-unreachable.ll | 2 +- .../CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir | 10 +- test/CodeGen/Hexagon/vararg-formal.ll | 12 + test/CodeGen/Hexagon/vec-pred-spill1.ll | 2 +- test/CodeGen/Hexagon/vec-vararg-align.ll | 2 +- test/CodeGen/Hexagon/vect/build-vect64.ll | 8 + test/CodeGen/Hexagon/vect/setcc-v2i32.ll | 21 + test/CodeGen/Hexagon/vect/shuff-32.ll | 86 + test/CodeGen/Hexagon/vect/shuff-64.ll | 66 + .../Hexagon/vect/vect-bool-basic-compile.ll | 65 + test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll | 31 + test/CodeGen/Hexagon/vect/vect-truncate.ll | 4 +- test/CodeGen/Hexagon/vect/zext-v4i1.ll | 40 + test/CodeGen/Hexagon/vextract-basic.mir | 26 + test/CodeGen/Lanai/peephole-compare.mir | 300 +- test/CodeGen/MIR/AArch64/addrspace-memoperands.mir | 31 + test/CodeGen/MIR/AArch64/atomic-memoperands.mir | 4 +- test/CodeGen/MIR/AArch64/cfi.mir | 32 +- .../MIR/AArch64/expected-target-flag-name.mir | 6 +- .../AArch64/generic-virtual-registers-error.mir | 4 +- ...eneric-virtual-registers-with-regbank-error.mir | 4 +- test/CodeGen/MIR/AArch64/intrinsics.mir | 4 +- .../MIR/AArch64/invalid-target-flag-name.mir | 6 +- .../MIR/AArch64/invalid-target-memoperands.mir | 2 +- test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir | 12 +- .../AArch64/print-parse-overloaded-intrinsics.mir | 24 + .../print-parse-verify-failedISel-property.mir | 65 + test/CodeGen/MIR/AArch64/register-operand-bank.mir | 8 +- test/CodeGen/MIR/AArch64/spill-fold.mir | 82 - test/CodeGen/MIR/AArch64/swp.mir | 10 +- test/CodeGen/MIR/AArch64/target-flags.mir | 28 +- test/CodeGen/MIR/AArch64/target-memoperands.mir | 4 +- .../MIR/AMDGPU/expected-target-index-name.mir | 38 +- test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir | 709 - test/CodeGen/MIR/AMDGPU/fold-multiple.mir | 40 - test/CodeGen/MIR/AMDGPU/intrinsics.mir | 4 +- .../MIR/AMDGPU/invalid-target-index-operand.mir | 38 +- .../AMDGPU/memory-legalizer-atomic-insert-end.mir | 122 - ...ory-legalizer-multiple-mem-operands-atomics.mir | 163 - ...galizer-multiple-mem-operands-nontemporal-1.mir | 161 - ...galizer-multiple-mem-operands-nontemporal-2.mir | 161 - test/CodeGen/MIR/AMDGPU/syncscopes.mir | 46 +- test/CodeGen/MIR/AMDGPU/target-flags.mir | 8 +- test/CodeGen/MIR/AMDGPU/target-index-operands.mir | 80 +- .../ARM/PR32721_ifcvt_triangle_unanalyzable.mir | 23 - test/CodeGen/MIR/ARM/bundled-instructions.mir | 62 +- test/CodeGen/MIR/ARM/cfi-same-value.mir | 68 +- test/CodeGen/MIR/ARM/expected-closing-brace.mir | 26 +- .../MIR/ARM/extraneous-closing-brace-error.mir | 6 +- test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir | 65 - .../CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir | 30 - .../MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir | 48 - .../MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir | 33 - test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir | 25 - .../MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir | 52 - .../MIR/ARM/nested-instruction-bundle-error.mir | 18 +- test/CodeGen/MIR/Hexagon/parse-lane-masks.mir | 4 +- test/CodeGen/MIR/Hexagon/target-flags.mir | 26 +- ...ted-global-value-or-symbol-after-call-entry.mir | 28 +- test/CodeGen/MIR/Mips/memory-operands.mir | 76 +- .../MIR/NVPTX/expected-floating-point-literal.mir | 2 +- .../NVPTX/floating-point-immediate-operands.mir | 8 +- .../NVPTX/floating-point-invalid-type-error.mir | 2 +- .../MIR/PowerPC/unordered-implicit-registers.mir | 12 +- test/CodeGen/MIR/X86/auto-successor.mir | 24 +- test/CodeGen/MIR/X86/basic-block-liveins.mir | 24 +- .../X86/basic-block-not-at-start-of-line-error.mir | 18 +- test/CodeGen/MIR/X86/block-address-operands.mir | 40 +- test/CodeGen/MIR/X86/branch-probabilities.mir | 4 +- test/CodeGen/MIR/X86/callee-saved-info.mir | 48 +- test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir | 4 +- test/CodeGen/MIR/X86/cfi-def-cfa-register.mir | 12 +- test/CodeGen/MIR/X86/cfi-offset.mir | 26 +- test/CodeGen/MIR/X86/constant-pool.mir | 52 +- test/CodeGen/MIR/X86/dead-register-flag.mir | 6 +- .../MIR/X86/def-register-already-tied-error.mir | 10 +- test/CodeGen/MIR/X86/diexpr-win32.mir | 44 +- .../MIR/X86/duplicate-memory-operand-flag.mir | 12 +- .../MIR/X86/duplicate-register-flag-error.mir | 12 +- test/CodeGen/MIR/X86/dynamic-regmask.ll | 30 - .../MIR/X86/early-clobber-register-flag.mir | 22 +- test/CodeGen/MIR/X86/empty0.mir | 2 +- test/CodeGen/MIR/X86/empty1.mir | 2 +- test/CodeGen/MIR/X86/empty2.mir | 2 +- .../MIR/X86/expected-align-in-memory-operand.mir | 16 +- ...ted-alignment-after-align-in-memory-operand.mir | 16 +- .../X86/expected-basic-block-at-start-of-body.mir | 18 +- .../expected-block-reference-in-blockaddress.mir | 6 +- .../MIR/X86/expected-comma-after-cfi-register.mir | 22 +- .../X86/expected-comma-after-memory-operand.mir | 6 +- .../X86/expected-different-implicit-operand.mir | 10 +- .../expected-different-implicit-register-flag.mir | 10 +- ...ected-function-reference-after-blockaddress.mir | 6 +- .../expected-global-value-after-blockaddress.mir | 6 +- .../MIR/X86/expected-integer-after-offset-sign.mir | 8 +- .../MIR/X86/expected-integer-after-tied-def.mir | 10 +- .../X86/expected-integer-in-successor-weight.mir | 16 +- .../expected-load-or-store-in-memory-operand.mir | 8 +- test/CodeGen/MIR/X86/expected-machine-operand.mir | 4 +- ...expected-metadata-node-after-debug-location.mir | 8 +- .../X86/expected-metadata-node-after-exclaim.mir | 6 +- .../X86/expected-metadata-node-in-stack-object.mir | 10 +- .../expected-named-register-in-allocation-hint.mir | 16 +- ...ted-named-register-in-callee-saved-register.mir | 40 +- .../MIR/X86/expected-named-register-livein.mir | 4 +- .../MIR/X86/expected-newline-at-end-of-list.mir | 18 +- test/CodeGen/MIR/X86/expected-number-after-bb.mir | 10 +- .../MIR/X86/expected-offset-after-cfi-operand.mir | 4 +- .../expected-pointer-value-in-memory-operand.mir | 8 +- .../expected-positive-alignment-after-align.mir | 16 +- .../X86/expected-register-after-cfi-operand.mir | 20 +- .../MIR/X86/expected-register-after-flags.mir | 4 +- ...xpected-size-integer-after-memory-operation.mir | 8 +- test/CodeGen/MIR/X86/expected-stack-object.mir | 30 +- .../MIR/X86/expected-subregister-after-colon.mir | 8 +- test/CodeGen/MIR/X86/expected-target-flag-name.mir | 8 +- .../MIR/X86/expected-tied-def-after-lparen.mir | 10 +- .../MIR/X86/expected-value-in-memory-operand.mir | 8 +- ...pected-virtual-register-in-functions-livein.mir | 10 +- test/CodeGen/MIR/X86/external-symbol-operands.mir | 46 +- .../MIR/X86/fixed-stack-memory-operands.mir | 12 +- .../X86/fixed-stack-object-redefinition-error.mir | 6 +- test/CodeGen/MIR/X86/fixed-stack-objects.mir | 6 +- .../MIR/X86/frame-info-save-restore-points.mir | 32 +- .../MIR/X86/frame-info-stack-references.mir | 36 +- .../MIR/X86/frame-setup-instruction-flag.mir | 15 +- test/CodeGen/MIR/X86/function-liveins.mir | 20 +- test/CodeGen/MIR/X86/generic-instr-type.mir | 12 +- test/CodeGen/MIR/X86/global-value-operands.mir | 72 +- test/CodeGen/MIR/X86/immediate-operands.mir | 16 +- test/CodeGen/MIR/X86/implicit-register-flag.mir | 30 +- test/CodeGen/MIR/X86/inline-asm-registers.mir | 28 +- test/CodeGen/MIR/X86/inline-asm.mir | 4 +- .../MIR/X86/instructions-debug-location.mir | 28 +- .../CodeGen/MIR/X86/invalid-constant-pool-item.mir | 4 +- test/CodeGen/MIR/X86/invalid-target-flag-name.mir | 8 +- .../MIR/X86/invalid-tied-def-index-error.mir | 10 +- test/CodeGen/MIR/X86/jump-table-info.mir | 72 +- .../MIR/X86/jump-table-redefinition-error.mir | 34 +- test/CodeGen/MIR/X86/killed-register-flag.mir | 20 +- .../MIR/X86/large-cfi-offset-number-error.mir | 4 +- .../MIR/X86/large-immediate-operand-error.mir | 4 +- test/CodeGen/MIR/X86/large-index-number-error.mir | 10 +- test/CodeGen/MIR/X86/large-offset-number-error.mir | 8 +- .../MIR/X86/large-size-in-memory-operand-error.mir | 8 +- test/CodeGen/MIR/X86/liveout-register-mask.mir | 20 +- .../MIR/X86/machine-basic-block-operands.mir | 24 +- test/CodeGen/MIR/X86/machine-instructions.mir | 4 +- test/CodeGen/MIR/X86/machine-verifier.mir | 2 +- test/CodeGen/MIR/X86/memory-operands.mir | 282 +- test/CodeGen/MIR/X86/metadata-operands.mir | 12 +- test/CodeGen/MIR/X86/missing-closing-quote.mir | 6 +- test/CodeGen/MIR/X86/missing-comma.mir | 4 +- test/CodeGen/MIR/X86/missing-implicit-operand.mir | 8 +- test/CodeGen/MIR/X86/named-registers.mir | 8 +- test/CodeGen/MIR/X86/newline-handling.mir | 70 +- test/CodeGen/MIR/X86/null-register-operands.mir | 8 +- test/CodeGen/MIR/X86/register-mask-operands.mir | 16 +- .../MIR/X86/register-operand-class-invalid0.mir | 2 +- .../MIR/X86/register-operand-class-invalid1.mir | 2 +- test/CodeGen/MIR/X86/register-operand-class.mir | 16 +- .../X86/register-operands-target-flag-error.mir | 8 +- test/CodeGen/MIR/X86/renamable-register-flag.mir | 6 +- test/CodeGen/MIR/X86/roundtrip.mir | 12 +- test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir | 182 - .../MIR/X86/simple-register-allocation-hints.mir | 20 +- .../X86/simple-register-allocation-read-undef.mir | 30 - .../MIR/X86/spill-slot-fixed-stack-objects.mir | 6 +- test/CodeGen/MIR/X86/stack-object-invalid-name.mir | 6 +- .../stack-object-operand-name-mismatch-error.mir | 6 +- test/CodeGen/MIR/X86/stack-object-operands.mir | 16 +- .../MIR/X86/stack-object-redefinition-error.mir | 12 +- test/CodeGen/MIR/X86/stack-objects.mir | 8 +- test/CodeGen/MIR/X86/standalone-register-error.mir | 10 +- test/CodeGen/MIR/X86/subreg-on-physreg.mir | 2 +- .../CodeGen/MIR/X86/subregister-index-operands.mir | 20 +- test/CodeGen/MIR/X86/subregister-operands.mir | 20 +- .../MIR/X86/successor-basic-blocks-weights.mir | 16 +- test/CodeGen/MIR/X86/successor-basic-blocks.mir | 34 +- test/CodeGen/MIR/X86/tied-def-operand-invalid.mir | 10 +- test/CodeGen/MIR/X86/tied-physical-regs-match.mir | 6 +- test/CodeGen/MIR/X86/undef-register-flag.mir | 14 +- .../MIR/X86/undefined-fixed-stack-object.mir | 4 +- test/CodeGen/MIR/X86/undefined-global-value.mir | 8 +- .../MIR/X86/undefined-ir-block-in-blockaddress.mir | 6 +- .../undefined-ir-block-slot-in-blockaddress.mir | 6 +- test/CodeGen/MIR/X86/undefined-jump-table-id.mir | 34 +- .../MIR/X86/undefined-named-global-value.mir | 8 +- test/CodeGen/MIR/X86/undefined-stack-object.mir | 6 +- .../MIR/X86/undefined-value-in-memory-operand.mir | 8 +- .../CodeGen/MIR/X86/undefined-virtual-register.mir | 6 +- test/CodeGen/MIR/X86/unexpected-type-phys.mir | 4 +- .../MIR/X86/unknown-machine-basic-block.mir | 10 +- test/CodeGen/MIR/X86/unknown-metadata-keyword.mir | 12 +- test/CodeGen/MIR/X86/unknown-metadata-node.mir | 6 +- .../MIR/X86/unknown-named-machine-basic-block.mir | 10 +- test/CodeGen/MIR/X86/unknown-register.mir | 4 +- .../MIR/X86/unknown-subregister-index-op.mir | 2 +- test/CodeGen/MIR/X86/unknown-subregister-index.mir | 8 +- test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir | 38 - .../MIR/X86/variable-sized-stack-objects.mir | 8 +- test/CodeGen/MIR/X86/virtual-registers.mir | 46 +- test/CodeGen/MSP430/memset.ll | 4 +- test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll | 4 +- test/CodeGen/Mips/Fast-ISel/memtest1.ll | 15 +- test/CodeGen/Mips/Fast-ISel/sel1.ll | 147 +- test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll | 11 + test/CodeGen/Mips/GlobalISel/llvm-ir/ret.ll | 12 + test/CodeGen/Mips/analyzebranch.ll | 305 +- test/CodeGen/Mips/biggot.ll | 4 +- ...rguments-small-structures-bigger-than-32bits.ll | 6 +- .../cconv/arguments-varargs-small-structs-byte.ll | 12 +- ...arguments-varargs-small-structs-combinations.ll | 6 +- test/CodeGen/Mips/cconv/callee-saved-float.ll | 2 +- test/CodeGen/Mips/cconv/return-struct.ll | 6 +- test/CodeGen/Mips/cconv/vector.ll | 8058 ++++- .../compact-branch-implicit-def.mir | 98 +- test/CodeGen/Mips/compactbranches/empty-block.mir | 24 +- test/CodeGen/Mips/dsp_msa_warning.ll | 44 + test/CodeGen/Mips/emutls_generic.ll | 5 + test/CodeGen/Mips/fastcc_byval.ll | 27 + test/CodeGen/Mips/gprestore.ll | 221 +- test/CodeGen/Mips/indirect-jump-hazard/calls.ll | 172 + .../indirect-jump-hazard/guards-verify-call.mir | 58 + .../guards-verify-tailcall.mir | 59 + .../Mips/indirect-jump-hazard/jumptables.ll | 649 + .../Mips/indirect-jump-hazard/long-branch.ll | 138 + .../Mips/indirect-jump-hazard/long-calls.ll | 104 + .../indirect-jump-hazard/unsupported-micromips.ll | 5 + .../indirect-jump-hazard/unsupported-mips32.ll | 5 + test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll | 13 + test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 10 + test/CodeGen/Mips/inlineasm-opcode-bad-y.ll | 11 + test/CodeGen/Mips/inlineasm-operand-code.ll | 11 + test/CodeGen/Mips/inlineasmmemop.ll | 22 +- test/CodeGen/Mips/instverify/dext-pos.mir | 10 +- test/CodeGen/Mips/instverify/dext-size.mir | 10 +- test/CodeGen/Mips/instverify/dextm-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dextm-pos.mir | 10 +- test/CodeGen/Mips/instverify/dextm-size.mir | 10 +- test/CodeGen/Mips/instverify/dextu-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dextu-pos.mir | 10 +- test/CodeGen/Mips/instverify/dextu-size-valid.mir | 10 +- test/CodeGen/Mips/instverify/dextu-size.mir | 10 +- test/CodeGen/Mips/instverify/dins-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dins-pos.mir | 10 +- test/CodeGen/Mips/instverify/dins-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsm-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsm-pos.mir | 10 +- test/CodeGen/Mips/instverify/dinsm-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsu-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsu-pos.mir | 10 +- test/CodeGen/Mips/instverify/dinsu-size.mir | 10 +- test/CodeGen/Mips/instverify/ext-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/ext-pos.mir | 10 +- test/CodeGen/Mips/instverify/ext-size.mir | 10 +- test/CodeGen/Mips/instverify/ins-pos-size.mir | 14 +- test/CodeGen/Mips/instverify/ins-pos.mir | 14 +- test/CodeGen/Mips/instverify/ins-size.mir | 14 +- test/CodeGen/Mips/largeimmprinting.ll | 4 +- test/CodeGen/Mips/llvm-ir/abs.ll | 28 + test/CodeGen/Mips/llvm-ir/and.ll | 36 +- test/CodeGen/Mips/llvm-ir/arith-fp.ll | 55 + test/CodeGen/Mips/llvm-ir/ashr.ll | 153 +- test/CodeGen/Mips/llvm-ir/bitcast.ll | 30 + test/CodeGen/Mips/llvm-ir/call.ll | 4 +- test/CodeGen/Mips/llvm-ir/cvt.ll | 37 + test/CodeGen/Mips/llvm-ir/lshr.ll | 180 +- test/CodeGen/Mips/llvm-ir/or.ll | 36 +- test/CodeGen/Mips/llvm-ir/select-dbl.ll | 936 +- test/CodeGen/Mips/llvm-ir/select-flt.ll | 872 +- test/CodeGen/Mips/llvm-ir/shl.ll | 156 +- test/CodeGen/Mips/llvm-ir/sqrt.ll | 29 + test/CodeGen/Mips/llvm-ir/sub.ll | 2 +- test/CodeGen/Mips/llvm-ir/xor.ll | 32 +- test/CodeGen/Mips/long-calls.ll | 4 +- test/CodeGen/Mips/memcpy.ll | 4 +- test/CodeGen/Mips/micromips-eva.mir | 213 + .../Mips/mirparser/target-flags-pic-mxgot-tls.mir | 138 +- .../Mips/mirparser/target-flags-pic-o32.mir | 28 +- test/CodeGen/Mips/mirparser/target-flags-pic.mir | 26 +- .../Mips/mirparser/target-flags-static-tls.mir | 78 +- test/CodeGen/Mips/msa/compare.ll | 16 +- test/CodeGen/Mips/msa/emergency-spill.mir | 180 +- test/CodeGen/Mips/o32_cc_byval.ll | 229 +- test/CodeGen/Mips/pr33978.ll | 6 +- test/CodeGen/Mips/pr34975.ll | 2 +- test/CodeGen/Mips/pr35071.ll | 2 +- test/CodeGen/Mips/pr36061.ll | 65 + test/CodeGen/Mips/select.ll | 1765 +- test/CodeGen/Mips/sll-micromips-r6-encoding.mir | 6 +- test/CodeGen/Mips/tailcall/tailcall.ll | 24 +- test/CodeGen/Mips/unsized-global.ll | 22 + test/CodeGen/NVPTX/access-non-generic.ll | 7 - test/CodeGen/NVPTX/generic-to-nvvm-ir.ll | 6 +- test/CodeGen/NVPTX/generic-to-nvvm.ll | 11 +- test/CodeGen/NVPTX/lower-aggr-copies.ll | 20 +- test/CodeGen/NVPTX/param-load-store.ll | 9 +- .../CodeGen/NVPTX/read-global-variable-constant.ll | 29 + test/CodeGen/Nios2/add-sub.ll | 19 + test/CodeGen/Nios2/mul-div.ll | 27 + test/CodeGen/Nios2/shift-rotate.ll | 26 + test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll | 2 +- .../PowerPC/2011-12-06-SpillAndRestoreCR.ll | 2 +- test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll | 2 +- test/CodeGen/PowerPC/MMO-flags-assertion.ll | 4 +- test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll | 94 + test/CodeGen/PowerPC/aantidep-def-ec.mir | 54 +- test/CodeGen/PowerPC/aantidep-inline-asm-use.ll | 4 +- test/CodeGen/PowerPC/addegluecrash.ll | 2 +- test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 52 +- .../PowerPC/aggressive-anti-dep-breaker-subreg.ll | 2 +- test/CodeGen/PowerPC/atomics-regression.ll | 40 + test/CodeGen/PowerPC/byval-agg-info.ll | 2 +- test/CodeGen/PowerPC/coldcc.ll | 46 + test/CodeGen/PowerPC/coldcc2.ll | 42 + ...convert-rr-to-ri-instrs-R0-special-handling.mir | 110 +- .../convert-rr-to-ri-instrs-out-of-range.mir | 340 +- test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 1445 +- test/CodeGen/PowerPC/ctrloop-reg.ll | 2 +- test/CodeGen/PowerPC/ctrloops-hot-exit.ll | 187 + test/CodeGen/PowerPC/debuginfo-split-int.ll | 8 +- test/CodeGen/PowerPC/debuginfo-stackarg.ll | 2 +- test/CodeGen/PowerPC/emptystruct.ll | 4 +- test/CodeGen/PowerPC/emutls_generic.ll | 7 + test/CodeGen/PowerPC/expand-isel-1.mir | 18 +- test/CodeGen/PowerPC/expand-isel-10.mir | 20 +- test/CodeGen/PowerPC/expand-isel-2.mir | 22 +- test/CodeGen/PowerPC/expand-isel-3.mir | 22 +- test/CodeGen/PowerPC/expand-isel-4.mir | 24 +- test/CodeGen/PowerPC/expand-isel-5.mir | 18 +- test/CodeGen/PowerPC/expand-isel-6.mir | 18 +- test/CodeGen/PowerPC/expand-isel-7.mir | 22 +- test/CodeGen/PowerPC/expand-isel-8.mir | 36 +- test/CodeGen/PowerPC/expand-isel-9.mir | 16 +- test/CodeGen/PowerPC/fastcc_stacksize.ll | 141 + test/CodeGen/PowerPC/fma-mutate.ll | 3 +- test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 25 + test/CodeGen/PowerPC/fp64-to-int16.ll | 2 +- test/CodeGen/PowerPC/fsl-e500mc.ll | 4 +- test/CodeGen/PowerPC/fsl-e5500.ll | 4 +- test/CodeGen/PowerPC/glob-comp-aa-crash.ll | 4 +- test/CodeGen/PowerPC/gpr-vsr-spill.ll | 2 +- test/CodeGen/PowerPC/isel-rc-nox0.ll | 4 +- test/CodeGen/PowerPC/licm-remat.ll | 12 +- test/CodeGen/PowerPC/licm-tocReg.ll | 16 +- test/CodeGen/PowerPC/livephysregs.mir | 54 +- test/CodeGen/PowerPC/load-two-flts.ll | 4 +- test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll | 6 +- test/CodeGen/PowerPC/mature-mc-support.ll | 19 +- test/CodeGen/PowerPC/memcmp-mergeexpand.ll | 50 + test/CodeGen/PowerPC/memcpy-vec.ll | 12 +- test/CodeGen/PowerPC/memcpy_dereferenceable.ll | 12 +- test/CodeGen/PowerPC/memset-nc-le.ll | 4 +- test/CodeGen/PowerPC/memset-nc.ll | 6 +- test/CodeGen/PowerPC/merge-st-chain-op.ll | 4 +- test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 8 +- test/CodeGen/PowerPC/noPermuteFormasking.ll | 42 + test/CodeGen/PowerPC/non-simple-args-intrin.ll | 60 + test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 14 +- test/CodeGen/PowerPC/opt-li-add-to-addi.ll | 2 +- test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 26 +- test/CodeGen/PowerPC/ppc-empty-fs.ll | 4 +- test/CodeGen/PowerPC/ppc64-align-long-double.ll | 2 +- test/CodeGen/PowerPC/ppc64-byval-align.ll | 3 +- test/CodeGen/PowerPC/pr27350.ll | 4 +- test/CodeGen/PowerPC/pr33547.ll | 70 + test/CodeGen/PowerPC/pr36068.ll | 18 + test/CodeGen/PowerPC/pr36292.ll | 46 + test/CodeGen/PowerPC/quadint-return.ll | 4 +- test/CodeGen/PowerPC/resolvefi-basereg.ll | 28 +- test/CodeGen/PowerPC/resolvefi-disp.ll | 16 +- test/CodeGen/PowerPC/rlwinm-zero-ext.ll | 2 +- test/CodeGen/PowerPC/scavenging.mir | 264 +- test/CodeGen/PowerPC/select-i1-vs-i1.ll | 60 +- test/CodeGen/PowerPC/structsinmem.ll | 30 +- test/CodeGen/PowerPC/structsinregs.ll | 30 +- test/CodeGen/PowerPC/stwu8.ll | 4 +- test/CodeGen/PowerPC/tail-dup-layout.ll | 2 +- test/CodeGen/PowerPC/tailcall-string-rvo.ll | 4 +- test/CodeGen/PowerPC/tls_get_addr_fence1.mir | 18 +- test/CodeGen/PowerPC/tls_get_addr_fence2.mir | 16 +- test/CodeGen/PowerPC/toc-load-sched-bug.ll | 14 +- test/CodeGen/PowerPC/vec_extract_p9_2.ll | 8 +- test/CodeGen/RISCV/addc-adde-sube-subc.ll | 14 - test/CodeGen/RISCV/alu32.ll | 133 - test/CodeGen/RISCV/analyze-branch.ll | 85 + test/CodeGen/RISCV/bare-select.ll | 7 - test/CodeGen/RISCV/blockaddress.ll | 3 - test/CodeGen/RISCV/branch-relaxation.ll | 65 + test/CodeGen/RISCV/branch.ll | 40 +- test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 327 +- test/CodeGen/RISCV/byval.ll | 20 +- test/CodeGen/RISCV/calling-conv-sext-zext.ll | 117 - test/CodeGen/RISCV/calling-conv.ll | 1409 +- test/CodeGen/RISCV/calls.ll | 69 +- test/CodeGen/RISCV/div.ll | 151 +- test/CodeGen/RISCV/fp128.ll | 66 +- test/CodeGen/RISCV/frame.ll | 66 +- test/CodeGen/RISCV/frameaddr-returnaddr.ll | 92 + test/CodeGen/RISCV/get-setcc-result-type.ll | 35 + test/CodeGen/RISCV/i32-icmp.ll | 70 - test/CodeGen/RISCV/imm.ll | 35 - test/CodeGen/RISCV/indirectbr.ll | 6 - test/CodeGen/RISCV/inline-asm.ll | 55 + test/CodeGen/RISCV/jumptable.ll | 46 +- test/CodeGen/RISCV/large-stack.ll | 172 + test/CodeGen/RISCV/mem.ll | 84 - test/CodeGen/RISCV/mul.ll | 134 +- test/CodeGen/RISCV/rem.ll | 20 +- test/CodeGen/RISCV/rotl-rotr.ll | 14 - test/CodeGen/RISCV/select-cc.ll | 9 +- test/CodeGen/RISCV/sext-zext-trunc.ll | 210 - test/CodeGen/RISCV/shifts.ll | 9 - test/CodeGen/RISCV/vararg.ll | 1171 + test/CodeGen/RISCV/wide-mem.ll | 14 - test/CodeGen/SPARC/32abi.ll | 28 +- test/CodeGen/SPARC/64abi.ll | 19 +- test/CodeGen/SPARC/64cond.ll | 13 +- test/CodeGen/SPARC/atomics.ll | 5 +- test/CodeGen/SPARC/stack-align.ll | 16 +- test/CodeGen/SPARC/tls.ll | 19 +- test/CodeGen/SystemZ/Large/branch-01.ll | 11953 +++++++ test/CodeGen/SystemZ/Large/lit.local.cfg | 2 +- test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir | 90 +- test/CodeGen/SystemZ/anyregcc-novec.ll | 65 + test/CodeGen/SystemZ/anyregcc-vec.ll | 99 + test/CodeGen/SystemZ/anyregcc.ll | 449 + test/CodeGen/SystemZ/asm-19.ll | 138 + test/CodeGen/SystemZ/branch-07.ll | 8 +- test/CodeGen/SystemZ/bswap-02.ll | 95 +- test/CodeGen/SystemZ/bswap-03.ll | 95 +- test/CodeGen/SystemZ/bswap-04.ll | 11 - test/CodeGen/SystemZ/bswap-05.ll | 11 - test/CodeGen/SystemZ/bswap-06.ll | 11 - test/CodeGen/SystemZ/bswap-07.ll | 12 - test/CodeGen/SystemZ/clear-liverange-spillreg.mir | 212 +- test/CodeGen/SystemZ/cmpxchg-01.ll | 80 + test/CodeGen/SystemZ/cmpxchg-02.ll | 79 + test/CodeGen/SystemZ/cmpxchg-03.ll | 39 + test/CodeGen/SystemZ/cmpxchg-04.ll | 38 + test/CodeGen/SystemZ/cmpxchg-06.ll | 51 + test/CodeGen/SystemZ/cond-move-04.mir | 12 +- test/CodeGen/SystemZ/cond-move-05.mir | 8 +- test/CodeGen/SystemZ/dag-combine-02.ll | 8 +- test/CodeGen/SystemZ/fp-cmp-07.mir | 20 +- test/CodeGen/SystemZ/fp-conv-17.mir | 112 +- test/CodeGen/SystemZ/insert-05.ll | 4 +- test/CodeGen/SystemZ/load-and-test.mir | 52 + test/CodeGen/SystemZ/loop-01.ll | 10 +- test/CodeGen/SystemZ/loop-03.ll | 6 +- test/CodeGen/SystemZ/loop-04.ll | 25 + test/CodeGen/SystemZ/lower-copy-undef-src.mir | 6 +- test/CodeGen/SystemZ/memcpy-01.ll | 92 +- test/CodeGen/SystemZ/memset-01.ll | 62 +- test/CodeGen/SystemZ/memset-02.ll | 68 +- test/CodeGen/SystemZ/memset-03.ll | 164 +- test/CodeGen/SystemZ/memset-04.ll | 164 +- test/CodeGen/SystemZ/patchpoint-invoke.ll | 65 + test/CodeGen/SystemZ/patchpoint.ll | 102 + test/CodeGen/SystemZ/pr32505.ll | 4 +- test/CodeGen/SystemZ/pr36164.ll | 113 + .../SystemZ/regalloc-fast-invalid-kill-flag.mir | 10 +- test/CodeGen/SystemZ/setcc-03.ll | 73 + test/CodeGen/SystemZ/setcc-04.ll | 173 + test/CodeGen/SystemZ/stack-size-section.ll | 38 + test/CodeGen/SystemZ/stackmap-nops.ll | 140 + .../SystemZ/stackmap-shadow-optimization.ll | 27 + test/CodeGen/SystemZ/stackmap.ll | 537 + test/CodeGen/SystemZ/store_nonbytesized_vecs.ll | 143 + test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll | 12 +- test/CodeGen/SystemZ/vec-intrinsics-01.ll | 75 +- test/CodeGen/SystemZ/vec-intrinsics-02.ll | 17 +- test/CodeGen/SystemZ/vec-load-element.ll | 86 + test/CodeGen/SystemZ/vec-move-17.ll | 10 +- test/CodeGen/SystemZ/vec-sub-01.ll | 12 +- test/CodeGen/SystemZ/vec-trunc-to-i1.ll | 4 +- test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll | 10 +- test/CodeGen/Thumb/PR35481.ll | 24 + test/CodeGen/Thumb/branchless-cmp.ll | 140 +- test/CodeGen/Thumb/constants.ll | 17 + test/CodeGen/Thumb/dyn-stackalloc.ll | 4 +- test/CodeGen/Thumb/frame-access.ll | 416 + .../Thumb/ldm-stm-base-materialization-thumb2.ll | 10 +- test/CodeGen/Thumb/ldm-stm-base-materialization.ll | 10 +- test/CodeGen/Thumb/long-setcc.ll | 8 +- test/CodeGen/Thumb/long.ll | 20 +- test/CodeGen/Thumb/machine-cse-physreg.mir | 24 +- test/CodeGen/Thumb/mvn.ll | 222 + test/CodeGen/Thumb/pr35836.ll | 56 + test/CodeGen/Thumb/pr35836_2.ll | 57 + .../Thumb/stack-coloring-without-frame-ptr.ll | 4 +- test/CodeGen/Thumb/stm-scavenging.ll | 46 + test/CodeGen/Thumb/tbb-reuse.mir | 82 +- test/CodeGen/Thumb/thumb-shrink-wrapping.ll | 2 +- .../CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll | 4 +- test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | 4 +- test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll | 4 +- test/CodeGen/Thumb2/aapcs.ll | 2 +- test/CodeGen/Thumb2/cmp-frame.ll | 11 + test/CodeGen/Thumb2/float-cmp.ll | 19 +- test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir | 32 +- test/CodeGen/Thumb2/t2sizereduction.mir | 52 +- test/CodeGen/Thumb2/tbb-removeadd.mir | 46 +- test/CodeGen/Thumb2/thumb2-cmn.ll | 40 +- test/CodeGen/Thumb2/thumb2-cmn2.ll | 20 +- test/CodeGen/Thumb2/thumb2-cmp.ll | 25 +- test/CodeGen/Thumb2/thumb2-select_xform.ll | 14 +- test/CodeGen/Thumb2/thumb2-teq.ll | 79 +- test/CodeGen/Thumb2/thumb2-teq2.ll | 30 +- test/CodeGen/Thumb2/thumb2-tst.ll | 81 +- test/CodeGen/Thumb2/thumb2-tst2.ll | 30 +- test/CodeGen/WebAssembly/comdat.ll | 5 - test/CodeGen/WebAssembly/comparisons_f32.ll | 57 +- test/CodeGen/WebAssembly/comparisons_f64.ll | 56 +- test/CodeGen/WebAssembly/dbgvalue.ll | 2 +- test/CodeGen/WebAssembly/global.ll | 4 +- test/CodeGen/WebAssembly/i128-returned.ll | 20 + test/CodeGen/WebAssembly/implicit-def.ll | 2 +- test/CodeGen/WebAssembly/import-module.ll | 19 + test/CodeGen/WebAssembly/libcalls.ll | 107 + test/CodeGen/WebAssembly/load-ext-atomic.ll | 2 +- test/CodeGen/WebAssembly/mem-intrinsics.ll | 26 +- test/CodeGen/WebAssembly/memory-addr32.ll | 21 + test/CodeGen/WebAssembly/offset-atomics.ll | 2 +- test/CodeGen/WebAssembly/signext-arg.ll | 12 +- test/CodeGen/WebAssembly/signext-inreg.ll | 20 +- test/CodeGen/WebAssembly/umulo-i64.ll | 6 +- test/CodeGen/WinCFGuard/cfguard.ll | 162 + test/CodeGen/{MIR/X86 => WinCFGuard}/lit.local.cfg | 0 test/CodeGen/X86/2006-03-01-InstrSchedBug.ll | 2 +- test/CodeGen/X86/2006-11-17-IllegalMove.ll | 2 +- test/CodeGen/X86/2007-05-15-maskmovq.ll | 28 +- test/CodeGen/X86/2007-07-03-GR64ToVR64.ll | 14 +- test/CodeGen/X86/2007-10-15-CoalescerCrash.ll | 2 +- test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll | 34 +- test/CodeGen/X86/2009-01-25-NoSSE.ll | 4 +- test/CodeGen/X86/2009-02-26-MachineLICMBug.ll | 45 +- test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll | 4 +- test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll | 4 +- test/CodeGen/X86/2010-04-08-CoalescerBug.ll | 4 +- test/CodeGen/X86/2010-04-21-CoalescerBug.ll | 4 +- test/CodeGen/X86/2010-05-12-FastAllocKills.ll | 8 +- test/CodeGen/X86/2010-05-28-Crash.ll | 2 +- test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll | 2 +- .../X86/2010-06-25-CoalescerSubRegDefDead.ll | 4 +- test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll | 4 +- test/CodeGen/X86/2011-12-8-bitcastintprom.ll | 4 +- test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll | 8 +- test/CodeGen/X86/2012-01-18-vbitcast.ll | 19 +- test/CodeGen/X86/2012-08-16-setcc.ll | 4 +- test/CodeGen/X86/3addr-16bit.ll | 237 +- test/CodeGen/X86/3addr-or.ll | 84 +- test/CodeGen/X86/3dnow-intrinsics.ll | 719 +- test/CodeGen/X86/3dnow-schedule.ll | 2 +- test/CodeGen/X86/GlobalISel/add-scalar.ll | 10 +- .../X86/GlobalISel/avoid-matchtable-crash.mir | 36 + test/CodeGen/X86/GlobalISel/callingconv.ll | 72 +- test/CodeGen/X86/GlobalISel/ext-x86-64.ll | 2 +- test/CodeGen/X86/GlobalISel/ext.ll | 4 +- test/CodeGen/X86/GlobalISel/gep.ll | 4 +- test/CodeGen/X86/GlobalISel/inttoptr.ll | 12 + .../X86/GlobalISel/irtranslator-callingconv.ll | 1243 +- test/CodeGen/X86/GlobalISel/legalize-GV.mir | 31 - test/CodeGen/X86/GlobalISel/legalize-add-v128.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-add-v256.mir | 40 +- test/CodeGen/X86/GlobalISel/legalize-add-v512.mir | 78 +- test/CodeGen/X86/GlobalISel/legalize-add.mir | 26 +- .../CodeGen/X86/GlobalISel/legalize-and-scalar.mir | 40 +- test/CodeGen/X86/GlobalISel/legalize-brcond.mir | 20 +- test/CodeGen/X86/GlobalISel/legalize-cmp.mir | 90 +- test/CodeGen/X86/GlobalISel/legalize-constant.mir | 42 +- .../CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir | 168 +- test/CodeGen/X86/GlobalISel/legalize-ext.mir | 381 +- .../X86/GlobalISel/legalize-fadd-scalar.mir | 62 +- .../X86/GlobalISel/legalize-fdiv-scalar.mir | 62 +- .../X86/GlobalISel/legalize-fmul-scalar.mir | 62 +- .../X86/GlobalISel/legalize-fpext-scalar.mir | 24 +- .../X86/GlobalISel/legalize-fsub-scalar.mir | 62 +- .../X86/GlobalISel/legalize-insert-vec256.mir | 18 +- .../X86/GlobalISel/legalize-insert-vec512.mir | 36 +- .../X86/GlobalISel/legalize-memop-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-mul-scalar.mir | 58 +- test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/legalize-phi.mir | 421 +- test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-sub.mir | 24 +- .../CodeGen/X86/GlobalISel/legalize-xor-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/ptrtoint.ll | 52 + test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir | 14 +- .../X86/GlobalISel/regbankselect-AVX512.mir | 14 +- .../X86/GlobalISel/regbankselect-X86_64.mir | 1326 +- test/CodeGen/X86/GlobalISel/select-GV.mir | 54 +- test/CodeGen/X86/GlobalISel/select-add-v128.mir | 40 +- test/CodeGen/X86/GlobalISel/select-add-v256.mir | 40 +- test/CodeGen/X86/GlobalISel/select-add-v512.mir | 72 +- test/CodeGen/X86/GlobalISel/select-add-x32.mir | 22 +- test/CodeGen/X86/GlobalISel/select-add.mir | 100 +- test/CodeGen/X86/GlobalISel/select-and-scalar.mir | 80 +- test/CodeGen/X86/GlobalISel/select-blsi.mir | 28 +- test/CodeGen/X86/GlobalISel/select-blsr.mir | 26 +- test/CodeGen/X86/GlobalISel/select-brcond.mir | 30 +- test/CodeGen/X86/GlobalISel/select-cmp.mir | 312 +- test/CodeGen/X86/GlobalISel/select-constant.mir | 66 +- test/CodeGen/X86/GlobalISel/select-copy.mir | 138 +- test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir | 103 +- test/CodeGen/X86/GlobalISel/select-ext.mir | 263 +- .../X86/GlobalISel/select-extract-vec256.mir | 36 +- .../X86/GlobalISel/select-extract-vec512.mir | 56 +- test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir | 157 +- test/CodeGen/X86/GlobalISel/select-fconstant.mir | 98 +- test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir | 157 +- test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir | 157 +- .../CodeGen/X86/GlobalISel/select-fpext-scalar.mir | 24 +- test/CodeGen/X86/GlobalISel/select-frameIndex.mir | 36 - test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir | 157 +- test/CodeGen/X86/GlobalISel/select-gep.mir | 16 +- test/CodeGen/X86/GlobalISel/select-inc.mir | 8 +- .../X86/GlobalISel/select-insert-vec256.mir | 92 +- .../X86/GlobalISel/select-insert-vec512.mir | 128 +- .../select-intrinsic-x86-flags-read-u32.mir | 17 +- .../X86/GlobalISel/select-leaf-constant.mir | 36 +- .../X86/GlobalISel/select-memop-scalar-x32.mir | 96 +- .../CodeGen/X86/GlobalISel/select-memop-scalar.mir | 880 +- test/CodeGen/X86/GlobalISel/select-memop-v128.mir | 92 +- test/CodeGen/X86/GlobalISel/select-memop-v256.mir | 112 +- test/CodeGen/X86/GlobalISel/select-memop-v512.mir | 56 +- .../CodeGen/X86/GlobalISel/select-merge-vec256.mir | 14 +- .../CodeGen/X86/GlobalISel/select-merge-vec512.mir | 18 +- test/CodeGen/X86/GlobalISel/select-mul-scalar.mir | 60 +- test/CodeGen/X86/GlobalISel/select-mul-vec.mir | 270 +- test/CodeGen/X86/GlobalISel/select-or-scalar.mir | 80 +- test/CodeGen/X86/GlobalISel/select-phi.mir | 405 +- test/CodeGen/X86/GlobalISel/select-sub-v128.mir | 40 +- test/CodeGen/X86/GlobalISel/select-sub-v256.mir | 40 +- test/CodeGen/X86/GlobalISel/select-sub-v512.mir | 72 +- test/CodeGen/X86/GlobalISel/select-sub.mir | 60 +- test/CodeGen/X86/GlobalISel/select-trunc.mir | 86 +- test/CodeGen/X86/GlobalISel/select-undef.mir | 46 +- .../X86/GlobalISel/select-unmerge-vec256.mir | 18 +- .../X86/GlobalISel/select-unmerge-vec512.mir | 16 +- test/CodeGen/X86/GlobalISel/select-xor-scalar.mir | 80 +- .../X86/GlobalISel/x32-select-frameIndex.mir | 34 + test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir | 30 + .../X86/GlobalISel/x86-legalize-inttoptr.mir | 39 + .../X86/GlobalISel/x86-legalize-ptrtoint.mir | 141 + .../X86/GlobalISel/x86-select-frameIndex.mir | 34 + .../CodeGen/X86/GlobalISel/x86-select-inttoptr.mir | 39 + .../CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir | 143 + test/CodeGen/X86/GlobalISel/x86_64-fallback.ll | 2 +- test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir | 30 + .../X86/GlobalISel/x86_64-legalize-inttoptr.mir | 35 + .../X86/GlobalISel/x86_64-legalize-ptrtoint.mir | 154 + .../X86/GlobalISel/x86_64-select-frameIndex.mir | 34 + .../X86/GlobalISel/x86_64-select-inttoptr.mir | 36 + .../X86/GlobalISel/x86_64-select-ptrtoint.mir | 162 + test/CodeGen/X86/MachineBranchProb.ll | 8 +- test/CodeGen/X86/O0-pipeline.ll | 3 + test/CodeGen/X86/add-i64.ll | 27 + test/CodeGen/X86/add-sub-nsw-nuw.ll | 2 +- test/CodeGen/X86/add.ll | 4 +- test/CodeGen/X86/addcarry.ll | 5 +- test/CodeGen/X86/addcarry2.ll | 296 + test/CodeGen/X86/alignment-2.ll | 4 +- test/CodeGen/X86/and-encoding.ll | 109 +- test/CodeGen/X86/and-sink.ll | 4 +- test/CodeGen/X86/and-su.ll | 45 +- test/CodeGen/X86/anyext.ll | 8 +- test/CodeGen/X86/arg-copy-elide.ll | 2 +- test/CodeGen/X86/asm-reject-rex.ll | 21 + test/CodeGen/X86/asm-reject-xmm16.ll | 8 + test/CodeGen/X86/atomic-eflags-reuse.ll | 2 +- test/CodeGen/X86/atomic32.ll | 757 +- test/CodeGen/X86/avg-mask.ll | 132 +- test/CodeGen/X86/avg.ll | 1433 +- test/CodeGen/X86/avx-brcond.ll | 121 +- test/CodeGen/X86/avx-cast.ll | 33 +- test/CodeGen/X86/avx-cmp.ll | 2 +- test/CodeGen/X86/avx-insertelt.ll | 9 +- test/CodeGen/X86/avx-intrinsics-fast-isel.ll | 68 +- test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 10 +- test/CodeGen/X86/avx-intrinsics-x86.ll | 17 +- test/CodeGen/X86/avx-load-store.ll | 32 +- test/CodeGen/X86/avx-schedule.ll | 108 +- test/CodeGen/X86/avx-splat.ll | 2 +- test/CodeGen/X86/avx-vinsertf128.ll | 6 +- test/CodeGen/X86/avx-vperm2x128.ll | 32 +- test/CodeGen/X86/avx-vzeroupper.ll | 12 +- test/CodeGen/X86/avx2-conversions.ll | 54 +- test/CodeGen/X86/avx2-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/avx2-masked-gather.ll | 24 +- test/CodeGen/X86/avx2-schedule.ll | 138 +- test/CodeGen/X86/avx2-shift.ll | 8 +- test/CodeGen/X86/avx2-vbroadcast.ll | 35 +- test/CodeGen/X86/avx2-vector-shifts.ll | 72 +- test/CodeGen/X86/avx512-arith.ll | 108 +- test/CodeGen/X86/avx512-bugfix-25270.ll | 4 +- test/CodeGen/X86/avx512-build-vector.ll | 2 +- test/CodeGen/X86/avx512-calling-conv.ll | 48 +- test/CodeGen/X86/avx512-cmp-kor-sequence.ll | 37 +- test/CodeGen/X86/avx512-cmp.ll | 20 +- test/CodeGen/X86/avx512-cvt.ll | 1342 +- test/CodeGen/X86/avx512-ext.ll | 351 +- .../X86/avx512-extract-subvector-load-store.ll | 36 +- test/CodeGen/X86/avx512-extract-subvector.ll | 4 +- test/CodeGen/X86/avx512-hadd-hsub.ll | 20 +- test/CodeGen/X86/avx512-insert-extract.ll | 647 +- test/CodeGen/X86/avx512-insert-extract_i1.ll | 4 +- test/CodeGen/X86/avx512-intel-ocl.ll | 536 +- test/CodeGen/X86/avx512-intrinsics-fast-isel.ll | 148 +- test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 386 +- test/CodeGen/X86/avx512-intrinsics.ll | 246 +- test/CodeGen/X86/avx512-load-store.ll | 14 +- test/CodeGen/X86/avx512-load-trunc-store-i1.ll | 57 +- test/CodeGen/X86/avx512-mask-op.ll | 2011 +- test/CodeGen/X86/avx512-mask-zext-bugfix.ll | 50 +- test/CodeGen/X86/avx512-masked-memop-64-32.ll | 32 +- test/CodeGen/X86/avx512-memfold.ll | 2 +- test/CodeGen/X86/avx512-mov.ll | 24 +- test/CodeGen/X86/avx512-regcall-Mask.ll | 140 +- test/CodeGen/X86/avx512-regcall-NoMask.ll | 42 +- test/CodeGen/X86/avx512-scalar.ll | 169 +- test/CodeGen/X86/avx512-schedule.ll | 828 +- test/CodeGen/X86/avx512-select.ll | 12 +- test/CodeGen/X86/avx512-shift.ll | 10 +- test/CodeGen/X86/avx512-shuffle-schedule.ll | 4224 +-- .../X86/avx512-shuffles/broadcast-scalar-int.ll | 552 +- .../X86/avx512-shuffles/broadcast-vector-int.ll | 344 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 1155 +- test/CodeGen/X86/avx512-shuffles/permute.ll | 368 +- test/CodeGen/X86/avx512-shuffles/shuffle-vec.ll | 208 +- test/CodeGen/X86/avx512-shuffles/shuffle.ll | 576 +- test/CodeGen/X86/avx512-skx-insert-subvec.ll | 28 +- test/CodeGen/X86/avx512-trunc.ll | 42 +- test/CodeGen/X86/avx512-vbroadcast.ll | 32 +- test/CodeGen/X86/avx512-vec-cmp.ll | 978 +- test/CodeGen/X86/avx512-vec3-crash.ll | 11 +- test/CodeGen/X86/avx512-vpternlog-commute.ll | 8 +- test/CodeGen/X86/avx512-vselect.ll | 19 +- test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll | 2271 +- test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll | 1795 +- test/CodeGen/X86/avx512bw-intrinsics.ll | 101 +- test/CodeGen/X86/avx512bw-mask-op.ll | 10 +- test/CodeGen/X86/avx512bw-mov.ll | 28 +- test/CodeGen/X86/avx512bw-vec-cmp.ll | 6 +- test/CodeGen/X86/avx512bw-vec-test-testn.ll | 16 +- test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll | 468 +- test/CodeGen/X86/avx512bwvl-intrinsics.ll | 147 +- test/CodeGen/X86/avx512bwvl-mov.ll | 24 +- test/CodeGen/X86/avx512bwvl-vec-cmp.ll | 12 +- test/CodeGen/X86/avx512bwvl-vec-test-testn.ll | 56 +- test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll | 1 + test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll | 2 + test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll | 55 +- test/CodeGen/X86/avx512dq-intrinsics.ll | 38 +- test/CodeGen/X86/avx512dq-mask-op.ll | 8 +- test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll | 59 +- test/CodeGen/X86/avx512dqvl-intrinsics.ll | 60 +- test/CodeGen/X86/avx512f-vec-test-testn.ll | 64 +- test/CodeGen/X86/avx512vl-arith.ll | 138 +- test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll | 1342 +- test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 437 +- test/CodeGen/X86/avx512vl-intrinsics.ll | 49 +- test/CodeGen/X86/avx512vl-mov.ll | 84 +- test/CodeGen/X86/avx512vl-vbroadcast.ll | 21 +- test/CodeGen/X86/avx512vl-vec-cmp.ll | 475 +- test/CodeGen/X86/avx512vl-vec-masked-cmp.ll | 28249 +++------------ test/CodeGen/X86/avx512vl-vec-test-testn.ll | 82 +- test/CodeGen/X86/bad-tls-fold.mir | 77 + test/CodeGen/X86/bitcast-and-setcc-128.ll | 102 +- test/CodeGen/X86/bitcast-and-setcc-256.ll | 76 +- test/CodeGen/X86/bitcast-and-setcc-512.ll | 813 +- .../CodeGen/X86/bitcast-int-to-vector-bool-sext.ll | 118 +- .../CodeGen/X86/bitcast-int-to-vector-bool-zext.ll | 281 +- test/CodeGen/X86/bitcast-int-to-vector-bool.ll | 6 +- test/CodeGen/X86/bitcast-int-to-vector.ll | 2 +- test/CodeGen/X86/bitcast-setcc-128.ll | 208 +- test/CodeGen/X86/bitcast-setcc-256.ll | 66 +- test/CodeGen/X86/bitcast-setcc-512.ll | 739 +- test/CodeGen/X86/bitcnt-false-dep.ll | 172 + test/CodeGen/X86/bitreverse.ll | 14 +- test/CodeGen/X86/block-placement.mir | 32 +- test/CodeGen/X86/bmi-schedule.ll | 24 +- test/CodeGen/X86/bmi.ll | 57 +- test/CodeGen/X86/bool-simplify.ll | 8 +- test/CodeGen/X86/bool-vector.ll | 8 +- test/CodeGen/X86/branchfolding-undef.mir | 14 +- test/CodeGen/X86/brcond.ll | 160 +- test/CodeGen/X86/break-false-dep.ll | 4 +- test/CodeGen/X86/broadcastm-lowering.ll | 23 +- test/CodeGen/X86/bswap.ll | 135 +- test/CodeGen/X86/bug26810.ll | 7 +- test/CodeGen/X86/buildvec-insertvec.ll | 19 +- test/CodeGen/X86/bypass-slow-division-32.ll | 18 +- test/CodeGen/X86/bypass-slow-division-64.ll | 8 +- test/CodeGen/X86/catchpad-weight.ll | 2 +- .../CodeGen/X86/clear_upper_vector_element_bits.ll | 925 +- test/CodeGen/X86/clwb.ll | 7 + test/CodeGen/X86/clz.ll | 189 +- test/CodeGen/X86/cmov-into-branch.ll | 2 +- test/CodeGen/X86/cmov-promotion.ll | 17 +- test/CodeGen/X86/cmov.ll | 2 +- test/CodeGen/X86/cmp.ll | 2 +- test/CodeGen/X86/cmpxchg-i128-i1.ll | 108 +- test/CodeGen/X86/cmpxchg16b.ll | 15 +- test/CodeGen/X86/cmpxchg8b.ll | 31 + test/CodeGen/X86/coalesce_commute_movsd.ll | 4 +- test/CodeGen/X86/coff-no-dead-strip.ll | 22 + test/CodeGen/X86/combine-abs.ll | 4 +- test/CodeGen/X86/combine-and.ll | 59 +- test/CodeGen/X86/combine-fabs.ll | 141 + test/CodeGen/X86/combine-fcopysign.ll | 43 +- test/CodeGen/X86/combine-mul.ll | 26 - test/CodeGen/X86/combine-or.ll | 40 +- test/CodeGen/X86/combine-sdiv.ll | 3826 +- test/CodeGen/X86/combine-shl.ll | 72 +- test/CodeGen/X86/combine-smax.ll | 47 + test/CodeGen/X86/combine-smin.ll | 47 + test/CodeGen/X86/combine-sra.ll | 120 +- test/CodeGen/X86/combine-srem.ll | 35 - test/CodeGen/X86/combine-srl.ll | 85 +- test/CodeGen/X86/combine-testm-and.ll | 21 +- test/CodeGen/X86/combine-udiv.ll | 35 - test/CodeGen/X86/combine-umax.ll | 43 + test/CodeGen/X86/combine-umin.ll | 43 + test/CodeGen/X86/combine-urem.ll | 35 - test/CodeGen/X86/commute-blend-avx2.ll | 4 +- test/CodeGen/X86/commute-blend-sse41.ll | 2 +- test/CodeGen/X86/commute-fcmp.ll | 160 +- test/CodeGen/X86/commute-xop.ll | 4 +- test/CodeGen/X86/commuted-blend-mask.ll | 4 +- test/CodeGen/X86/complex-fastmath.ll | 10 +- test/CodeGen/X86/compress_expand.ll | 99 +- test/CodeGen/X86/conditional-tailcall-samedest.mir | 30 +- test/CodeGen/X86/critical-edge-split-2.ll | 2 +- test/CodeGen/X86/ctpop-combine.ll | 2 +- test/CodeGen/X86/cvtv2f32.ll | 16 +- test/CodeGen/X86/dagcombine-cse.ll | 4 +- test/CodeGen/X86/darwin-bzero.ll | 13 +- test/CodeGen/X86/divide-by-constant.ll | 42 +- test/CodeGen/X86/divrem.ll | 12 +- test/CodeGen/X86/divrem8_ext.ll | 72 +- test/CodeGen/X86/dllexport-x86_64.ll | 64 +- test/CodeGen/X86/dllexport.ll | 68 +- test/CodeGen/X86/domain-reassignment.mir | 675 +- test/CodeGen/X86/dwarf-comp-dir.ll | 6 +- test/CodeGen/X86/dynamic-regmask.ll | 30 + test/CodeGen/X86/eflags-copy-expansion.mir | 22 +- test/CodeGen/X86/eh-label.ll | 2 +- test/CodeGen/X86/eh-unknown.ll | 15 +- test/CodeGen/X86/emutls-pic.ll | 7 + test/CodeGen/X86/emutls-pie.ll | 11 + test/CodeGen/X86/emutls.ll | 9 +- test/CodeGen/X86/emutls_generic.ll | 11 + test/CodeGen/X86/evex-to-vex-compress.mir | 9132 ++--- test/CodeGen/X86/expand-vr64-gr64-copy.mir | 24 +- test/CodeGen/X86/extract-store.ll | 4 +- test/CodeGen/X86/extractelement-index.ll | 50 +- test/CodeGen/X86/f16c-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/fabs.ll | 126 +- test/CodeGen/X86/fast-isel-bc.ll | 40 +- test/CodeGen/X86/fast-isel-call.ll | 8 +- test/CodeGen/X86/fast-isel-cmp.ll | 8 +- test/CodeGen/X86/fast-isel-deadcode.ll | 6 +- test/CodeGen/X86/fast-isel-emutls.ll | 4 + test/CodeGen/X86/fast-isel-nontemporal.ll | 36 +- test/CodeGen/X86/fast-isel-sext-zext.ll | 16 +- test/CodeGen/X86/fast-isel-shift.ll | 24 +- test/CodeGen/X86/fast-isel-x86-64.ll | 4 +- test/CodeGen/X86/finite-libcalls.ll | 399 +- test/CodeGen/X86/fixup-bw-copy.ll | 2 +- test/CodeGen/X86/fixup-bw-copy.mir | 70 +- test/CodeGen/X86/fixup-bw-inst.mir | 157 +- test/CodeGen/X86/fltused.ll | 2 +- test/CodeGen/X86/fltused_function_pointer.ll | 2 +- test/CodeGen/X86/fma.ll | 8 +- test/CodeGen/X86/fmaxnum.ll | 8 +- test/CodeGen/X86/fmf-flags.ll | 2 +- test/CodeGen/X86/fminnum.ll | 8 +- test/CodeGen/X86/fold-rmw-ops.ll | 15 +- test/CodeGen/X86/fold-vector-sext-crash.ll | 4 +- test/CodeGen/X86/force-align-stack-alloca.ll | 4 +- test/CodeGen/X86/fp-arith.ll | 621 + test/CodeGen/X86/fp-intrinsics.ll | 4 +- test/CodeGen/X86/fp128-cast.ll | 27 + test/CodeGen/X86/fp128-extract.ll | 29 +- test/CodeGen/X86/fp128-i128.ll | 4 +- test/CodeGen/X86/gather-addresses.ll | 271 +- test/CodeGen/X86/global-access-pie-copyrelocs.ll | 7 +- test/CodeGen/X86/global-access-pie.ll | 7 +- test/CodeGen/X86/gpr-to-mask.ll | 72 +- .../X86/greedy_regalloc_bad_eviction_sequence.ll | 14 +- test/CodeGen/X86/h-registers-1.ll | 38 +- test/CodeGen/X86/haddsub-2.ll | 12 +- test/CodeGen/X86/haddsub-3.ll | 39 + test/CodeGen/X86/haddsub-undef.ll | 4 +- test/CodeGen/X86/half.ll | 10 +- test/CodeGen/X86/hidden-vis-3.ll | 2 +- test/CodeGen/X86/horizontal-reduce-smax.ll | 373 +- test/CodeGen/X86/horizontal-reduce-smin.ll | 425 +- test/CodeGen/X86/horizontal-reduce-umax.ll | 819 +- test/CodeGen/X86/horizontal-reduce-umin.ll | 685 +- test/CodeGen/X86/i128-mul.ll | 362 +- test/CodeGen/X86/i386-shrink-wrapping.ll | 11 +- test/CodeGen/X86/i64-to-float.ll | 113 +- test/CodeGen/X86/iabs.ll | 2 +- test/CodeGen/X86/illegal-bitfield-loadstore.ll | 6 +- test/CodeGen/X86/immediate_merging.ll | 4 +- test/CodeGen/X86/immediate_merging64.ll | 4 +- test/CodeGen/X86/implicit-null-checks.mir | 748 +- test/CodeGen/X86/implicit-use-spill.mir | 4 +- test/CodeGen/X86/imul.ll | 4 +- test/CodeGen/X86/indirect-branch-tracking.ll | 200 + test/CodeGen/X86/inline-asm-A-constraint.ll | 3 +- test/CodeGen/X86/inline-asm-fpstack.ll | 1 + test/CodeGen/X86/inline-asm-modifier-V.ll | 14 + test/CodeGen/X86/insert-into-constant-vector.ll | 6 +- test/CodeGen/X86/insertelement-ones.ll | 2 +- test/CodeGen/X86/insertelement-shuffle.ll | 17 +- test/CodeGen/X86/insertelement-zero.ll | 138 +- test/CodeGen/X86/invalid-liveness.mir | 6 +- test/CodeGen/X86/ipra-inline-asm.ll | 2 +- test/CodeGen/X86/ipra-local-linkage.ll | 2 +- test/CodeGen/X86/ipra-reg-alias.ll | 2 +- test/CodeGen/X86/ipra-reg-usage.ll | 2 +- test/CodeGen/X86/jump_sign.ll | 3 +- test/CodeGen/X86/known-bits-vector.ll | 8 +- test/CodeGen/X86/known-bits.ll | 2 - test/CodeGen/X86/lea-3.ll | 8 +- test/CodeGen/X86/lea-opt-cse3.ll | 16 +- test/CodeGen/X86/lea-opt-memop-check-1.ll | 4 +- test/CodeGen/X86/lea-opt-with-debug.mir | 30 +- test/CodeGen/X86/lea32-schedule.ll | 306 +- test/CodeGen/X86/leaFixup32.mir | 182 +- test/CodeGen/X86/leaFixup64.mir | 372 +- test/CodeGen/X86/legalize-shift.ll | 37 + test/CodeGen/X86/legalize-shl-vec.ll | 190 +- test/CodeGen/X86/live-out-reg-info.ll | 4 +- test/CodeGen/X86/load-slice.ll | 2 +- test/CodeGen/X86/localescape.ll | 2 +- test/CodeGen/X86/loop-search.ll | 6 +- test/CodeGen/X86/lsr-normalization.ll | 4 +- test/CodeGen/X86/lzcnt-schedule.ll | 12 +- test/CodeGen/X86/lzcnt-tzcnt.ll | 223 +- test/CodeGen/X86/lzcnt-zext-cmp.ll | 6 +- test/CodeGen/X86/machine-combiner-int-vec.ll | 4 +- test/CodeGen/X86/machine-combiner-int.ll | 8 +- test/CodeGen/X86/machine-combiner.ll | 4 +- test/CodeGen/X86/machine-copy-prop.mir | 192 +- test/CodeGen/X86/machine-cp.ll | 139 +- test/CodeGen/X86/machine-cse.ll | 6 +- test/CodeGen/X86/machine-outliner-disubprogram.ll | 214 + test/CodeGen/X86/machine-region-info.mir | 28 +- test/CodeGen/X86/madd.ll | 1324 +- test/CodeGen/X86/masked_gather_scatter.ll | 905 +- test/CodeGen/X86/masked_memop.ll | 307 +- test/CodeGen/X86/mcu-abi.ll | 4 +- test/CodeGen/X86/mem-intrin-base-reg.ll | 10 +- test/CodeGen/X86/memcmp-mergeexpand.ll | 66 + test/CodeGen/X86/memcpy-2.ll | 10 +- test/CodeGen/X86/memcpy-from-string.ll | 4 +- test/CodeGen/X86/memcpy.ll | 24 +- test/CodeGen/X86/memset-2.ll | 10 +- test/CodeGen/X86/memset-3.ll | 4 +- test/CodeGen/X86/memset-nonzero.ll | 18 +- test/CodeGen/X86/memset-sse-stack-realignment.ll | 6 +- test/CodeGen/X86/memset.ll | 6 +- test/CodeGen/X86/memset64-on-x86-32.ll | 4 +- test/CodeGen/X86/merge-consecutive-loads-256.ll | 12 +- test/CodeGen/X86/misaligned-memset.ll | 4 +- test/CodeGen/X86/misched-copy.ll | 8 +- test/CodeGen/X86/misched-new.ll | 4 +- test/CodeGen/X86/mmx-arith.ll | 609 +- test/CodeGen/X86/mmx-build-vector.ll | 1858 + test/CodeGen/X86/mmx-fold-load.ll | 21 +- test/CodeGen/X86/mmx-fold-zero.ll | 109 + test/CodeGen/X86/mmx-schedule.ll | 136 +- test/CodeGen/X86/movmsk.ll | 2 +- test/CodeGen/X86/movtopush.mir | 80 +- test/CodeGen/X86/mul-constant-i16.ll | 180 +- test/CodeGen/X86/mul-constant-i32.ll | 190 +- test/CodeGen/X86/mul-constant-result.ll | 48 +- test/CodeGen/X86/mul-i1024.ll | 165 +- test/CodeGen/X86/mul-i256.ll | 10 +- test/CodeGen/X86/mul-i512.ll | 45 +- test/CodeGen/X86/mul128.ll | 2 +- test/CodeGen/X86/mulvi32.ll | 124 +- test/CodeGen/X86/musttail-varargs.ll | 487 +- test/CodeGen/X86/negate-add-zero.ll | 2 +- test/CodeGen/X86/negate-i1.ll | 6 +- test/CodeGen/X86/negative-sin.ll | 6 +- test/CodeGen/X86/no-plt.ll | 49 +- test/CodeGen/X86/no-stack-arg-probe.ll | 38 + test/CodeGen/X86/non-value-mem-operand.mir | 212 +- test/CodeGen/X86/nontemporal-loads.ll | 3 +- test/CodeGen/X86/oddshuffles.ll | 378 +- test/CodeGen/{MIR => }/X86/opt_phis.mir | 0 test/CodeGen/X86/optimize-max-0.ll | 20 +- test/CodeGen/X86/or-branch.ll | 27 +- test/CodeGen/X86/or-lea.ll | 26 +- test/CodeGen/X86/patchpoint-invoke.ll | 12 +- test/CodeGen/X86/patchpoint-verifiable.mir | 20 +- test/CodeGen/X86/patchpoint.ll | 15 + test/CodeGen/X86/peephole-recurrence.mir | 66 +- test/CodeGen/X86/pmul.ll | 118 +- test/CodeGen/X86/popcnt-schedule.ll | 16 +- test/CodeGen/X86/popcnt.ll | 14 +- test/CodeGen/X86/post-ra-sched-with-debug.mir | 126 +- test/CodeGen/X86/powi.ll | 2 +- test/CodeGen/X86/pr11334.ll | 2 +- test/CodeGen/X86/pr11985.ll | 4 +- test/CodeGen/X86/pr12312.ll | 243 - test/CodeGen/X86/pr12360.ll | 21 +- test/CodeGen/X86/pr13577.ll | 1 - test/CodeGen/X86/pr14333.ll | 4 +- test/CodeGen/X86/pr18344.ll | 12 +- test/CodeGen/X86/pr20011.ll | 20 +- test/CodeGen/X86/pr21792.ll | 20 +- test/CodeGen/X86/pr22970.ll | 2 +- test/CodeGen/X86/pr27591.ll | 2 +- test/CodeGen/X86/pr27681.mir | 94 +- test/CodeGen/X86/pr28173.ll | 4 +- test/CodeGen/X86/pr28560.ll | 2 +- test/CodeGen/X86/pr29061.ll | 4 +- test/CodeGen/X86/pr29112.ll | 8 +- test/CodeGen/X86/pr29222.ll | 82 + test/CodeGen/X86/pr30430.ll | 6 +- test/CodeGen/X86/pr31956.ll | 2 +- test/CodeGen/X86/pr32282.ll | 35 +- test/CodeGen/X86/pr32284.ll | 25 +- test/CodeGen/X86/pr32329.ll | 2 +- test/CodeGen/X86/pr32345.ll | 14 +- test/CodeGen/X86/pr32484.ll | 4 +- test/CodeGen/X86/pr33349.ll | 30 +- test/CodeGen/X86/pr33747.ll | 29 + test/CodeGen/X86/pr33844.ll | 2 +- test/CodeGen/X86/pr33960.ll | 4 +- test/CodeGen/X86/pr34080-2.ll | 4 +- test/CodeGen/X86/pr34088.ll | 6 +- test/CodeGen/X86/pr34592.ll | 71 + test/CodeGen/X86/pr34605.ll | 2 +- test/CodeGen/X86/pr34653.ll | 8 +- test/CodeGen/X86/pr35272.ll | 3 +- test/CodeGen/X86/pr35316.ll | 76 + test/CodeGen/X86/pr35761.ll | 36 + test/CodeGen/X86/pr35763.ll | 42 + test/CodeGen/X86/pr35765.ll | 2 +- test/CodeGen/X86/pr35918.ll | 108 + test/CodeGen/X86/pr35972.ll | 20 + test/CodeGen/X86/pr35982.ll | 123 + test/CodeGen/X86/pr36199.ll | 22 + test/CodeGen/X86/pr36553.ll | 20 + test/CodeGen/X86/pr37563.ll | 42 - test/CodeGen/X86/pre-coalesce.mir | 28 +- test/CodeGen/X86/prefer-avx256-lzcnt.ll | 130 + test/CodeGen/X86/prefer-avx256-mask-extend.ll | 262 + test/CodeGen/X86/prefer-avx256-mask-shuffle.ll | 237 + test/CodeGen/X86/prefer-avx256-popcnt.ll | 105 + test/CodeGen/X86/prefer-avx256-shift.ll | 475 + test/CodeGen/X86/prefer-avx256-trunc.ll | 50 + test/CodeGen/X86/prefer-avx256-wide-mul.ll | 44 + test/CodeGen/X86/prologue-epilogue-remarks.mir | 6 + test/CodeGen/X86/promote-vec3.ll | 52 +- test/CodeGen/X86/promote.ll | 65 +- test/CodeGen/X86/psubus.ll | 1736 +- test/CodeGen/X86/ptest.ll | 323 + test/CodeGen/X86/push-cfi-obj.ll | 2 +- test/CodeGen/X86/ragreedy-hoist-spill.ll | 4 +- test/CodeGen/X86/rdpid-schedule.ll | 20 + test/CodeGen/X86/rdpid.ll | 21 + test/CodeGen/X86/rdpmc.ll | 28 +- test/CodeGen/X86/rdrand.ll | 30 +- test/CodeGen/X86/reduce-trunc-shl.ll | 2 +- test/CodeGen/X86/regalloc-advanced-split-cost.ll | 91 + test/CodeGen/X86/regparm.ll | 6 +- test/CodeGen/X86/remat-fold-load.ll | 6 +- test/CodeGen/X86/remat-phys-dead.ll | 4 +- test/CodeGen/X86/required-vector-width.ll | 655 + test/CodeGen/X86/retpoline-external.ll | 166 + test/CodeGen/X86/retpoline-regparm.ll | 42 + test/CodeGen/X86/retpoline.ll | 363 + test/CodeGen/X86/rounding-ops.ll | 20 +- test/CodeGen/X86/sad.ll | 855 +- test/CodeGen/X86/sad_variations.ll | 162 +- test/CodeGen/X86/safestack.ll | 8 + test/CodeGen/X86/safestack_inline.ll | 30 + test/CodeGen/X86/sar_fold64.ll | 8 +- test/CodeGen/X86/scalar-fp-to-i64.ll | 1720 +- test/CodeGen/X86/scalar-int-to-fp.ll | 14 +- test/CodeGen/X86/scalar_widen_div.ll | 34 +- test/CodeGen/X86/scavenger.mir | 30 +- test/CodeGen/X86/schedule-x86-64-shld.ll | 464 + test/CodeGen/X86/schedule-x86_32.ll | 42 +- test/CodeGen/X86/schedule-x86_64.ll | 120 +- test/CodeGen/X86/select-1-or-neg1.ll | 29 + test/CodeGen/X86/select.ll | 29 +- test/CodeGen/X86/select_const.ll | 12 +- test/CodeGen/X86/setcc-lowering.ll | 11 +- test/CodeGen/X86/sext-i1.ll | 9 +- test/CodeGen/X86/shift-combine.ll | 8 +- test/CodeGen/X86/shift-double.ll | 4 +- test/CodeGen/X86/shift-pair.ll | 11 +- test/CodeGen/X86/shrink-compare.ll | 4 +- test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll | 36 + test/CodeGen/X86/shrink-wrap-chkstk.ll | 2 +- test/CodeGen/X86/shrink_vmul.ll | 64 +- test/CodeGen/X86/shrink_wrap_dbg_value.mir | 182 + test/CodeGen/X86/shuffle-of-splat-multiuses.ll | 22 +- .../CodeGen/X86/shuffle-strided-with-offset-128.ll | 18 +- .../CodeGen/X86/shuffle-strided-with-offset-256.ll | 83 +- .../CodeGen/X86/shuffle-strided-with-offset-512.ll | 156 +- test/CodeGen/X86/shuffle-vs-trunc-128.ll | 15 +- test/CodeGen/X86/shuffle-vs-trunc-256.ll | 110 +- test/CodeGen/X86/shuffle-vs-trunc-512.ll | 363 +- .../X86/simple-register-allocation-read-undef.mir | 30 + test/CodeGen/X86/slow-pmulld.ll | 1320 +- test/CodeGen/X86/slow-unaligned-mem.ll | 4 +- test/CodeGen/X86/small-byval-memcpy.ll | 4 +- test/CodeGen/X86/split-extend-vector-inreg.ll | 12 +- test/CodeGen/X86/sqrt-fastmath-mir.ll | 12 +- test/CodeGen/X86/sqrt-fastmath.ll | 78 +- test/CodeGen/X86/sse-fsignum.ll | 52 +- test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 4 - test/CodeGen/X86/sse-scalar-fp-arith.ll | 18 +- test/CodeGen/X86/sse-schedule.ll | 175 +- test/CodeGen/X86/sse1.ll | 4 +- test/CodeGen/X86/sse2-intrinsics-x86.ll | 13 +- test/CodeGen/X86/sse2-schedule.ll | 90 +- test/CodeGen/X86/sse3-avx-addsub-2.ll | 4 +- test/CodeGen/X86/sse3.ll | 20 +- test/CodeGen/X86/sse41-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll | 2 +- test/CodeGen/X86/sse41-intrinsics-x86.ll | 10 +- test/CodeGen/X86/sse41-schedule.ll | 88 +- test/CodeGen/X86/sse41.ll | 8 +- test/CodeGen/X86/sse42-schedule.ll | 42 +- test/CodeGen/X86/sse4a-schedule.ll | 4 +- test/CodeGen/X86/stack-align.ll | 4 +- test/CodeGen/X86/stack-folding-fp-avx1.ll | 39 +- test/CodeGen/X86/stack-folding-fp-avx512.ll | 66 +- test/CodeGen/X86/stack-folding-fp-avx512vl.ll | 52 +- test/CodeGen/X86/stack-folding-fp-sse42.ll | 12 +- test/CodeGen/X86/stack-folding-int-avx512.ll | 70 +- test/CodeGen/X86/stack-folding-int-avx512vl.ll | 21 + test/CodeGen/X86/stack-folding-tbm.ll | 40 +- test/CodeGen/X86/stack-protector-weight.ll | 14 +- test/CodeGen/X86/stack-protector.ll | 6 +- test/CodeGen/X86/statepoint-call-lowering.ll | 21 + test/CodeGen/X86/statepoint-invoke.ll | 8 +- test/CodeGen/X86/statepoint-live-in.ll | 2 +- test/CodeGen/X86/statepoint-stack-usage.ll | 6 +- test/CodeGen/X86/statepoint-vector.ll | 97 +- test/CodeGen/X86/subvector-broadcast.ll | 112 +- test/CodeGen/X86/swift-return.ll | 455 +- test/CodeGen/X86/switch-edge-weight.ll | 44 +- test/CodeGen/X86/switch-jump-table.ll | 4 +- test/CodeGen/X86/switch-lower-peel-top-case.ll | 58 +- test/CodeGen/X86/tail-call-conditional.mir | 52 +- test/CodeGen/X86/tail-dup-debugloc.ll | 4 +- test/CodeGen/X86/tail-dup-merge-loop-headers.ll | 4 +- test/CodeGen/X86/tail-merge-after-mbp.mir | 60 +- test/CodeGen/X86/tail-merge-debugloc.ll | 2 +- test/CodeGen/X86/tailcall-mem-intrinsics.ll | 18 +- .../CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll | 2 +- test/CodeGen/X86/tbm-intrinsics-fast-isel.ll | 12 +- test/CodeGen/X86/tbm-intrinsics-x86_64.ll | 12 +- test/CodeGen/X86/tbm-schedule.ll | 160 +- test/CodeGen/X86/tbm_patterns.ll | 120 +- test/CodeGen/X86/test-shrink-bug.ll | 98 +- test/CodeGen/X86/test-shrink.ll | 126 +- test/CodeGen/X86/test-vs-bittest.ll | 377 + test/CodeGen/X86/testb-je-fusion.ll | 13 +- test/CodeGen/X86/tls-android-negative.ll | 3 + test/CodeGen/X86/tls-android.ll | 3 + test/CodeGen/X86/tlv-1.ll | 4 +- test/CodeGen/X86/trunc-store.ll | 1 - test/CodeGen/X86/trunc-subvector.ll | 253 + test/CodeGen/X86/umul-with-overflow.ll | 6 +- test/CodeGen/X86/unaligned-load.ll | 4 +- test/CodeGen/X86/undef-globals-bss.ll | 12 + test/CodeGen/X86/undef-ops.ll | 460 + test/CodeGen/X86/unreachable-mbb-undef-phi.mir | 38 + test/CodeGen/X86/unused_stackslots.ll | 18 +- test/CodeGen/X86/unwindraise.ll | 6 +- test/CodeGen/X86/update-terminator-debugloc.ll | 4 +- test/CodeGen/X86/update-terminator.mir | 22 +- test/CodeGen/X86/urem-i8-constant.ll | 3 +- test/CodeGen/X86/urem-power-of-two.ll | 16 +- test/CodeGen/X86/var-permute-128.ll | 638 +- test/CodeGen/X86/var-permute-256.ll | 2431 +- test/CodeGen/X86/variable-sized-darwin-bzero.ll | 4 +- test/CodeGen/X86/vastart-defs-eflags.ll | 38 +- test/CodeGen/X86/vec_cast.ll | 168 +- test/CodeGen/X86/vec_cast2.ll | 258 +- test/CodeGen/X86/vec_cast3.ll | 342 + test/CodeGen/X86/vec_cmp_sint-128.ll | 324 +- test/CodeGen/X86/vec_cmp_uint-128.ll | 497 +- test/CodeGen/X86/vec_extract-avx.ll | 32 +- test/CodeGen/X86/vec_floor.ll | 40 +- test/CodeGen/X86/vec_fp_to_int.ll | 128 +- test/CodeGen/X86/vec_ins_extract-1.ll | 8 +- test/CodeGen/X86/vec_insert-4.ll | 2 +- test/CodeGen/X86/vec_insert-5.ll | 2 +- test/CodeGen/X86/vec_insert-7.ll | 8 +- test/CodeGen/X86/vec_insert-8.ll | 4 +- test/CodeGen/X86/vec_insert-mmx.ll | 2 +- test/CodeGen/X86/vec_int_to_fp.ll | 190 +- test/CodeGen/X86/vec_minmax_match.ll | 11 +- test/CodeGen/X86/vec_minmax_sint.ll | 812 +- test/CodeGen/X86/vec_minmax_uint.ll | 959 +- test/CodeGen/X86/vec_setcc-2.ll | 137 +- test/CodeGen/X86/vec_shift4.ll | 8 +- test/CodeGen/X86/vec_ss_load_fold.ll | 53 +- test/CodeGen/X86/vector-bitreverse.ll | 16 +- test/CodeGen/X86/vector-blend.ll | 150 +- test/CodeGen/X86/vector-compare-all_of.ll | 113 +- test/CodeGen/X86/vector-compare-any_of.ll | 88 +- test/CodeGen/X86/vector-compare-results.ll | 9936 ++--- test/CodeGen/X86/vector-compare-simplify.ll | 356 + test/CodeGen/X86/vector-extend-inreg.ll | 36 +- test/CodeGen/X86/vector-half-conversions.ll | 439 +- test/CodeGen/X86/vector-idiv-sdiv-128.ll | 10 +- test/CodeGen/X86/vector-idiv-sdiv-512.ll | 4 +- test/CodeGen/X86/vector-idiv-udiv-128.ll | 2 +- test/CodeGen/X86/vector-idiv-udiv-512.ll | 4 +- test/CodeGen/X86/vector-lzcnt-128.ll | 16 +- test/CodeGen/X86/vector-lzcnt-256.ll | 16 +- test/CodeGen/X86/vector-lzcnt-512.ll | 30 +- test/CodeGen/X86/vector-mul.ll | 8 +- test/CodeGen/X86/vector-popcnt-128.ll | 18 +- test/CodeGen/X86/vector-popcnt-256.ll | 16 +- test/CodeGen/X86/vector-rotate-128.ll | 54 +- test/CodeGen/X86/vector-rotate-256.ll | 38 +- test/CodeGen/X86/vector-rotate-512.ll | 4 +- test/CodeGen/X86/vector-sext.ll | 284 +- test/CodeGen/X86/vector-shift-ashr-128.ll | 40 +- test/CodeGen/X86/vector-shift-ashr-256.ll | 28 +- test/CodeGen/X86/vector-shift-ashr-512.ll | 5 +- test/CodeGen/X86/vector-shift-lshr-128.ll | 32 +- test/CodeGen/X86/vector-shift-lshr-256.ll | 10 +- test/CodeGen/X86/vector-shift-lshr-512.ll | 2 +- test/CodeGen/X86/vector-shift-shl-128.ll | 34 +- test/CodeGen/X86/vector-shift-shl-256.ll | 10 +- test/CodeGen/X86/vector-shuffle-128-v2.ll | 175 +- test/CodeGen/X86/vector-shuffle-128-v4.ll | 299 +- test/CodeGen/X86/vector-shuffle-128-v8.ll | 15 +- test/CodeGen/X86/vector-shuffle-256-v16.ll | 31 +- test/CodeGen/X86/vector-shuffle-256-v32.ll | 36 +- test/CodeGen/X86/vector-shuffle-256-v4.ll | 256 +- test/CodeGen/X86/vector-shuffle-256-v8.ll | 334 +- test/CodeGen/X86/vector-shuffle-512-v16.ll | 28 +- test/CodeGen/X86/vector-shuffle-512-v8.ll | 52 +- test/CodeGen/X86/vector-shuffle-avx512.ll | 176 +- test/CodeGen/X86/vector-shuffle-combining-avx.ll | 10 +- test/CodeGen/X86/vector-shuffle-combining-avx2.ll | 92 +- .../X86/vector-shuffle-combining-avx512bw.ll | 12 +- test/CodeGen/X86/vector-shuffle-combining-ssse3.ll | 6 +- test/CodeGen/X86/vector-shuffle-combining-xop.ll | 49 +- test/CodeGen/X86/vector-shuffle-combining.ll | 337 +- test/CodeGen/X86/vector-shuffle-masked.ll | 218 +- test/CodeGen/X86/vector-shuffle-mmx.ll | 66 +- test/CodeGen/X86/vector-shuffle-sse1.ll | 4 - test/CodeGen/X86/vector-shuffle-v1.ll | 411 +- test/CodeGen/X86/vector-shuffle-variable-128.ll | 228 +- test/CodeGen/X86/vector-shuffle-variable-256.ll | 72 +- test/CodeGen/X86/vector-trunc-math.ll | 1820 +- test/CodeGen/X86/vector-trunc-packus.ll | 3264 ++ test/CodeGen/X86/vector-trunc-ssat.ll | 3197 ++ test/CodeGen/X86/vector-trunc-usat.ll | 2459 ++ test/CodeGen/X86/vector-trunc.ll | 436 +- test/CodeGen/X86/vector-tzcnt-128.ll | 20 +- test/CodeGen/X86/vector-tzcnt-256.ll | 16 +- test/CodeGen/X86/vector-zext.ll | 31 +- test/CodeGen/X86/vectorcall.ll | 12 +- test/CodeGen/X86/verifier-phi-fail0.mir | 2 +- test/CodeGen/X86/verifier-phi.mir | 4 +- ...gisters-cleared-in-machine-functions-liveins.ll | 8 +- test/CodeGen/X86/vmaskmov-offset.ll | 42 + test/CodeGen/X86/vpshufbitqbm-intrinsics.ll | 2 +- test/CodeGen/X86/vselect-2.ll | 38 +- test/CodeGen/X86/vselect-minmax.ll | 7836 ++-- test/CodeGen/X86/vselect-packss.ll | 43 +- test/CodeGen/X86/vselect-pcmp.ll | 158 +- test/CodeGen/X86/vselect.ll | 185 +- test/CodeGen/X86/widen_bitops-0.ll | 36 +- test/CodeGen/X86/widen_conv-1.ll | 3 +- test/CodeGen/X86/widen_conv-3.ll | 2 +- test/CodeGen/X86/widen_conv-4.ll | 4 +- test/CodeGen/X86/widen_load-2.ll | 12 +- test/CodeGen/X86/widened-broadcast.ll | 92 + test/CodeGen/X86/win64_frame.ll | 375 +- test/CodeGen/X86/x86-64-baseptr.ll | 55 +- test/CodeGen/X86/x86-64-bittest-logic.ll | 242 + .../X86/x86-64-double-precision-shift-left.ll | 44 +- .../X86/x86-64-double-precision-shift-right.ll | 48 +- test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll | 25 +- test/CodeGen/X86/x86-64-psub.ll | 164 +- test/CodeGen/X86/x86-64-static-relo-movl.ll | 4 +- test/CodeGen/X86/x86-cmov-converter.ll | 2 +- test/CodeGen/X86/x86-interleaved-access.ll | 349 +- test/CodeGen/X86/x86-interrupt_cc.ll | 733 +- test/CodeGen/X86/x86-repmov-copy-eflags.ll | 4 +- test/CodeGen/X86/x86-shrink-wrap-unwind.ll | 6 +- test/CodeGen/X86/x86-shrink-wrapping.ll | 9 +- test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll | 2 +- test/CodeGen/X86/xor-combine-debugloc.ll | 10 +- test/CodeGen/X86/xor-icmp.ll | 4 +- test/CodeGen/X86/xor.ll | 550 +- test/CodeGen/X86/xray-empty-firstmbb.mir | 4 +- test/CodeGen/X86/xray-empty-function.mir | 2 +- test/CodeGen/X86/xray-multiplerets-in-blocks.mir | 4 +- test/CodeGen/X86/zext-demanded.ll | 140 + test/CodeGen/X86/zext-fold.ll | 40 +- test/CodeGen/XCore/byVal.ll | 6 +- test/CodeGen/XCore/exception.ll | 24 +- test/CodeGen/XCore/memcpy.ll | 8 +- test/DebugInfo/AArch64/asan-stack-vars.ll | 6 +- test/DebugInfo/AArch64/frameindices.ll | 10 +- test/DebugInfo/AMDGPU/code-pointer-size.ll | 22 +- test/DebugInfo/AMDGPU/dwarfdump-relocs.ll | 26 +- test/DebugInfo/AMDGPU/pointer-address-space.ll | 40 +- test/DebugInfo/AMDGPU/variable-locations.ll | 30 +- test/DebugInfo/ARM/PR16736.ll | 2 +- test/DebugInfo/ARM/PR26163.ll | 16 +- test/DebugInfo/ARM/partial-subreg.ll | 2 +- test/DebugInfo/ARM/sdag-split-arg.ll | 4 +- test/DebugInfo/ARM/sdag-split-arg1.ll | 2 +- test/DebugInfo/COFF/const-unnamed-member.ll | 61 + test/DebugInfo/COFF/enum.ll | 11 + test/DebugInfo/COFF/fpo-csrs.ll | 20 +- test/DebugInfo/COFF/fpo-shrink-wrap.ll | 2 +- test/DebugInfo/COFF/local-variable-gap.ll | 6 +- test/DebugInfo/COFF/long-name.ll | 17 +- test/DebugInfo/COFF/nested-types.ll | 2 +- test/DebugInfo/COFF/pieces.ll | 18 +- test/DebugInfo/COFF/register-variables.ll | 22 +- test/DebugInfo/COFF/type-quals.ll | 573 + test/DebugInfo/COFF/types-array.ll | 8 +- test/DebugInfo/COFF/types-cvarargs.ll | 117 + test/DebugInfo/COFF/types-data-members.ll | 2 +- test/DebugInfo/COFF/vftables.ll | 6 +- test/DebugInfo/Generic/2010-10-01-crash.ll | 2 +- .../Generic/accel-table-hash-collisions.ll | 40 +- test/DebugInfo/Generic/cross-cu-inlining.ll | 6 +- test/DebugInfo/Generic/debug-info-enum.ll | 203 + test/DebugInfo/Generic/discriminated-union.ll | 80 + test/DebugInfo/Generic/disubrange_vla.ll | 50 + .../Generic/disubrange_vla_no_dbgvalue.ll | 48 + test/DebugInfo/Generic/empty.ll | 2 + test/DebugInfo/Generic/global-sra-struct.ll | 2 +- test/DebugInfo/Generic/inlined-strings.ll | 45 + test/DebugInfo/Generic/lto-comp-dir.ll | 8 +- test/DebugInfo/Generic/string-offsets-form.ll | 293 + .../Generic/univariant-discriminated-union.ll | 65 + .../Inputs/split-dwarf-no-skel-address.dwo | Bin 0 -> 968 bytes .../DebugInfo/Inputs/split-dwarf-no-skel-address.o | Bin 0 -> 2904 bytes test/DebugInfo/MIR/AArch64/clobber-sp.mir | 94 +- .../MIR/AArch64/implicit-def-dead-scope.mir | 78 +- test/DebugInfo/MIR/ARM/split-superreg-complex.mir | 52 +- test/DebugInfo/MIR/ARM/split-superreg-piece.mir | 72 +- test/DebugInfo/MIR/ARM/split-superreg.mir | 72 +- test/DebugInfo/MIR/Mips/last-inst-bundled.mir | 188 + test/{CodeGen => DebugInfo/MIR}/Mips/lit.local.cfg | 0 test/DebugInfo/MIR/X86/bit-piece-dh.mir | 22 +- test/DebugInfo/MIR/X86/empty-inline.mir | 26 +- test/DebugInfo/MIR/X86/kill-after-spill.mir | 388 + .../DebugInfo/MIR/X86/live-debug-values-3preds.mir | 142 +- test/DebugInfo/MIR/X86/live-debug-values-spill.mir | 242 +- test/DebugInfo/MIR/X86/live-debug-values.mir | 102 +- .../X86/live-debug-vars-unused-arg-debugonly.mir | 30 +- .../MIR/X86/live-debug-vars-unused-arg.mir | 32 +- test/DebugInfo/MIR/X86/livedebugvalues-limit.mir | 108 +- test/DebugInfo/MIR/X86/mlicm-hoist.mir | 14 +- test/DebugInfo/MIR/X86/no-cfi-loc.mir | 14 +- test/DebugInfo/MIR/X86/regcoalescer.mir | 10 +- test/DebugInfo/MSP430/sdagsplit-1.ll | 8 +- test/DebugInfo/Mips/dsr-fixed-objects.ll | 8 +- test/DebugInfo/Sparc/subreg.ll | 2 +- test/DebugInfo/X86/DW_AT_location-reference.ll | 10 +- test/DebugInfo/X86/PR26148.ll | 6 +- test/DebugInfo/X86/accel-tables.ll | 49 + test/DebugInfo/X86/array.ll | 4 +- test/DebugInfo/X86/array2.ll | 4 +- test/DebugInfo/X86/bbjoin.ll | 10 +- test/DebugInfo/X86/constant-loclist.ll | 10 +- test/DebugInfo/X86/dbg-addr-dse.ll | 4 +- test/DebugInfo/X86/dbg-addr.ll | 4 +- test/DebugInfo/X86/dbg-declare-arg.ll | 6 +- test/DebugInfo/X86/dbg-value-const-byref.ll | 8 +- test/DebugInfo/X86/dbg-value-dag-combine.ll | 4 +- test/DebugInfo/X86/dbg-value-frame-index.ll | 4 +- test/DebugInfo/X86/dbg-value-inlined-parameter.ll | 6 +- test/DebugInfo/X86/dbg-value-regmask-clobber.ll | 4 +- test/DebugInfo/X86/dbg-value-transfer-order.ll | 2 +- test/DebugInfo/X86/debug-loc-asan.ll | 6 +- test/DebugInfo/X86/debug-loc-frame.ll | 4 +- test/DebugInfo/X86/debug-loc-offset.ll | 16 +- test/DebugInfo/X86/debug-macro.ll | 11 +- test/DebugInfo/X86/debug-ranges-offset.ll | 2 +- test/DebugInfo/X86/debugger-tune.ll | 66 +- test/DebugInfo/X86/dw_op_minus_direct.ll | 2 +- test/DebugInfo/X86/dwarfdump-debug-loc-simple.test | 16 +- test/DebugInfo/X86/dwarfdump-debug-names.s | 176 + test/DebugInfo/X86/dwarfdump-header-64.s | 20 +- test/DebugInfo/X86/dwarfdump-header.s | 69 +- test/DebugInfo/X86/dwarfdump-line-dwo.s | 10 +- test/DebugInfo/X86/dwarfdump-line-only.s | 41 +- test/DebugInfo/X86/dwarfdump-ranges-baseaddr-exe.s | 8 +- test/DebugInfo/X86/dwarfdump-ranges-baseaddr.s | 10 +- test/DebugInfo/X86/dwarfdump-ranges-unrelocated.s | 16 +- test/DebugInfo/X86/empty_macinfo.ll | 24 + test/DebugInfo/X86/enum-class.ll | 6 +- test/DebugInfo/X86/float_const_loclist.ll | 4 +- test/DebugInfo/X86/fragment-offset-order.ll | 62 + test/DebugInfo/X86/generate-odr-hash.ll | 12 +- test/DebugInfo/X86/global-sra-fp80-array.ll | 129 + test/DebugInfo/X86/global-sra-fp80-struct.ll | 134 + test/DebugInfo/X86/inlined-formal-parameter.ll | 2 +- test/DebugInfo/X86/invalid-prologue-end.ll | 92 + test/DebugInfo/X86/linear-dbg-value.ll | 70 + test/DebugInfo/X86/live-debug-values.ll | 2 +- test/DebugInfo/X86/live-debug-variables.ll | 6 +- .../X86/live-debug-vars-discard-invalid.mir | 141 + test/DebugInfo/X86/live-debug-vars-dse.mir | 28 +- test/DebugInfo/X86/op_deref.ll | 2 +- test/DebugInfo/X86/pieces-1.ll | 4 +- test/DebugInfo/X86/pieces-2.ll | 4 +- test/DebugInfo/X86/pieces-3.ll | 6 +- test/DebugInfo/X86/pieces-4.ll | 2 +- test/DebugInfo/X86/pr34545.ll | 18 +- test/DebugInfo/X86/safestack-byval.ll | 4 +- test/DebugInfo/X86/sdag-combine.ll | 46 + test/DebugInfo/X86/sdag-salvage-add.ll | 6 +- test/DebugInfo/X86/sdag-split-arg.ll | 10 +- test/DebugInfo/X86/sdagsplit-1.ll | 4 +- test/DebugInfo/X86/spill-indirect-nrvo.ll | 4 +- test/DebugInfo/X86/spill-nontrivial-param.ll | 4 +- test/DebugInfo/X86/spill-nospill.ll | 14 +- .../X86/split-dwarf-cross-unit-reference.ll | 6 +- test/DebugInfo/X86/sret.ll | 6 +- test/DebugInfo/X86/sroasplit-1.ll | 4 +- test/DebugInfo/X86/sroasplit-2.ll | 7 +- test/DebugInfo/X86/sroasplit-4.ll | 6 +- test/DebugInfo/X86/sroasplit-5.ll | 8 +- test/DebugInfo/X86/sroasplit-dbg-declare.ll | 4 +- test/DebugInfo/X86/stack-value-piece.ll | 10 +- .../X86/stmt-list-multiple-compile-units.ll | 16 +- test/DebugInfo/X86/string-offsets-multiple-cus.ll | 157 + test/DebugInfo/X86/string-offsets-table.ll | 123 + test/DebugInfo/X86/strip-broken-debuginfo.ll | 22 + test/DebugInfo/X86/subregisters.ll | 2 +- test/DebugInfo/X86/vla-dependencies.ll | 101 + test/DebugInfo/X86/vla-global.ll | 65 + test/DebugInfo/X86/vla-multi.ll | 136 + test/DebugInfo/X86/vla.ll | 2 +- test/DebugInfo/debugify.ll | 20 + test/DebugInfo/debugmacinfo.test | 12 +- test/DebugInfo/dwarfdump-accel.test | 59 +- test/DebugInfo/dwarfdump-ranges.test | 8 +- .../llvm-symbolizer-split-dwarf-empty.test | 1 - ...lvm-symbolizer-split-dwarf-no-skel-address.test | 19 + test/ExecutionEngine/MCJIT/eh-lg-pic.ll | 1 + test/ExecutionEngine/MCJIT/eh.ll | 1 + test/ExecutionEngine/MCJIT/multi-module-eh-a.ll | 1 + test/ExecutionEngine/MCJIT/remote/eh.ll | 1 + test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll | 1 + test/ExecutionEngine/OrcMCJIT/eh.ll | 1 + test/ExecutionEngine/OrcMCJIT/multi-module-eh-a.ll | 1 + test/ExecutionEngine/OrcMCJIT/remote/eh.ll | 1 + .../RuntimeDyld/AArch64/MachO_ARM64_relocations.s | 9 + .../RuntimeDyld/X86/COFF_x86_64_IMGREL.s | 26 + test/Feature/elf-linker-options.ll | 17 + test/FileCheck/check-empty2.txt | 4 + test/Instrumentation/AddressSanitizer/basic.ll | 12 +- .../AddressSanitizer/stack-poisoning-byval-args.ll | 4 +- .../custom_fun_callback_attributes.ll | 37 + .../custom_fun_varargs_attributes.ll | 27 + test/Instrumentation/DataFlowSanitizer/memset.ll | 4 +- .../EfficiencySanitizer/working_set_basic.ll | 12 +- .../EfficiencySanitizer/working_set_slow.ll | 12 +- test/Instrumentation/HWAddressSanitizer/alloca.ll | 52 + test/Instrumentation/HWAddressSanitizer/atomic.ll | 4 +- test/Instrumentation/HWAddressSanitizer/basic.ll | 52 +- .../HWAddressSanitizer/kernel-alloca.ll | 29 + .../HWAddressSanitizer/kernel-inline.ll | 28 + test/Instrumentation/HWAddressSanitizer/kernel.ll | 42 + .../HWAddressSanitizer/with-calls.ll | 8 +- test/Instrumentation/InstrProfiling/early-exit.ll | 15 + test/Instrumentation/InstrProfiling/linkage.ll | 6 +- test/Instrumentation/InstrProfiling/no-counters.ll | 14 +- test/Instrumentation/InstrProfiling/profiling.ll | 3 +- .../MemorySanitizer/AArch64/vararg.ll | 6 +- .../MemorySanitizer/Mips/vararg-mips64.ll | 2 +- .../MemorySanitizer/Mips/vararg-mips64el.ll | 2 +- .../MemorySanitizer/PowerPC/vararg-ppc64.ll | 6 +- .../MemorySanitizer/PowerPC/vararg-ppc64le.ll | 6 +- test/Instrumentation/MemorySanitizer/alloca.ll | 8 +- .../MemorySanitizer/byval-alignment.ll | 2 +- .../MemorySanitizer/check_access_address.ll | 4 +- test/Instrumentation/MemorySanitizer/msan_basic.ll | 18 +- test/Instrumentation/ThreadSanitizer/tsan_basic.ll | 12 +- test/LTO/Resolution/X86/Inputs/not-prevailing.ll | 6 + test/LTO/Resolution/X86/cache-dso-local.ll | 22 + test/LTO/Resolution/X86/cache-dso-local2.ll | 23 + test/LTO/Resolution/X86/cache-prevailing.ll | 18 + test/LTO/Resolution/X86/comdat.ll | 2 +- test/LTO/Resolution/X86/not-prevailing-alias.ll | 43 + .../LTO/Resolution/X86/not-prevailing-variables.ll | 35 + test/LTO/Resolution/X86/not-prevailing.ll | 38 + test/LTO/Resolution/X86/setting-dso-local.ll | 15 + test/LTO/X86/Inputs/remangle_intrinsics.ll | 4 +- .../X86/diagnostic-handler-remarks-with-hotness.ll | 15 + test/LTO/X86/remangle_intrinsics.ll | 7 +- test/Linker/Inputs/metadata-source-a.ll | 22 + test/Linker/Inputs/metadata-source-b.ll | 22 + test/Linker/metadata-source.ll | 4 + test/Linker/subprogram-linkonce-weak.ll | 12 +- test/Linker/type-unique-dst-types.ll | 6 +- test/Linker/type-unique-simple2-a.ll | 4 +- test/Linker/type-unique-type-array-a.ll | 4 +- test/Linker/type-unique-type-array-b.ll | 4 +- test/MC/AArch64/SVE/add-diagnostics.s | 58 + test/MC/AArch64/SVE/add.s | 96 + test/MC/AArch64/SVE/addpl-diagnostics.s | 13 + test/MC/AArch64/SVE/addpl.s | 32 + test/MC/AArch64/SVE/addvl-diagnostics.s | 13 + test/MC/AArch64/SVE/addvl.s | 32 + test/MC/AArch64/SVE/and-diagnostics.s | 52 + test/MC/AArch64/SVE/and.s | 56 + test/MC/AArch64/SVE/dup-diagnostics.s | 19 + test/MC/AArch64/SVE/dup.s | 56 + test/MC/AArch64/SVE/mov-diagnostics.s | 19 + test/MC/AArch64/SVE/mov.s | 56 + test/MC/AArch64/SVE/ptrue-diagnostics.s | 29 + test/MC/AArch64/SVE/ptrue.s | 264 + test/MC/AArch64/SVE/ptrues-diagnostics.s | 29 + test/MC/AArch64/SVE/ptrues.s | 264 + test/MC/AArch64/SVE/rdvl-diagnostics.s | 13 + test/MC/AArch64/SVE/rdvl.s | 32 + test/MC/AArch64/SVE/sub-diagnostics.s | 58 + test/MC/AArch64/SVE/sub.s | 96 + test/MC/AArch64/coff-debug.ll | 6 +- test/MC/AArch64/coff-relocations.s | 13 + test/MC/AArch64/csdb.s | 4 + test/MC/AArch64/gicv3-regs.s | 4 +- test/MC/AMDGPU/buf-fmt-d16-packed.s | 74 + test/MC/AMDGPU/buf-fmt-d16-unpacked.s | 73 + test/MC/AMDGPU/hsa_isa_version_attrs.s | 6 + test/MC/AMDGPU/isa-version-hsa.s | 18 +- test/MC/AMDGPU/isa-version-pal.s | 18 +- test/MC/AMDGPU/isa-version-unk.s | 18 +- test/MC/AMDGPU/mimg-err.s | 60 + test/MC/AMDGPU/mimg.s | 241 +- test/MC/AMDGPU/mubuf.s | 72 +- test/MC/AMDGPU/sopk-err.s | 10 +- test/MC/AMDGPU/sopk.s | 87 +- test/MC/AMDGPU/sym_option.s | 2 +- test/MC/AMDGPU/vop_sdwa.s | 269 +- test/MC/AMDGPU/xnack-mask.s | 30 + test/MC/ARM/csdb-errors.s | 6 + test/MC/ARM/csdb.s | 8 + test/MC/ARM/diagnostics.s | 7 + test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s | 4 +- test/MC/ARM/dwarf-asm-multiple-sections.s | 15 +- test/MC/ARM/dwarf-asm-nonstandard-section.s | 2 +- test/MC/ARM/dwarf-asm-single-section.s | 2 +- test/MC/ARM/thumbv8m.s | 6 + test/MC/ARM/type-directive-print.ll | 17 + test/MC/ARM/vfp4.s | 4 +- test/MC/ARM/vmov-pair-diags.s | 6 + test/MC/AsmParser/debug-empty-source.s | 5 + test/MC/AsmParser/debug-no-source.s | 5 + test/MC/AsmParser/include.ll | 2 +- test/MC/AsmParser/inline_macro_duplication.ll | 8 + .../AsmParser/macro-duplicate-params-names-err.s | 1 + test/MC/AsmParser/preserve-comments-crlf.s | 1 + test/MC/BPF/insn-unit-32.s | 1 + test/MC/BPF/insn-unit.s | 21 +- test/MC/BPF/load-store-32.s | 25 + test/MC/COFF/cv-inline-linetable.s | 26 + test/MC/COFF/symidx.s | 15 + test/MC/Disassembler/AArch64/csdb.txt | 4 + test/MC/Disassembler/AArch64/gicv3-regs.txt | 2 +- test/MC/Disassembler/AMDGPU/buf_fmt_packed_d16.txt | 50 + .../Disassembler/AMDGPU/buf_fmt_unpacked_d16.txt | 50 + test/MC/Disassembler/AMDGPU/mimg_vi.txt | 120 +- test/MC/Disassembler/AMDGPU/mubuf_vi.txt | 43 + test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt | 100 + test/MC/Disassembler/AMDGPU/sop1_vi.txt | 11 +- test/MC/Disassembler/AMDGPU/vop3_gfx9.txt | 6 + test/MC/Disassembler/ARM/csdb-arm.txt | 4 + test/MC/Disassembler/ARM/csdb-thumb.txt | 4 + test/MC/Disassembler/ARM/invalid-armv7.txt | 18 +- .../Disassembler/ARM/invalid-thumb-MSR-MClass.txt | 8 +- test/MC/Disassembler/ARM/invalid-thumbv7.txt | 17 +- test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt | 38 + .../Disassembler/Mips/micromips32r3/valid-el.txt | 16 + .../Mips/micromips32r3/valid-fp64-el.txt | 19 + .../Disassembler/Mips/micromips32r3/valid-fp64.txt | 19 + test/MC/Disassembler/Mips/micromips32r3/valid.txt | 16 + test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt | 17 + test/MC/Disassembler/Mips/mips32/valid-fp64.txt | 17 + .../Disassembler/Mips/mips32r2/valid-fp64-el.txt | 19 + test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt | 19 + .../Disassembler/Mips/mips32r3/valid-fp64-el.txt | 19 + test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt | 19 + .../Disassembler/Mips/mips32r5/valid-fp64-el.txt | 19 + test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt | 19 + test/MC/Disassembler/PowerPC/vsx.txt | 15 - test/MC/Disassembler/X86/amd3dnow.txt | 79 + test/MC/Disassembler/X86/simple-tests.txt | 4 +- test/MC/Disassembler/X86/x86-16.txt | 4 +- test/MC/ELF/basic-elf-64.s | 18 +- test/MC/ELF/debug-file-options.s | 36 + test/MC/ELF/debug-md5-err.s | 26 + test/MC/ELF/debug-md5.s | 30 + test/MC/ELF/debug-source.s | 32 + test/MC/ELF/div-by-zero.s | 3 + test/MC/ELF/gen-dwarf.s | 2 +- test/MC/ELF/ifunc-reloc.s | 2 +- test/MC/ELF/section.s | 14 + test/MC/ELF/uleb-ehtable.s | 28 + test/MC/ELF/weak-diff.s | 2 +- test/MC/ELF/weak-relocation.s | 2 +- test/MC/ELF/weakref-reloc.s | 2 +- test/MC/Hexagon/J2_trap1_dep.s | 6 + test/MC/Hexagon/guest.s | 67 + test/MC/Hexagon/inst_select.ll | 8 +- test/MC/Hexagon/instructions/system_user.s | 8 +- test/MC/MachO/gen-dwarf-cpp.s | 18 +- test/MC/MachO/gen-dwarf-macro-cpp.s | 10 +- test/MC/MachO/gen-dwarf.s | 6 +- test/MC/MachO/x86_32-optimal_nop.s | 12 +- test/MC/Mips/micromips-fpu-instructions.s | 6 +- test/MC/Mips/micromips/valid-fp64.s | 35 + test/MC/Mips/micromips/valid.s | 30 +- test/MC/Mips/micromips32r6/valid.s | 26 +- test/MC/Mips/mips-fpu-instructions.s | 6 +- test/MC/Mips/mips1/valid.s | 38 +- test/MC/Mips/mips2/valid.s | 44 +- test/MC/Mips/mips32/valid.s | 44 +- test/MC/Mips/mips32r2/valid-fp64.s | 35 + test/MC/Mips/mips32r2/valid.s | 50 +- test/MC/Mips/mips32r3/valid-fp64.s | 35 + test/MC/Mips/mips32r3/valid.s | 50 +- test/MC/Mips/mips32r5/valid-fp64.s | 35 + test/MC/Mips/mips32r5/valid.s | 50 +- test/MC/Mips/unsupported-relocation.s | 13 + test/MC/PowerPC/vsx.s | 19 +- test/MC/RISCV/cnop.s | 26 + test/MC/RISCV/csr-aliases.s | 117 + test/MC/RISCV/elf-flags.s | 13 + test/MC/RISCV/fixups-compressed.s | 11 +- test/MC/RISCV/relocations.s | 26 +- test/MC/RISCV/rv32-relaxation.s | 75 + test/MC/RISCV/rv32c-invalid.s | 21 +- test/MC/RISCV/rv32c-only-valid.s | 9 +- test/MC/RISCV/rv32c-valid.s | 14 +- test/MC/RISCV/rv32dc-valid.s | 12 +- test/MC/RISCV/rv32fc-valid.s | 16 +- test/MC/RISCV/rv32i-invalid.s | 9 + test/MC/RISCV/rv64-relaxation.s | 64 + test/MC/RISCV/rv64c-valid.s | 16 +- test/MC/RISCV/rv64dc-valid.s | 29 + test/MC/WebAssembly/array-fill.ll | 9 +- test/MC/WebAssembly/blockaddress.ll | 15 + test/MC/WebAssembly/bss.ll | 86 +- test/MC/WebAssembly/comdat.ll | 121 + test/MC/WebAssembly/custom-code-section.ll | 4 +- test/MC/WebAssembly/debug-info.ll | 4 +- test/MC/WebAssembly/explicit-sections.ll | 73 +- test/MC/WebAssembly/external-data.ll | 9 +- test/MC/WebAssembly/external-func-address.ll | 18 +- test/MC/WebAssembly/func-address.ll | 12 +- test/MC/WebAssembly/global-ctor-dtor.ll | 183 + test/MC/WebAssembly/init-fini-array.ll | 178 - test/MC/WebAssembly/libcall.ll | 30 + test/MC/WebAssembly/reloc-code.ll | 14 +- test/MC/WebAssembly/reloc-data.ll | 17 +- test/MC/WebAssembly/sections.ll | 15 +- test/MC/WebAssembly/stack-ptr.ll | 4 +- test/MC/WebAssembly/unnamed-data.ll | 69 +- test/MC/WebAssembly/visibility.ll | 19 +- test/MC/WebAssembly/weak-alias.ll | 202 +- test/MC/WebAssembly/weak.ll | 26 +- test/MC/X86/AVX512F_512-32.s | 34842 ++++++++++++++++++ test/MC/X86/AVX512F_512-64.s | 35806 +++++++++++++++++++ test/MC/X86/AlignedBundling/long-nop-pad.s | 10 +- .../X86/AlignedBundling/misaligned-bundle-group.s | 4 +- test/MC/X86/AlignedBundling/misaligned-bundle.s | 2 +- test/MC/X86/AlignedBundling/pad-bundle-groups.s | 3 +- test/MC/X86/CET-32.s | 122 + test/MC/X86/CET-64.s | 178 + test/MC/X86/CLWB-32.s | 26 + test/MC/X86/CLWB-64.s | 26 + test/MC/X86/CLZERO-32.s | 6 + test/MC/X86/CLZERO-64.s | 6 + test/MC/X86/F16C-32.s | 114 + test/MC/X86/F16C-64.s | 114 + test/MC/X86/FXSAVE-32.s | 50 + test/MC/X86/FXSAVE-64.s | 50 + test/MC/X86/FXSAVE64-64.s | 50 + test/MC/X86/I186-32.s | 666 + test/MC/X86/I186-64.s | 846 + test/MC/X86/I286-32.s | 266 + test/MC/X86/I286-64.s | 406 + test/MC/X86/I386-32.s | 682 + test/MC/X86/I386-64.s | 874 + test/MC/X86/I486-32.s | 102 + test/MC/X86/I486-64.s | 166 + test/MC/X86/I86-32.s | 3530 ++ test/MC/X86/I86-64.s | 4846 +++ test/MC/X86/INVPCID-32.s | 26 + test/MC/X86/INVPCID-64.s | 26 + test/MC/X86/MMX-32.s | 1730 + test/MC/X86/MMX-64.s | 1754 + test/MC/X86/PKU-32.s | 10 + test/MC/X86/PKU-64.s | 10 + test/MC/X86/POPCNT-32.s | 34 + test/MC/X86/POPCNT-64.s | 50 + test/MC/X86/PPRO-32.s | 126 + test/MC/X86/PPRO-64.s | 130 + test/MC/X86/RTM.s | 18 + test/MC/X86/SGX-32.s | 10 + test/MC/X86/SGX-64.s | 10 + test/MC/X86/SHA-32.s | 202 + test/MC/X86/SHA-64.s | 394 + test/MC/X86/SVM-32.s | 34 + test/MC/X86/SVM-64.s | 34 + test/MC/X86/VMFUNC-32.s | 6 + test/MC/X86/VMFUNC-64.s | 6 + test/MC/X86/VTX-32.s | 222 + test/MC/X86/VTX-64.s | 218 + test/MC/X86/X86_64-pku.s | 4 +- test/MC/X86/XSAVE-32.s | 58 + test/MC/X86/XSAVE-64.s | 106 + test/MC/X86/XSAVEC-32.s | 26 + test/MC/X86/XSAVEC-64.s | 50 + test/MC/X86/XSAVEOPT-32.s | 26 + test/MC/X86/XSAVEOPT-64.s | 50 + test/MC/X86/XSAVES-32.s | 50 + test/MC/X86/XSAVES-64.s | 98 + test/MC/X86/avx512-encodings.s | 2 +- test/MC/X86/avx512-err.s | 2 +- test/MC/X86/avx512bitalg-encoding.s | 2 +- test/MC/X86/avx512bw-encoding.s | 2 +- test/MC/X86/avx512gfni-encoding.s | 2 +- test/MC/X86/avx512ifma-encoding.s | 2 +- test/MC/X86/avx512ifmavl-encoding.s | 2 +- test/MC/X86/avx512vaes-encoding.s | 2 +- test/MC/X86/avx512vbmi-encoding.s | 2 +- test/MC/X86/avx512vbmi2-encoding.s | 2 +- test/MC/X86/avx512vbmi2vl-encoding.s | 2 +- test/MC/X86/avx512vl-encoding.s | 2 +- test/MC/X86/avx512vl_bitalg-encoding.s | 2 +- test/MC/X86/avx512vl_gfni-encoding.s | 2 +- test/MC/X86/avx512vl_vaes-encoding.s | 2 +- test/MC/X86/avx512vl_vnni-encoding.s | 2 +- test/MC/X86/avx512vlvpclmul.s | 2 +- test/MC/X86/avx512vnni-encoding.s | 2 +- test/MC/X86/avx512vpclmul.s | 2 +- test/MC/X86/avx_vaes-encoding.s | 2 +- test/MC/X86/cet-encoding.s | 10 +- test/MC/X86/cfi-scope-unclosed.s | 10 + test/MC/X86/check-end-of-data-region.s | 8 + test/MC/X86/crlf.test | 2 +- test/MC/X86/eval-fill.s | 17 + test/MC/X86/gather.s | 2 +- test/MC/X86/gfni-encoding.s | 2 +- test/MC/X86/intel-syntax-avx512-error.s | 2 +- test/MC/X86/intel-syntax-avx512.s | 2 +- test/MC/X86/intel-syntax-unsized-memory.s | 2 +- test/MC/X86/intel-syntax-x86-64-avx512f_vl.s | 2 +- test/MC/X86/intel-syntax-x86-avx512dq_vl.s | 3 +- test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s | 2 +- test/MC/X86/intel-syntax.s | 8 + test/MC/X86/mpx-encodings.s | 6 +- test/MC/X86/space-err.s | 4 + test/MC/X86/vpclmulqdq.s | 2 +- test/MC/X86/x86-16.s | 8 +- test/MC/X86/x86-32-coverage.s | 61 +- test/MC/X86/x86-32.s | 16 +- test/MC/X86/x86-64-avx512bw.s | 2 +- test/MC/X86/x86-64-avx512bw_vl.s | 2 +- test/MC/X86/x86-64-avx512cd.s | 3 +- test/MC/X86/x86-64-avx512cd_vl.s | 2 +- test/MC/X86/x86-64-avx512dq.s | 2 +- test/MC/X86/x86-64-avx512dq_vl.s | 2 +- test/MC/X86/x86-64-avx512f_vl.s | 2 +- test/MC/X86/x86-64-avx512vpopcntdq.s | 2 +- test/MC/X86/x86-64.s | 52 +- test/MC/X86/x86_64-asm-match.s | 79 +- test/MC/X86/x86_64-tbm-encoding.s | 78 +- test/MC/X86/x86_errors.s | 4 - test/MC/X86/x86_long_nop.s | 47 +- test/Object/AMDGPU/elf-header-flags-mach.yaml | 468 + test/Object/AMDGPU/elf-header-flags-xnack.yaml | 37 + test/Object/AMDGPU/elf-header-osabi.yaml | 50 + test/Object/AMDGPU/elf32-r600-definitions.yaml | 34 - .../AMDGPU/elf64-amdgcn-amdhsa-definitions.yaml | 34 - .../AMDGPU/elf64-amdgcn-amdpal-definitions.yaml | 34 - .../AMDGPU/elf64-amdgcn-mesa3d-definitions.yaml | 34 - .../invalid-sections-address-alignment.x86-64 | Bin 473 -> 0 bytes test/Object/Inputs/trivial-object-test.wasm | Bin 303 -> 320 bytes test/Object/invalid-alignment.test | 12 +- test/Object/invalid.test | 4 - test/Object/mangle-ir.ll | 4 +- test/Object/nm-trivial-object.test | 5 +- test/Object/obj2yaml.test | 37 +- test/Object/objdump-relocations.test | 6 +- test/Object/wasm-duplicate-name.test | 28 + test/ObjectYAML/wasm/code_section.yaml | 31 +- test/ObjectYAML/wasm/data_section.yaml | 12 +- test/ObjectYAML/wasm/export_section.yaml | 19 +- test/ObjectYAML/wasm/function_section.yaml | 17 + test/ObjectYAML/wasm/global_section.yaml | 6 +- test/ObjectYAML/wasm/import_section.yaml | 3 +- test/ObjectYAML/wasm/linking_section.yaml | 27 +- test/ObjectYAML/wasm/name_section.yaml | 3 +- test/ObjectYAML/wasm/start_section.yaml | 16 +- test/ObjectYAML/wasm/type_section.yaml | 6 +- test/ObjectYAML/wasm/weak_symbols.yaml | 44 +- test/Other/can-execute.txt | 1 + test/Other/cgscc-libcall-update.ll | 4 +- test/Other/lint.ll | 4 +- test/Other/new-pm-defaults.ll | 12 + test/Other/new-pm-lto-defaults.ll | 8 +- test/Other/new-pm-thinlto-defaults.ll | 8 +- test/Other/pass-pipelines.ll | 2 +- test/TableGen/AnonDefinitionOnDemand.td | 26 +- test/TableGen/BitOffsetDecoder.td | 10 - test/TableGen/BitsInit.td | 2 +- test/TableGen/BitsInitOverflow.td | 6 +- test/TableGen/FieldAccess.td | 20 +- test/TableGen/GlobalISelEmitter.td | 820 +- test/TableGen/MultiClass-defm-fail.td | 32 + test/TableGen/MultiClass-defm.td | 50 + test/TableGen/MultiPat.td | 20 +- test/TableGen/RelTest.td | 40 + test/TableGen/TargetInstrSpec.td | 20 +- test/TableGen/UnsetBitInit.td | 31 +- test/TableGen/code.td | 22 + test/TableGen/foldl.td | 71 + test/TableGen/foreach-eval.td | 62 + test/TableGen/foreach-leak.td | 25 + test/TableGen/foreach.td | 34 +- test/TableGen/if-type.td | 11 + test/TableGen/if.td | 41 + test/TableGen/listconcat.td | 14 + test/TableGen/size.td | 34 + test/TableGen/template-arg-dependency.td | 16 + .../X86/Inputs/dicompositetype-unique-alias.ll | 39 + test/ThinLTO/X86/Inputs/dicompositetype-unique2.ll | 46 + test/ThinLTO/X86/Inputs/dot-dumper.ll | 20 + test/ThinLTO/X86/alias_import.ll | 6 +- test/ThinLTO/X86/cache.ll | 55 + test/ThinLTO/X86/cfi-icall.ll | 3 +- test/ThinLTO/X86/deadstrip.ll | 12 +- .../X86/diagnostic-handler-remarks-with-hotness.ll | 27 +- test/ThinLTO/X86/dicompositetype-unique-alias.ll | 62 + test/ThinLTO/X86/dicompositetype-unique2.ll | 69 + test/ThinLTO/X86/dot-dumper.ll | 58 + test/ThinLTO/X86/internalize.ll | 5 +- test/ThinLTO/X86/linkonce_odr_unnamed_addr.ll | 10 + test/ThinLTO/X86/linkonce_resolution_comdat.ll | 2 +- test/ThinLTO/X86/module_summary_graph_traits.ll | 58 + .../AddDiscriminators/memcpy-discriminator.ll | 4 +- .../AggressiveInstCombine/trunc_const_expr.ll | 110 + .../AggressiveInstCombine/trunc_multi_uses.ll | 270 + .../AggressiveInstCombine/trunc_unreachable_bb.ll | 48 + test/Transforms/AlignmentFromAssumptions/simple.ll | 12 +- .../AlignmentFromAssumptions/simple32.ll | 12 +- test/Transforms/ArgumentPromotion/musttail.ll | 45 + .../ArgumentPromotion/naked_functions.ll | 23 + test/Transforms/BDCE/basic.ll | 11 + test/Transforms/BlockExtractor/extract-blocks.ll | 43 + test/Transforms/BlockExtractor/invalid-block.ll | 9 + test/Transforms/BlockExtractor/invalid-function.ll | 9 + .../callsite-instructions-before-call.ll | 253 + .../CallSiteSplitting/callsite-no-or-structure.ll | 48 +- .../CallSiteSplitting/callsite-no-splitting.ll | 24 + .../CallSiteSplitting/callsite-split-debug.ll | 11 +- .../CallSiteSplitting/callsite-split-or-phi.ll | 155 +- .../Transforms/CallSiteSplitting/callsite-split.ll | 12 +- test/Transforms/CallSiteSplitting/musttail.ll | 75 + test/Transforms/CallSiteSplitting/split-loop.ll | 90 + .../CodeExtractor/PartialInlineVarArg.ll | 28 +- .../CodeGenPrepare/AMDGPU/sink-addrspacecast.ll | 42 +- .../CodeGenPrepare/ARM/memory-intrinsics.ll | 43 + .../X86/memset_chk-simplify-nobuiltin.ll | 2 +- test/Transforms/CodeGenPrepare/X86/select.ll | 127 +- .../CodeGenPrepare/X86/sink-addrmode-select.ll | 34 + .../CodeGenPrepare/X86/x86-shuffle-sink.ll | 159 +- test/Transforms/ConstProp/calls-math-finite.ll | 55 +- test/Transforms/Coroutines/coro-split-alloc.ll | 64 + .../CorrelatedValuePropagation/non-null.ll | 20 +- .../CorrelatedValuePropagation/pr35807.ll | 66 + test/Transforms/DCE/basic.ll | 12 +- .../DeadArgElim/dbginfo-preserve-dbgloc.ll | 135 + test/Transforms/DeadArgElim/musttail-caller.ll | 16 + .../DeadStoreElimination/2011-09-06-MemCpy.ll | 6 +- .../2016-07-17-UseAfterFree.ll | 6 +- .../DeadStoreElimination/OverwriteStoreBegin.ll | 34 +- .../DeadStoreElimination/OverwriteStoreEnd.ll | 36 +- .../combined-partial-overwrites.ll | 4 +- test/Transforms/DeadStoreElimination/crash.ll | 4 +- .../DeadStoreElimination/cs-cs-aliasing.ll | 10 +- test/Transforms/DeadStoreElimination/debuginfo.ll | 40 + test/Transforms/DeadStoreElimination/lifetime.ll | 4 +- .../DeadStoreElimination/mda-with-dbg-values.ll | 4 +- .../DeadStoreElimination/memintrinsics.ll | 12 +- .../DeadStoreElimination/merge-stores.ll | 17 + .../DeadStoreElimination/no-targetdata.ll | 6 +- test/Transforms/DeadStoreElimination/pr11390.ll | 6 +- test/Transforms/DeadStoreElimination/simple.ll | 79 +- test/Transforms/EarlyCSE/debuginfo-dce.ll | 64 + test/Transforms/FunctionAttrs/naked_functions.ll | 25 + test/Transforms/FunctionAttrs/norecurse.ll | 4 +- test/Transforms/GVN/PRE/load-pre-licm.ll | 2 +- test/Transforms/GVN/PRE/phi-translate-2.ll | 7 +- test/Transforms/GVN/PRE/rle.ll | 22 +- test/Transforms/GVN/fence.ll | 6 +- test/Transforms/GVN/nonescaping-malloc.ll | 4 +- test/Transforms/GVN/pr17732.ll | 6 +- test/Transforms/GVN/pr36063.ll | 22 + .../GlobalOpt/PowerPC/coldcc_coldsites.ll | 81 + .../GlobalOpt}/PowerPC/lit.local.cfg | 0 test/Transforms/GlobalOpt/coldcc_stress_test.ll | 48 + test/Transforms/GlobalOpt/crash.ll | 4 +- test/Transforms/GlobalOpt/memcpy.ll | 4 +- test/Transforms/GlobalOpt/memset-null.ll | 6 +- test/Transforms/GlobalOpt/memset.ll | 14 +- test/Transforms/GlobalOpt/musttail_cc.ll | 34 + test/Transforms/GlobalOpt/naked_functions.ll | 23 + test/Transforms/IPConstantProp/musttail-call.ll | 58 + test/Transforms/IPConstantProp/remove-call-inst.ll | 33 + .../IPConstantProp/user-with-multiple-uses.ll | 5 +- test/Transforms/IRCE/conjunctive-checks.ll | 6 +- test/Transforms/IRCE/decrementing-loop.ll | 80 + test/Transforms/IRCE/only-lower-check.ll | 2 +- test/Transforms/IRCE/optimistic_scev.ll | 42 + test/Transforms/IRCE/single-access-no-preloop.ll | 72 +- test/Transforms/IndVarSimplify/inner-loop.ll | 54 + .../IndVarSimplify/loop-invariant-conditions.ll | 66 +- test/Transforms/IndirectBrExpand/basic.ll | 63 + test/Transforms/InferAddressSpaces/AMDGPU/basic.ll | 132 +- test/Transforms/InferAddressSpaces/AMDGPU/icmp.ll | 118 +- .../AMDGPU/infer-address-space.ll | 82 +- .../AMDGPU/infer-addrspacecast.ll | 30 +- .../AMDGPU/infer-getelementptr.ll | 44 +- .../InferAddressSpaces/AMDGPU/intrinsics.ll | 100 +- .../InferAddressSpaces/AMDGPU/mem-intrinsics.ll | 114 +- .../AMDGPU/old-pass-regressions.ll | 46 +- .../Transforms/InferAddressSpaces/AMDGPU/select.ll | 210 +- .../InferAddressSpaces/AMDGPU/volatile.ll | 128 +- test/Transforms/Inline/alloca-dbgdeclare.ll | 6 +- test/Transforms/Inline/byval.ll | 13 +- test/Transforms/Inline/inline-invoke-tail.ll | 4 +- test/Transforms/Inline/inline-varargs.ll | 17 +- test/Transforms/Inline/inline-vla.ll | 6 +- test/Transforms/Inline/last-callsite.ll | 2 +- test/Transforms/Inline/noalias-calls.ll | 18 +- .../InstCombine/2007-10-10-EliminateMemCpy.ll | 4 +- .../InstCombine/2008-05-22-NegValVector.ll | 14 - .../InstCombine/2009-02-20-InstCombine-SROA.ll | 4 +- .../Transforms/InstCombine/2017-07-07-UMul-ZExt.ll | 51 - .../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 108 + .../InstCombine/X86/X86FsubCmpCombine.ll | 168 +- test/Transforms/InstCombine/addrspacecast.ll | 8 +- test/Transforms/InstCombine/align-addr.ll | 6 +- .../InstCombine/alloca-cast-debuginfo.ll | 4 + test/Transforms/InstCombine/alloca.ll | 6 +- test/Transforms/InstCombine/and-narrow.ll | 192 + test/Transforms/InstCombine/and.ll | 17 + test/Transforms/InstCombine/apint-mul1.ll | 33 +- test/Transforms/InstCombine/apint-mul2.ll | 37 +- test/Transforms/InstCombine/apint-sub.ll | 21 - test/Transforms/InstCombine/assume.ll | 17 + test/Transforms/InstCombine/bswap.ll | 101 +- test/Transforms/InstCombine/call-intrinsics.ll | 12 +- test/Transforms/InstCombine/cast-mul-select.ll | 142 +- test/Transforms/InstCombine/cos-intrinsic.ll | 85 +- test/Transforms/InstCombine/debuginfo-variables.ll | 95 + test/Transforms/InstCombine/div-shift.ll | 134 +- test/Transforms/InstCombine/div.ll | 55 + .../InstCombine/double-float-shrink-2.ll | 380 +- test/Transforms/InstCombine/fast-math.ll | 601 +- test/Transforms/InstCombine/fdiv-cos-sin.ll | 116 + test/Transforms/InstCombine/fdiv-sin-cos.ll | 111 + test/Transforms/InstCombine/fdiv.ll | 379 +- test/Transforms/InstCombine/fmul-sqrt.ll | 48 +- test/Transforms/InstCombine/fmul.ll | 184 +- test/Transforms/InstCombine/fpextend.ll | 305 +- test/Transforms/InstCombine/gep-custom-dl.ll | 155 + test/Transforms/InstCombine/icmp-custom-dl.ll | 247 + test/Transforms/InstCombine/icmp-mul-zext.ll | 82 + test/Transforms/InstCombine/icmp.ll | 12 + test/Transforms/InstCombine/malloc-free-delete.ll | 44 +- test/Transforms/InstCombine/max-of-nots.ll | 35 +- .../InstCombine/mem-par-metadata-memcpy.ll | 4 +- test/Transforms/InstCombine/memcpy-1.ll | 2 +- test/Transforms/InstCombine/memcpy-addrspace.ll | 10 +- test/Transforms/InstCombine/memcpy-from-global.ll | 50 +- test/Transforms/InstCombine/memcpy-to-load.ll | 22 +- test/Transforms/InstCombine/memcpy.ll | 14 +- test/Transforms/InstCombine/memcpy_chk-1.ll | 4 +- test/Transforms/InstCombine/memmove.ll | 16 +- test/Transforms/InstCombine/memmove_chk-1.ll | 4 +- test/Transforms/InstCombine/memset-1.ll | 2 +- test/Transforms/InstCombine/memset.ll | 12 +- test/Transforms/InstCombine/memset2.ll | 4 +- test/Transforms/InstCombine/memset_chk-1.ll | 8 +- test/Transforms/InstCombine/minmax-fold.ll | 57 +- test/Transforms/InstCombine/mul.ll | 484 +- test/Transforms/InstCombine/objsize.ll | 4 +- test/Transforms/InstCombine/opaque.ll | 5 +- test/Transforms/InstCombine/phi-timeout.ll | 47 + test/Transforms/InstCombine/pow-4.ll | 100 +- .../Transforms/InstCombine/pr31990_wrong_memcpy.ll | 5 +- test/Transforms/InstCombine/pr33765.ll | 31 - test/Transforms/InstCombine/pr36362.ll | 17 + test/Transforms/InstCombine/select-gep.ll | 138 + test/Transforms/InstCombine/select.ll | 21 +- test/Transforms/InstCombine/select_arithmetic.ll | 62 +- test/Transforms/InstCombine/shift.ll | 23 + test/Transforms/InstCombine/should-change-type.ll | 57 + test/Transforms/InstCombine/signext.ll | 2 +- test/Transforms/InstCombine/simplify-libcalls.ll | 8 +- test/Transforms/InstCombine/sprintf-1.ll | 4 +- test/Transforms/InstCombine/stack-overalign.ll | 8 +- test/Transforms/InstCombine/stpcpy_chk-1.ll | 6 +- test/Transforms/InstCombine/strcpy_chk-1.ll | 6 +- test/Transforms/InstCombine/strncpy_chk-1.ll | 4 +- .../InstCombine/struct-assign-tbaa-new.ll | 53 + test/Transforms/InstCombine/struct-assign-tbaa.ll | 6 +- test/Transforms/InstCombine/sub.ll | 65 +- .../InstCombine/udiv_select_to_select_shift.ll | 7 +- .../InstCombine/unsigned_saturated_sub.ll | 178 + test/Transforms/InstCombine/vec_demanded_elts.ll | 3 - test/Transforms/InstCombine/vector-mul.ll | 349 +- test/Transforms/InstCombine/vector-udiv.ll | 99 + test/Transforms/InstCombine/vector-urem.ll | 61 +- test/Transforms/InstCombine/vector-xor.ll | 317 + test/Transforms/InstSimplify/AndOrXor.ll | 26 +- test/Transforms/InstSimplify/and-or-icmp-zero.ll | 263 + test/Transforms/InstSimplify/assume.ll | 21 + test/Transforms/InstSimplify/div.ll | 16 + test/Transforms/InstSimplify/exp-intrinsic.ll | 71 - test/Transforms/InstSimplify/exp2-intrinsic.ll | 71 - test/Transforms/InstSimplify/fast-math.ll | 15 + test/Transforms/InstSimplify/fdiv.ll | 40 +- .../InstSimplify/floating-point-arithmetic.ll | 316 +- test/Transforms/InstSimplify/fp-undef.ll | 89 + test/Transforms/InstSimplify/icmp-bool-constant.ll | 25 + test/Transforms/InstSimplify/log-exp-intrinsic.ll | 192 + test/Transforms/InstSimplify/log-intrinsic.ll | 71 - test/Transforms/InstSimplify/log2-intrinsic.ll | 71 - test/Transforms/InstSimplify/mul.ll | 25 + test/Transforms/InstSimplify/or.ll | 15 +- test/Transforms/InstSimplify/reassociate.ll | 141 +- test/Transforms/InstSimplify/rem.ll | 102 +- test/Transforms/InstSimplify/select.ll | 20 + test/Transforms/InstSimplify/shr-nop.ll | 8 + test/Transforms/JumpThreading/ddt-crash.ll | 265 + test/Transforms/JumpThreading/ddt-crash2.ll | 40 + test/Transforms/JumpThreading/ddt-crash3.ll | 43 + test/Transforms/JumpThreading/ddt-crash4.ll | 75 + test/Transforms/JumpThreading/lvi-tristate.ll | 50 + test/Transforms/JumpThreading/pr36133.ll | 44 + .../LCSSA/avoid-intrinsics-in-catchswitch.ll | 133 + test/Transforms/LCSSA/basictest.ll | 2 + test/Transforms/LICM/pr26843.ll | 4 +- test/Transforms/LICM/pr27262.ll | 4 +- test/Transforms/LICM/sinking.ll | 61 + test/Transforms/LICM/unrolled-deeply-nested.ll | 6 +- .../AMDGPU/adjust-alloca-alignment.ll | 115 +- .../AMDGPU/merge-stores-private.ll | 189 +- test/Transforms/LoopDeletion/use-in-unreachable.ll | 24 + test/Transforms/LoopIdiom/basic-address-space.ll | 2 +- test/Transforms/LoopIdiom/basic.ll | 99 +- .../LoopIdiom/lir-heurs-multi-block-loop.ll | 4 +- test/Transforms/LoopIdiom/pr28196.ll | 2 +- test/Transforms/LoopIdiom/struct-custom-dl.ll | 212 + test/Transforms/LoopIdiom/unroll-custom-dl.ll | 78 + .../LoopInterchange/call-instructions.ll | 2 +- .../LoopInterchange/currentLimitation.ll | 2 +- .../LoopInterchange/interchange-flow-dep-outer.ll | 2 +- .../interchange-insts-between-indvar.ll | 2 +- .../LoopInterchange/interchange-latch-no-exit.ll | 40 + .../LoopInterchange/interchange-no-deps.ll | 44 + .../interchange-output-dependencies.ll | 2 +- .../interchange-simple-count-down.ll | 2 +- .../LoopInterchange/interchange-simple-count-up.ll | 2 +- .../not-interchanged-dependencies-1.ll | 2 +- test/Transforms/LoopInterchange/phi-ordering.ll | 2 +- test/Transforms/LoopInterchange/profitability.ll | 2 +- test/Transforms/LoopInterchange/reductions.ll | 2 +- test/Transforms/LoopPredication/reverse.ll | 105 + test/Transforms/LoopRotate/indirectbr.ll | 35 +- .../AMDGPU/different-addrspace-crash.ll | 5 +- .../LoopStrengthReduce/X86/ivchain-X86.ll | 406 +- .../LoopStrengthReduce/X86/lsr-insns-1.ll | 75 +- .../LoopStrengthReduce/X86/macro-fuse-cmp.ll | 118 + .../LoopStrengthReduce/X86/nested-loop.ll | 52 +- .../LoopStrengthReduce/post-inc-icmpzero.ll | 5 +- .../LoopUnroll/AMDGPU/unroll-for-private.ll | 42 +- test/Transforms/LoopUnroll/convergent.ll | 96 + test/Transforms/LoopUnroll/peel-loop.ll | 13 +- test/Transforms/LoopUnroll/unroll-pragmas.ll | 63 +- .../Transforms/LoopUnswitch/2015-06-17-Metadata.ll | 4 +- test/Transforms/LoopUnswitch/infinite-loop.ll | 2 +- test/Transforms/LoopVectorize/AArch64/pr36032.ll | 153 + test/Transforms/LoopVectorize/ARM/sphinx.ll | 165 + test/Transforms/LoopVectorize/X86/avx512.ll | 79 +- .../LoopVectorize/X86/consecutive-ptr-cg-bug.ll | 46 +- .../Transforms/LoopVectorize/X86/gather_scatter.ll | 768 +- .../LoopVectorize/X86/imprecise-through-phis.ll | 85 +- .../LoopVectorize/X86/masked_load_store.ll | 2878 +- .../LoopVectorize/X86/metadata-enable.ll | 2439 +- test/Transforms/LoopVectorize/X86/pr35432.ll | 213 + .../LoopVectorize/conditional-assignment.ll | 2 +- test/Transforms/LoopVectorize/hoist-loads.ll | 3 +- .../interleaved-acess-with-remarks.ll | 43 + .../LoopVectorize/pr30654-phiscev-sext-trunc.ll | 2 +- test/Transforms/LoopVectorize/pr35743.ll | 102 + test/Transforms/LoopVectorize/pr35773.ll | 53 + .../LoopVectorize/reduction-small-size.ll | 37 +- test/Transforms/LoopVectorize/tripcount.ll | 122 +- .../LoopVectorize/vect-phiscev-sext-trunc.ll | 4 +- .../LowerTypeTests/Inputs/blockaddr-import.yaml | 9 + .../LowerTypeTests/Inputs/import-alias.yaml | 11 + test/Transforms/LowerTypeTests/blockaddr-import.ll | 22 + test/Transforms/LowerTypeTests/export-alias.ll | 21 + test/Transforms/LowerTypeTests/import-alias.ll | 30 + .../MemCpyOpt/2008-02-24-MultipleUseofSRet.ll | 6 +- .../MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll | 4 +- test/Transforms/MemCpyOpt/align.ll | 10 +- test/Transforms/MemCpyOpt/atomic.ll | 4 +- test/Transforms/MemCpyOpt/callslot_aa.ll | 8 +- test/Transforms/MemCpyOpt/callslot_deref.ll | 12 +- test/Transforms/MemCpyOpt/capturing-func.ll | 4 +- test/Transforms/MemCpyOpt/crash.ll | 9 +- test/Transforms/MemCpyOpt/form-memset.ll | 40 +- test/Transforms/MemCpyOpt/invariant.start.ll | 24 +- test/Transforms/MemCpyOpt/lifetime.ll | 4 +- .../MemCpyOpt/memcpy-to-memset-with-lifetimes.ll | 26 +- test/Transforms/MemCpyOpt/memcpy-to-memset.ll | 4 +- test/Transforms/MemCpyOpt/memcpy-undef.ll | 8 +- test/Transforms/MemCpyOpt/memcpy.ll | 48 +- test/Transforms/MemCpyOpt/memmove.ll | 8 +- .../MemCpyOpt/memset-memcpy-redundant-memset.ll | 102 +- .../MemCpyOpt/memset-memcpy-to-2x-memset.ll | 80 +- test/Transforms/MemCpyOpt/pr29105.ll | 10 +- test/Transforms/MemCpyOpt/profitable-memset.ll | 2 +- test/Transforms/MemCpyOpt/smaller.ll | 8 +- test/Transforms/MemCpyOpt/sret.ll | 4 +- test/Transforms/MergeFunc/vector.ll | 2 +- .../MergeICmps/X86/last-block-produce-no-value.ll | 57 + .../MergeICmps/X86/multiple-blocks-does-work.ll | 64 + test/Transforms/MergeICmps/X86/two-complex-bb.ll | 58 + test/Transforms/MetaRenamer/metarenamer.ll | 4 +- test/Transforms/NewGVN/memory-handling.ll | 8 +- test/Transforms/NewGVN/nonescaping-malloc.ll | 4 +- test/Transforms/NewGVN/phi-of-ops-move-block.ll | 56 + test/Transforms/NewGVN/pr17732.ll | 6 +- test/Transforms/NewGVN/pr33367.ll | 137 + test/Transforms/NewGVN/rle.ll | 14 +- .../Transforms/ObjCARC/contract-replace-arg-use.ll | 28 + test/Transforms/ObjCARC/nested.ll | 24 +- test/Transforms/ObjCARC/rv.ll | 31 + test/Transforms/PGOProfile/memcpy.ll | 4 +- test/Transforms/PGOProfile/memop_clone.ll | 20 +- .../Transforms/PGOProfile/memop_size_annotation.ll | 6 +- .../PGOProfile/memop_size_from_strlen.ll | 4 +- test/Transforms/PGOProfile/memop_size_opt.ll | 14 +- test/Transforms/PGOProfile/memop_size_opt_zero.ll | 6 +- .../thinlto_samplepgo_icp_droppeddead.ll | 71 + test/Transforms/PhaseOrdering/scev-custom-dl.ll | 67 + test/Transforms/PlaceSafepoints/memset.ll | 4 +- test/Transforms/Reassociate/fast-basictest.ll | 124 +- .../RewriteStatepointsForGC/base-vector.ll | 16 + .../RewriteStatepointsForGC/deref-pointers.ll | 35 +- test/Transforms/RewriteStatepointsForGC/invokes.ll | 26 + .../RewriteStatepointsForGC/relocation.ll | 20 +- .../unreachable-regression.ll | 34 + .../RewriteStatepointsForGC/vector-bitcast.ll | 8 +- test/Transforms/SCCP/ip-constant-ranges.ll | 26 + test/Transforms/SCCP/loadtest.ll | 22 +- .../SLPVectorizer/AArch64/gather-reduce.ll | 313 +- .../SLPVectorizer/AArch64/gather-root.ll | 176 +- test/Transforms/SLPVectorizer/AArch64/matmul.ll | 139 + test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll | 127 + .../Transforms/SLPVectorizer/ARM/extract-insert.ll | 31 + test/Transforms/SLPVectorizer/X86/PR32086.ll | 56 +- test/Transforms/SLPVectorizer/X86/PR35628_1.ll | 74 + test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 64 + test/Transforms/SLPVectorizer/X86/PR35777.ll | 45 + test/Transforms/SLPVectorizer/X86/PR35865.ll | 27 + test/Transforms/SLPVectorizer/X86/PR36280.ll | 25 + test/Transforms/SLPVectorizer/X86/addsub.ll | 178 +- .../SLPVectorizer/X86/blending-shuffle.ll | 20 +- .../Transforms/SLPVectorizer/X86/compare-reduce.ll | 39 +- test/Transforms/SLPVectorizer/X86/cse.ll | 174 +- .../X86/external_user_jumbled_load.ll | 42 + .../SLPVectorizer/X86/extract-shuffle.ll | 25 + test/Transforms/SLPVectorizer/X86/extract.ll | 49 +- .../SLPVectorizer/X86/extract_in_tree_user.ll | 43 +- test/Transforms/SLPVectorizer/X86/funclet.ll | 32 +- test/Transforms/SLPVectorizer/X86/hoist.ll | 33 +- test/Transforms/SLPVectorizer/X86/horizontal.ll | 1076 +- test/Transforms/SLPVectorizer/X86/in-tree-user.ll | 38 +- .../X86/insert-element-build-vector.ll | 32 +- test/Transforms/SLPVectorizer/X86/insertvalue.ll | 26 +- .../SLPVectorizer/X86/jumbled-load-multiuse.ll | 27 +- .../X86/jumbled-load-shuffle-placement.ll | 139 + .../SLPVectorizer/X86/jumbled-load-used-in-phi.ll | 232 + test/Transforms/SLPVectorizer/X86/jumbled-load.ll | 61 +- test/Transforms/SLPVectorizer/X86/minimum-sizes.ll | 55 +- test/Transforms/SLPVectorizer/X86/pr19657.ll | 45 +- .../SLPVectorizer/X86/reassociated-loads.ll | 139 + .../SLPVectorizer/X86/reduction_unrolled.ll | 50 +- test/Transforms/SLPVectorizer/X86/reorder_phi.ll | 50 +- test/Transforms/SLPVectorizer/X86/return.ll | 36 +- .../SLPVectorizer/X86/reverse_extract_elements.ll | 36 +- test/Transforms/SLPVectorizer/X86/sext.ll | 911 + test/Transforms/SLPVectorizer/X86/sign-extend.ll | 62 + test/Transforms/SLPVectorizer/X86/simplebb.ll | 68 +- .../SLPVectorizer/X86/stores_vectorize.ll | 237 +- test/Transforms/SLPVectorizer/X86/value-bug.ll | 36 +- .../SLPVectorizer/X86/visit-dominated.ll | 153 - test/Transforms/SLPVectorizer/X86/zext.ll | 785 + test/Transforms/SROA/address-spaces.ll | 22 +- test/Transforms/SROA/alignment.ll | 18 +- test/Transforms/SROA/alloca-address-space.ll | 22 +- test/Transforms/SROA/basictest.ll | 534 +- test/Transforms/SROA/big-endian.ll | 44 +- test/Transforms/SROA/dbg-addr-diamond.ll | 4 +- test/Transforms/SROA/mem-par-metadata-sroa.ll | 2 +- test/Transforms/SROA/preserve-nonnull.ll | 4 +- test/Transforms/SROA/slice-order-independence.ll | 6 +- test/Transforms/SROA/slice-width.ll | 14 +- test/Transforms/SROA/vector-promotion.ll | 42 +- test/Transforms/SafeStack/X86/byval.ll | 19 +- test/Transforms/SafeStack/X86/call.ll | 10 +- test/Transforms/SampleProfile/gcc-simple.ll | 2 +- ...split-gep-and-gvn-addrspace-addressing-modes.ll | 97 +- .../Transforms/SimplifyCFG/UncondBranchToHeader.ll | 18 + test/Transforms/SimplifyCFG/critedge-assume.ll | 2 +- .../SimplifyCFG/switch_create-custom-dl.ll | 660 + test/Transforms/Sink/badloadsink.ll | 12 +- .../StructurizeCFG/AMDGPU/backedge-id-bug.ll | 1 + test/Transforms/StructurizeCFG/bug36015.ll | 53 + .../Transforms/StructurizeCFG/nested-loop-order.ll | 83 +- .../SyntheticCountsPropagation/initial.ll | 79 + test/Transforms/SyntheticCountsPropagation/prop.ll | 50 + test/Transforms/SyntheticCountsPropagation/scc.ll | 19 + .../ThinLTOBitcodeWriter/function-alias.ll | 25 + .../ThinLTOBitcodeWriter/x86/lit.local.cfg | 3 + .../ThinLTOBitcodeWriter/x86/module-asm.ll | 12 + .../Util/combine-alias-scope-metadata.ll | 10 +- test/Verifier/2006-12-12-IntrinsicDefine.ll | 2 +- test/Verifier/2008-08-22-MemCpyAlignment.ll | 12 - test/Verifier/2010-08-07-PointerIntrinsic.ll | 2 +- test/Verifier/DIFile.ll | 29 + test/Verifier/invalid-disubrange-count-node.ll | 37 + test/Verifier/invalid-eh.ll | 2 +- test/Verifier/llvm.dbg.intrinsic-dbg-attachment.ll | 2 +- test/Verifier/memcpy.ll | 6 +- test/Verifier/test_copy.mir | 33 + test/Verifier/test_copy_mismatch_types.mir | 31 + test/Verifier/test_g_phi.mir | 8 +- test/Verifier/variant-part.ll | 8 + test/lit.cfg.py | 30 + test/tools/dsymutil/Inputs/invalid.o | Bin 0 -> 2076 bytes test/tools/dsymutil/Inputs/invalid.s | 262 + test/tools/dsymutil/Inputs/label.o | Bin 0 -> 1088 bytes test/tools/dsymutil/Inputs/objc.macho.x86_64 | Bin 0 -> 9736 bytes test/tools/dsymutil/Inputs/objc.macho.x86_64.o | Bin 0 -> 7788 bytes test/tools/dsymutil/Inputs/sibling.o | Bin 0 -> 1732 bytes test/tools/dsymutil/PowerPC/lit.local.cfg | 4 + test/tools/dsymutil/PowerPC/sibling.test | 33 + test/tools/dsymutil/X86/basic-linking-x86.test | 28 +- .../dsymutil/X86/basic-lto-dw4-linking-x86.test | 40 +- test/tools/dsymutil/X86/basic-lto-linking-x86.test | 235 +- test/tools/dsymutil/X86/label.test | 16 + test/tools/dsymutil/X86/minimize.test | 9 + test/tools/dsymutil/X86/objc.test | 52 + test/tools/dsymutil/X86/update-one-CU.test | 38 + test/tools/dsymutil/X86/update.test | 18 + test/tools/dsymutil/X86/verify.test | 31 +- test/tools/dsymutil/cmdline.test | 2 + test/tools/gold/X86/cache.ll | 14 +- test/tools/gold/X86/coff.ll | 2 +- test/tools/gold/X86/emit-llvm.ll | 6 +- test/tools/gold/X86/global_with_section.ll | 17 +- test/tools/gold/X86/thinlto.ll | 3 + test/tools/gold/X86/thinlto_linkonceresolution.ll | 2 +- test/tools/gold/X86/thinlto_no_objects.ll | 18 + ..._objects.ll => thinlto_emit_linked_objects2.ll} | 0 .../v1.12/Inputs/thinlto_emit_linked_objects3.ll | 7 + .../gold/X86/v1.12/thinlto_emit_linked_objects.ll | 47 +- test/tools/llvm-ar/mri-delete.test | 14 + test/tools/llvm-ar/regex-cmd.test | 7 + .../X86/blacklist-expected-unprotected.s | 2 +- .../llvm-cfi-verify/X86/blacklist-match-fun.s | 2 +- .../X86/blacklist-unexpected-protected.s | 2 +- test/tools/llvm-cfi-verify/X86/dot-printing.s | 5 +- .../llvm-cfi-verify/X86/indirect-cf-elimination.s | 4 +- .../tools/llvm-cfi-verify/X86/protected-lineinfo.s | 2 +- .../llvm-cfi-verify/X86/unprotected-lineinfo.s | 2 +- test/tools/llvm-config/system-libs.windows.test | 2 +- test/tools/llvm-cov/copy_block_helper.m | 2 +- test/tools/llvm-cov/gcov47_compatibility.cpp | 2 +- test/tools/llvm-cov/hideUnexecutedSubviews.test | 10 +- test/tools/llvm-cov/llvm-cov.test | 2 +- test/tools/llvm-cov/multithreaded-report.test | 3 - test/tools/llvm-cov/range_based_for.cpp | 2 +- test/tools/llvm-cov/showLineExecutionCounts.cpp | 13 +- test/tools/llvm-cov/style.test | 10 +- test/tools/llvm-cvtres/help.test | 2 +- .../X86/Inputs/debug_rnglists_short_section.s | 2 + test/tools/llvm-dwarfdump/X86/debug-names-find.s | 182 + .../tools/llvm-dwarfdump/X86/debug_loc_offset.test | 8 +- test/tools/llvm-dwarfdump/X86/debug_rnglists.s | 147 + .../llvm-dwarfdump/X86/debug_rnglists_empty.s | 7 + .../llvm-dwarfdump/X86/debug_rnglists_invalid.s | 161 + test/tools/llvm-dwarfdump/X86/debugloc.s | 15 +- test/tools/llvm-dwarfdump/X86/verify_die_ranges.s | 2 +- test/tools/llvm-extract/extract-block.ll | 29 + test/tools/llvm-extract/extract-invalid-block.ll | 28 + test/tools/llvm-extract/extract-multiple-blocks.ll | 29 + .../llvm-isel-fuzzer/aarch64-execname-options.ll | 3 + test/tools/llvm-isel-fuzzer/execname-options.ll | 3 + test/tools/llvm-lto/thinlto.ll | 1 + test/tools/llvm-mt/big_merge.test | 2 +- test/tools/llvm-mt/conflicting.test | 2 +- test/tools/llvm-mt/simple_merge.test | 2 +- test/tools/llvm-mt/single_file.test | 2 +- test/tools/llvm-mt/xml_error.test | 2 +- .../AArch64/Inputs/kextbundle.macho-aarch64 | Bin .../llvm-nm}/AArch64/lit.local.cfg | 0 test/tools/llvm-nm/AArch64/macho-kextbundle.test | 4 + test/tools/llvm-nm/wasm/exports.yaml | 83 +- test/tools/llvm-nm/wasm/imports.yaml | 32 +- test/tools/llvm-nm/wasm/weak-symbols.yaml | 101 +- test/tools/llvm-objcopy/Inputs/alloc-symtab.o | Bin 0 -> 1312 bytes test/tools/llvm-objcopy/add-gnu-debuglink.test | 28 + test/tools/llvm-objcopy/basic-align-copy.test | 37 - test/tools/llvm-objcopy/binary-no-paddr.test | 42 + test/tools/llvm-objcopy/binary-out-error.test | 2 + test/tools/llvm-objcopy/binary-paddr.test | 45 + test/tools/llvm-objcopy/binary-segment-layout.test | 38 + test/tools/llvm-objcopy/marker-segment.test | 111 + test/tools/llvm-objcopy/remove-shstrtab-error.test | 2 +- test/tools/llvm-objcopy/strip-dwo-inplace.test | 29 + test/tools/llvm-objcopy/two-seg-remove-end.test | 4 +- test/tools/llvm-objcopy/two-seg-remove-first.test | 4 +- .../llvm-objcopy/two-seg-remove-third-sec.test | 4 +- test/tools/llvm-objdump/AMDGPU/source-lines.ll | 6 +- test/tools/llvm-objdump/Inputs/embedded-source | Bin 0 -> 9936 bytes test/tools/llvm-objdump/Inputs/trivial.obj.wasm | Bin 303 -> 320 bytes .../llvm-objdump/WebAssembly/symbol-table.test | 13 +- test/tools/llvm-objdump/embedded-source.test | 23 + test/tools/llvm-objdump/wasm.txt | 19 +- test/tools/llvm-opt-fuzzer/exec-options.ll | 10 + .../llvm-pdbdump/Inputs/PrettyFuncDumperTest.cpp | 49 + .../llvm-pdbdump/Inputs/PrettyFuncDumperTest.pdb | Bin 0 -> 102400 bytes .../llvm-pdbdump/Inputs/TypeQualifiersTest.cpp | 55 + .../llvm-pdbdump/Inputs/TypeQualifiersTest.pdb | 0 test/tools/llvm-pdbdump/pretty-func-dumper.test | 25 + test/tools/llvm-pdbdump/type-qualifiers.test | 25 + .../llvm-profdata/gcc-gcov-sample-profile.test | 2 +- test/tools/llvm-readobj/Inputs/trivial.obj.wasm | Bin 285 -> 291 bytes test/tools/llvm-readobj/elf-linker-options.ll | 12 + test/tools/llvm-readobj/macho-needed-libs.test | 26 + test/tools/llvm-readobj/relocations.test | 8 +- test/tools/llvm-readobj/sections.test | 49 +- test/tools/llvm-readobj/symbols.test | 28 +- test/tools/llvm-split/preserve-locals.ll | 2 +- test/tools/llvm-split/scc-alias.ll | 4 +- test/tools/llvm-split/scc-callchain.ll | 6 +- test/tools/llvm-split/scc-comdat.ll | 4 +- test/tools/llvm-split/scc-constants.ll | 4 +- test/tools/llvm-split/scc-cycle.ll | 4 +- test/tools/llvm-split/scc-global2global.ll | 4 +- test/tools/llvm-symbolizer/pdb/pdb.test | 2 +- test/tools/llvm-symbolizer/ppc64.test | 2 +- test/tools/llvm-symbolizer/split-debug.test | 26 + test/tools/llvm-xray/X86/extract-all-sledtypes.txt | 2 +- .../tools/opt-viewer/Outputs/basic/basic_or.c.html | 1 + .../tools/opt-viewer/Outputs/basic/basic_or.h.html | 1 + .../tools/opt-viewer/Outputs/suppress/s.swift.html | 1 + .../Outputs/unicode-function-name/s.swift.html | 1 + tools/bugpoint/BugDriver.cpp | 28 +- tools/bugpoint/BugDriver.h | 82 +- tools/bugpoint/CrashDebugger.cpp | 340 +- tools/bugpoint/ExecutionDriver.cpp | 49 +- tools/bugpoint/ExtractFunction.cpp | 27 +- tools/bugpoint/FindBugs.cpp | 8 +- tools/bugpoint/Miscompilation.cpp | 115 +- tools/bugpoint/OptimizerDriver.cpp | 31 +- tools/dsymutil/BinaryHolder.cpp | 4 +- tools/dsymutil/BinaryHolder.h | 24 +- tools/dsymutil/CMakeLists.txt | 10 +- tools/dsymutil/DebugMap.cpp | 3 +- tools/dsymutil/DebugMap.h | 24 +- tools/dsymutil/DwarfLinker.cpp | 1084 +- tools/dsymutil/MachODebugMapParser.cpp | 34 +- tools/dsymutil/MachOUtils.cpp | 40 +- tools/dsymutil/MachOUtils.h | 8 +- tools/dsymutil/NonRelocatableStringpool.cpp | 51 + tools/dsymutil/NonRelocatableStringpool.h | 59 +- tools/dsymutil/dsymutil.cpp | 136 +- tools/dsymutil/dsymutil.h | 17 +- tools/gold/gold-plugin.cpp | 147 +- tools/llc/llc.cpp | 25 +- tools/lli/OrcLazyJIT.h | 112 +- tools/lli/RemoteJITUtils.h | 4 +- tools/lli/lli.cpp | 4 +- tools/llvm-ar/llvm-ar.cpp | 23 +- tools/llvm-as/llvm-as.cpp | 11 +- tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp | 3 + tools/llvm-c-test/attributes.c | 3 + tools/llvm-c-test/echo.cpp | 21 +- tools/llvm-cat/llvm-cat.cpp | 2 +- tools/llvm-cfi-verify/llvm-cfi-verify.cpp | 152 +- tools/llvm-config/CMakeLists.txt | 15 +- tools/llvm-cov/CoverageExporterJson.cpp | 63 +- tools/llvm-cov/CoverageExporterJson.h | 6 +- tools/llvm-cov/SourceCoverageViewHTML.cpp | 49 +- tools/llvm-cvtres/Opts.td | 2 +- tools/llvm-dwarfdump/llvm-dwarfdump.cpp | 27 +- tools/llvm-extract/llvm-extract.cpp | 40 + tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp | 4 +- tools/llvm-link/llvm-link.cpp | 2 +- tools/llvm-lto/llvm-lto.cpp | 17 +- tools/llvm-lto2/llvm-lto2.cpp | 9 +- tools/llvm-mc/llvm-mc.cpp | 140 +- tools/llvm-modextract/llvm-modextract.cpp | 2 +- tools/llvm-nm/llvm-nm.cpp | 4 + tools/llvm-objcopy/Object.cpp | 745 +- tools/llvm-objcopy/Object.h | 343 +- tools/llvm-objcopy/llvm-objcopy.cpp | 146 +- tools/llvm-objcopy/llvm-objcopy.h | 3 + tools/llvm-objdump/MachODump.cpp | 310 +- tools/llvm-objdump/llvm-objdump.cpp | 28 +- tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp | 40 +- tools/llvm-pdbutil/Diff.cpp | 4 +- tools/llvm-pdbutil/PrettyBuiltinDumper.cpp | 9 +- tools/llvm-pdbutil/PrettyFunctionDumper.cpp | 5 + tools/llvm-pdbutil/PrettyTypedefDumper.cpp | 3 + tools/llvm-pdbutil/PrettyVariableDumper.cpp | 6 + tools/llvm-rc/ResourceFileWriter.h | 2 +- tools/llvm-rc/ResourceScriptToken.h | 2 +- tools/llvm-readobj/ARMEHABIPrinter.h | 13 +- tools/llvm-readobj/COFFDumper.cpp | 19 +- tools/llvm-readobj/COFFImportDumper.cpp | 38 +- tools/llvm-readobj/ELFDumper.cpp | 155 +- tools/llvm-readobj/MachODumper.cpp | 39 +- tools/llvm-readobj/ObjDumper.h | 4 +- tools/llvm-readobj/StackMapPrinter.h | 49 +- tools/llvm-readobj/WasmDumper.cpp | 20 +- tools/llvm-readobj/llvm-readobj.cpp | 46 +- tools/llvm-split/llvm-split.cpp | 2 +- tools/llvm-xray/func-id-helper.cc | 8 +- tools/llvm-xray/func-id-helper.h | 2 + tools/llvm-xray/xray-account.cc | 7 +- tools/lto/lto.cpp | 10 + tools/lto/lto.exports | 6 +- tools/obj2yaml/elf2yaml.cpp | 8 +- tools/obj2yaml/wasm2yaml.cpp | 62 +- tools/opt-viewer/opt-diff.py | 15 +- tools/opt-viewer/opt-viewer.py | 20 +- tools/opt-viewer/optpmap.py | 2 + tools/opt-viewer/optrecord.py | 2 +- tools/opt/CMakeLists.txt | 1 + tools/opt/Debugify.cpp | 30 +- tools/opt/NewPMDriver.cpp | 33 +- tools/opt/NewPMDriver.h | 5 +- tools/opt/PassPrinters.h | 16 + tools/opt/opt.cpp | 35 +- tools/verify-uselistorder/verify-uselistorder.cpp | 2 +- tools/yaml2obj/yaml2elf.cpp | 27 +- tools/yaml2obj/yaml2wasm.cpp | 134 +- unittests/ADT/APIntTest.cpp | 7 + unittests/ADT/ArrayRefTest.cpp | 8 +- unittests/ADT/CMakeLists.txt | 1 + unittests/ADT/DenseMapTest.cpp | 10 +- unittests/ADT/DenseSetTest.cpp | 2 +- unittests/ADT/OptionalTest.cpp | 20 +- unittests/ADT/ScopeExitTest.cpp | 17 + unittests/ADT/StatisticTest.cpp | 106 + unittests/ADT/StringMapTest.cpp | 40 + unittests/ADT/StringRefTest.cpp | 12 +- unittests/ADT/StringSwitchTest.cpp | 6 +- unittests/ADT/TripleTest.cpp | 34 +- unittests/Analysis/MemorySSA.cpp | 90 + unittests/Analysis/ScalarEvolutionTest.cpp | 102 + unittests/Analysis/ValueLatticeTest.cpp | 116 +- unittests/Bitcode/BitReaderTest.cpp | 2 +- unittests/CodeGen/GlobalISel/CMakeLists.txt | 9 +- unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp | 167 +- unittests/CodeGen/GlobalISel/PatternMatchTest.cpp | 413 + unittests/CodeGen/MachineInstrTest.cpp | 23 + unittests/CodeGen/MachineOperandTest.cpp | 16 +- unittests/DebugInfo/PDB/HashTableTest.cpp | 41 + unittests/DebugInfo/PDB/PDBApiTest.cpp | 36 +- unittests/ExecutionEngine/Orc/CMakeLists.txt | 2 + .../Orc/CompileOnDemandLayerTest.cpp | 17 +- unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp | 328 + .../ExecutionEngine/Orc/LazyEmittingLayerTest.cpp | 10 +- .../ExecutionEngine/Orc/LegacyAPIInteropTest.cpp | 144 + .../Orc/ObjectTransformLayerTest.cpp | 126 +- unittests/ExecutionEngine/Orc/OrcCAPITest.cpp | 13 +- .../Orc/RTDyldObjectLinkingLayerTest.cpp | 128 +- .../ExecutionEngine/Orc/RemoteObjectLayerTest.cpp | 34 +- unittests/FuzzMutate/RandomIRBuilderTest.cpp | 30 + unittests/FuzzMutate/StrategiesTest.cpp | 47 +- unittests/IR/AttributesTest.cpp | 70 + unittests/IR/CMakeLists.txt | 1 + unittests/IR/DebugTypeODRUniquingTest.cpp | 22 +- unittests/IR/DeferredDominanceTest.cpp | 344 + unittests/IR/DominatorTreeBatchUpdatesTest.cpp | 95 + unittests/IR/DominatorTreeTest.cpp | 59 +- unittests/IR/IRBuilderTest.cpp | 17 + unittests/IR/MetadataTest.cpp | 123 +- unittests/MI/LiveIntervalTest.cpp | 37 +- unittests/Option/OptionParsingTest.cpp | 2 + unittests/Option/Opts.td | 1 + unittests/Support/AllocatorTest.cpp | 2 +- unittests/Support/CMakeLists.txt | 2 + unittests/Support/CheckedArithmeticTest.cpp | 71 + unittests/Support/CommandLineTest.cpp | 35 + unittests/Support/DJBTest.cpp | 96 + unittests/Support/ErrorOrTest.cpp | 4 +- unittests/Support/ManagedStatic.cpp | 6 +- unittests/Support/MemoryBufferTest.cpp | 4 +- unittests/Support/Path.cpp | 19 + unittests/Support/TargetParserTest.cpp | 63 +- unittests/Support/YAMLIOTest.cpp | 4 + .../Transforms/Scalar/LoopPassManagerTest.cpp | 12 +- unittests/Transforms/Utils/BasicBlockUtils.cpp | 52 + unittests/Transforms/Utils/CMakeLists.txt | 1 + unittests/Transforms/Utils/Cloning.cpp | 100 +- unittests/Transforms/Utils/Local.cpp | 315 +- utils/FileCheck/FileCheck.cpp | 3 + utils/TableGen/AsmMatcherEmitter.cpp | 261 +- utils/TableGen/CodeGenMapTable.cpp | 7 +- utils/TableGen/CodeGenSchedule.cpp | 103 +- utils/TableGen/CodeGenSchedule.h | 1 - utils/TableGen/CodeGenTarget.cpp | 18 +- utils/TableGen/CodeGenTarget.h | 8 + utils/TableGen/FixedLenDecoderEmitter.cpp | 25 +- utils/TableGen/GlobalISelEmitter.cpp | 180 +- utils/TableGen/InstrInfoEmitter.cpp | 9 +- utils/TableGen/SubtargetEmitter.cpp | 68 +- utils/TableGen/X86DisassemblerTables.cpp | 8 +- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp | 20 +- utils/TableGen/X86RecognizableInstr.cpp | 31 +- utils/TableGen/X86RecognizableInstr.h | 14 +- .../llvm => utils/UpdateTestChecks}/__init__.py | 0 utils/UpdateTestChecks/asm.py | 233 + utils/UpdateTestChecks/common.py | 212 + utils/bugpoint_gisel_reducer.py | 146 + utils/docker/debian8/build/Dockerfile | 10 +- utils/docker/scripts/build_install_llvm.sh | 4 +- utils/emacs/llvm-mode.el | 11 +- utils/lit/lit/TestRunner.py | 123 +- utils/lit/lit/TestingConfig.py | 2 +- utils/lit/lit/llvm/config.py | 5 +- .../tests/Inputs/shtest-shell/diff-r-error-0.txt | 8 + .../tests/Inputs/shtest-shell/diff-r-error-1.txt | 9 + .../tests/Inputs/shtest-shell/diff-r-error-2.txt | 7 + .../tests/Inputs/shtest-shell/diff-r-error-3.txt | 7 + .../tests/Inputs/shtest-shell/diff-r-error-4.txt | 8 + .../tests/Inputs/shtest-shell/diff-r-error-5.txt | 8 + .../tests/Inputs/shtest-shell/diff-r-error-6.txt | 8 + utils/lit/tests/Inputs/shtest-shell/diff-r.txt | 20 + utils/lit/tests/max-failures.py | 2 +- utils/lit/tests/shtest-shell.py | 57 +- utils/lit/tests/xunit-output.py | 2 +- utils/release/build_llvm_package.bat | 14 +- utils/release/test-release.sh | 10 +- utils/unicode-case-fold.py | 137 + .../googletest/include/gtest/gtest-message.h | 43 +- .../googletest/include/gtest/gtest-printers.h | 3 +- .../include/gtest/internal/custom/raw-ostream.h | 74 + .../include/gtest/internal/gtest-filepath.h | 2 +- utils/unittest/googletest/src/gtest-filepath.cc | 2 +- utils/unittest/googletest/src/gtest-port.cc | 2 +- utils/update_cc_test_checks.py | 242 + utils/update_llc_test_checks.py | 305 +- utils/update_mir_test_checks.py | 61 +- utils/update_test_checks.py | 205 +- utils/vim/syntax/llvm.vim | 1 + 4766 files changed, 365528 insertions(+), 140342 deletions(-) create mode 100644 include/llvm/Analysis/SyntheticCountsUtils.h create mode 100644 include/llvm/CodeGen/AccelTable.h delete mode 100644 include/llvm/CodeGen/ExecutionDepsFix.h create mode 100644 include/llvm/CodeGen/ExecutionDomainFix.h create mode 100644 include/llvm/CodeGen/GlobalISel/Combiner.h create mode 100644 include/llvm/CodeGen/GlobalISel/CombinerHelper.h create mode 100644 include/llvm/CodeGen/GlobalISel/CombinerInfo.h create mode 100644 include/llvm/CodeGen/GlobalISel/MIPatternMatch.h create mode 100644 include/llvm/CodeGen/LoopTraversal.h create mode 100644 include/llvm/CodeGen/ReachingDefAnalysis.h create mode 100644 include/llvm/DebugInfo/DWARF/DWARFAddressRange.h create mode 100644 include/llvm/DebugInfo/DWARF/DWARFDebugRnglists.h create mode 100644 include/llvm/ExecutionEngine/Orc/Core.h create mode 100644 include/llvm/ExecutionEngine/Orc/Legacy.h create mode 100644 include/llvm/MC/MCAsmMacro.h create mode 100644 include/llvm/Support/CheckedArithmetic.h create mode 100644 include/llvm/Support/DJB.h create mode 100644 include/llvm/Transforms/AggressiveInstCombine/AggressiveInstCombine.h create mode 100644 include/llvm/Transforms/IPO/SyntheticCountsPropagation.h create mode 100644 lib/Analysis/SyntheticCountsUtils.cpp create mode 100644 lib/CodeGen/AsmPrinter/AccelTable.cpp delete mode 100644 lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp delete mode 100644 lib/CodeGen/AsmPrinter/DwarfAccelTable.h create mode 100644 lib/CodeGen/AsmPrinter/WinCFGuard.cpp create mode 100644 lib/CodeGen/AsmPrinter/WinCFGuard.h create mode 100644 lib/CodeGen/BreakFalseDeps.cpp delete mode 100644 lib/CodeGen/ExecutionDepsFix.cpp create mode 100644 lib/CodeGen/ExecutionDomainFix.cpp create mode 100644 lib/CodeGen/GlobalISel/Combiner.cpp create mode 100644 lib/CodeGen/GlobalISel/CombinerHelper.cpp create mode 100644 lib/CodeGen/GlobalISel/LegalityPredicates.cpp create mode 100644 lib/CodeGen/GlobalISel/LegalizeMutations.cpp create mode 100644 lib/CodeGen/IndirectBrExpandPass.cpp create mode 100644 lib/CodeGen/LoopTraversal.cpp create mode 100644 lib/CodeGen/ReachingDefAnalysis.cpp create mode 100644 lib/DebugInfo/DWARF/DWARFAddressRange.cpp create mode 100644 lib/DebugInfo/DWARF/DWARFDebugRnglists.cpp create mode 100644 lib/ExecutionEngine/Orc/Core.cpp create mode 100644 lib/ExecutionEngine/Orc/Legacy.cpp create mode 100644 lib/MC/MCAsmMacro.cpp create mode 100644 lib/Support/DJB.cpp create mode 100644 lib/Support/UnicodeCaseFold.cpp create mode 100644 lib/Target/AArch64/AArch64SchedExynosM1.td create mode 100644 lib/Target/AArch64/AArch64SchedExynosM3.td delete mode 100644 lib/Target/AArch64/AArch64SchedM1.td create mode 100644 lib/Target/BPF/BPFMIPeephole.cpp create mode 100644 lib/Target/Hexagon/HexagonCallingConv.td create mode 100644 lib/Target/Hexagon/HexagonPatternsHVX.td create mode 100644 lib/Target/Hexagon/HexagonVExtract.cpp create mode 100644 lib/Target/Mips/MipsCallLowering.cpp create mode 100644 lib/Target/Mips/MipsCallLowering.h create mode 100644 lib/Target/Mips/MipsInstructionSelector.cpp create mode 100644 lib/Target/Mips/MipsLegalizerInfo.cpp create mode 100644 lib/Target/Mips/MipsLegalizerInfo.h create mode 100644 lib/Target/Mips/MipsRegisterBankInfo.cpp create mode 100644 lib/Target/Mips/MipsRegisterBankInfo.h delete mode 100644 lib/Target/PowerPC/PPCMachineBasicBlockUtils.h create mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp create mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h create mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp create mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h create mode 100644 lib/Target/RISCV/RISCVMachineFunctionInfo.h delete mode 100644 lib/Target/X86/README-UNIMPLEMENTED.txt create mode 100644 lib/Target/X86/X86IndirectBranchTracking.cpp create mode 100644 lib/Target/X86/X86RetpolineThunks.cpp create mode 100644 lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp create mode 100644 lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h create mode 100644 lib/Transforms/AggressiveInstCombine/CMakeLists.txt create mode 100644 lib/Transforms/AggressiveInstCombine/LLVMBuild.txt create mode 100644 lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp create mode 100644 lib/Transforms/IPO/BlockExtractor.cpp create mode 100644 lib/Transforms/IPO/SyntheticCountsPropagation.cpp create mode 100644 test/Analysis/BasicAA/pr35843.ll create mode 100644 test/Analysis/GlobalsModRef/pr35899-dbg-value.ll create mode 100644 test/Analysis/Lint/memintrin.ll create mode 100644 test/Analysis/ScalarEvolution/pr35890.ll create mode 100644 test/Analysis/ScalarEvolution/unknown_phis.ll create mode 100644 test/Analysis/TypeBasedAliasAnalysis/aggregates.ll create mode 100644 test/Analysis/TypeBasedAliasAnalysis/tbaa-path-new.ll create mode 100644 test/Analysis/ValueTracking/select-pattern.ll create mode 100644 test/Assembler/DIEnumerator.ll create mode 100644 test/Assembler/call-nonzero-program-addrspace-2.ll create mode 100644 test/Assembler/call-nonzero-program-addrspace.ll create mode 100644 test/Assembler/datalayout-program-addrspace.ll create mode 100644 test/Assembler/drop-debug-info-nonzero-alloca.ll delete mode 100644 test/Assembler/ifunc-dsolocal-daig.ll create mode 100644 test/Assembler/ifunc-dsolocal.ll create mode 100644 test/Assembler/invalid-datalayout-program-addrspace.ll create mode 100644 test/Assembler/invalid-disubrange-count-node.ll create mode 100644 test/Assembler/invoke-nonzero-program-addrspace.ll create mode 100644 test/Bitcode/disubrange-v0.ll create mode 100644 test/Bitcode/disubrange-v0.ll.bc create mode 100644 test/Bitcode/disubrange.ll create mode 100644 test/Bitcode/metadata-source.ll create mode 100644 test/Bitcode/metadata-source.ll.bc create mode 100644 test/Bitcode/thinlto-deadstrip-flag.ll create mode 100644 test/Bitcode/thinlto-function-summary-callgraph-relbf.ll create mode 100644 test/Bitcode/upgrade-dbg-checksum.ll create mode 100644 test/Bitcode/upgrade-dbg-checksum.ll.bc create mode 100644 test/Bitcode/upgrade-memory-intrinsics.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/select-mul.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir create mode 100644 test/CodeGen/AArch64/aarch64-vuzp.ll create mode 100644 test/CodeGen/AArch64/big-callframe.ll create mode 100644 test/CodeGen/AArch64/copy-zero-reg.ll create mode 100644 test/CodeGen/AArch64/copyprop.mir create mode 100644 test/CodeGen/AArch64/expand-select.ll create mode 100644 test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir create mode 100644 test/CodeGen/AArch64/misched-fusion-addr.ll create mode 100644 test/CodeGen/AArch64/misched-fusion-csel.ll create mode 100644 test/CodeGen/AArch64/spill-fold.mir create mode 100644 test/CodeGen/AArch64/strqu.ll create mode 100644 test/CodeGen/AArch64/sub1.ll create mode 100644 test/CodeGen/AArch64/taildup-cfi.ll create mode 100644 test/CodeGen/AArch64/win-alloca.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-maxnum.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-minnum.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir create mode 100644 test/CodeGen/AMDGPU/alloca.ll create mode 100644 test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll create mode 100644 test/CodeGen/AMDGPU/buffer-schedule.ll create mode 100644 test/CodeGen/AMDGPU/constant-address-space-32bit.ll create mode 100644 test/CodeGen/AMDGPU/ctpop16.ll create mode 100644 test/CodeGen/AMDGPU/debug-value2.ll create mode 100644 test/CodeGen/AMDGPU/elf-header-flags-mach.ll create mode 100644 test/CodeGen/AMDGPU/elf-header-flags-xnack.ll create mode 100644 test/CodeGen/AMDGPU/elf-header-osabi.ll delete mode 100644 test/CodeGen/AMDGPU/elf-header.ll create mode 100644 test/CodeGen/AMDGPU/fold-imm-f16-f32.mir create mode 100644 test/CodeGen/AMDGPU/fold-implicit-operand.mir create mode 100644 test/CodeGen/AMDGPU/fold-multiple.mir create mode 100644 test/CodeGen/AMDGPU/image-schedule.ll create mode 100644 test/CodeGen/AMDGPU/invalid-alloca.ll create mode 100644 test/CodeGen/AMDGPU/lds_atomic_f32.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll create mode 100644 test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir create mode 100644 test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir create mode 100644 test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nont [...] create mode 100644 test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nont [...] create mode 100644 test/CodeGen/AMDGPU/merge-load-store-physreg.mir create mode 100644 test/CodeGen/AMDGPU/merge-load-store-vreg.mir create mode 100644 test/CodeGen/AMDGPU/postra-norename.mir create mode 100644 test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll create mode 100644 test/CodeGen/AMDGPU/unpack-half.ll create mode 100644 test/CodeGen/AMDGPU/waitcnt-no-redundant.mir create mode 100644 test/CodeGen/ARM/2018-02-13-PR36079.ll create mode 100644 test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir create mode 100644 test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir create mode 100644 test/CodeGen/ARM/GlobalISel/select-pr35926.mir create mode 100644 test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir create mode 100644 test/CodeGen/ARM/PR35379.ll create mode 100644 test/CodeGen/ARM/coff-no-dead-strip.ll create mode 100644 test/CodeGen/ARM/dsp-mlal.ll create mode 100644 test/CodeGen/ARM/fp16-instructions.ll create mode 100644 test/CodeGen/ARM/fp16-litpool-arm.mir create mode 100644 test/CodeGen/ARM/fp16-litpool-thumb.mir create mode 100644 test/CodeGen/ARM/fp16-litpool2-arm.mir create mode 100644 test/CodeGen/ARM/fp16-litpool3-arm.mir create mode 100644 test/CodeGen/ARM/fpvcvtr.ll create mode 100644 test/CodeGen/ARM/global-merge-dllexport.ll create mode 100644 test/CodeGen/ARM/ifcvt_canFallThroughTo.mir create mode 100644 test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir create mode 100644 test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir create mode 100644 test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir create mode 100644 test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir create mode 100644 test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir create mode 100644 test/CodeGen/ARM/inlineasm-error-t-toofewregs.ll create mode 100644 test/CodeGen/ARM/overflow-intrinsic-optimizations.ll create mode 100644 test/CodeGen/ARM/peephole-phi.mir create mode 100644 test/CodeGen/ARM/sat-to-bitop.ll create mode 100644 test/CodeGen/ARM/splitkit.ll create mode 100644 test/CodeGen/ARM/stack-size-section.ll delete mode 100644 test/CodeGen/ARM/su-addsub-overflow.ll create mode 100644 test/CodeGen/ARM/trap-unreachable.ll create mode 100644 test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll create mode 100644 test/CodeGen/BPF/32-bit-subreg-alu.ll create mode 100644 test/CodeGen/BPF/32-bit-subreg-cond-select.ll create mode 100644 test/CodeGen/BPF/32-bit-subreg-load-store.ll create mode 100644 test/CodeGen/BPF/32-bit-subreg-peephole.ll create mode 100644 test/CodeGen/BPF/remove_truncate_4.ll create mode 100644 test/CodeGen/BPF/remove_truncate_5.ll create mode 100644 test/CodeGen/Generic/dwarf-md5.ll create mode 100644 test/CodeGen/Generic/dwarf-source.ll create mode 100644 test/CodeGen/Hexagon/autohvx/align2-128b.ll create mode 100644 test/CodeGen/Hexagon/autohvx/align2-64b.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-build-undef.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-const-splat.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-const-vector.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-qfalse.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll create mode 100644 test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll create mode 100644 test/CodeGen/Hexagon/autohvx/shift-128b.ll create mode 100644 test/CodeGen/Hexagon/autohvx/shift-64b.ll create mode 100644 test/CodeGen/Hexagon/bit-addr-align.mir create mode 100644 test/CodeGen/Hexagon/cext-opt-range-assert.mir create mode 100644 test/CodeGen/Hexagon/cext-opt-shifted-range.mir create mode 100644 test/CodeGen/Hexagon/constp-andir-global.mir create mode 100644 test/CodeGen/Hexagon/early-if-low8.mir create mode 100644 test/CodeGen/Hexagon/isel-global-offset-alignment.ll create mode 100644 test/CodeGen/Hexagon/isel-setcc-i1.ll create mode 100644 test/CodeGen/Hexagon/isel-vacopy.ll create mode 100644 test/CodeGen/Hexagon/newvaluejump-float.mir create mode 100644 test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir create mode 100644 test/CodeGen/Hexagon/vararg-formal.ll create mode 100644 test/CodeGen/Hexagon/vect/build-vect64.ll create mode 100644 test/CodeGen/Hexagon/vect/setcc-v2i32.ll create mode 100644 test/CodeGen/Hexagon/vect/shuff-32.ll create mode 100644 test/CodeGen/Hexagon/vect/shuff-64.ll create mode 100644 test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll create mode 100644 test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll create mode 100644 test/CodeGen/Hexagon/vect/zext-v4i1.ll create mode 100644 test/CodeGen/Hexagon/vextract-basic.mir create mode 100644 test/CodeGen/MIR/AArch64/addrspace-memoperands.mir create mode 100644 test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir create mode 100644 test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir delete mode 100644 test/CodeGen/MIR/AArch64/spill-fold.mir delete mode 100644 test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir delete mode 100644 test/CodeGen/MIR/AMDGPU/fold-multiple.mir delete mode 100644 test/CodeGen/MIR/AMDGPU/memory-legalizer-atomic-insert-end.mir delete mode 100644 test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands- [...] delete mode 100644 test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands- [...] delete mode 100644 test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands- [...] delete mode 100644 test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir delete mode 100644 test/CodeGen/MIR/ARM/ifcvt_canFallThroughTo.mir delete mode 100644 test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir delete mode 100644 test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir delete mode 100644 test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir delete mode 100644 test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir delete mode 100644 test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir delete mode 100644 test/CodeGen/MIR/X86/dynamic-regmask.ll delete mode 100644 test/CodeGen/MIR/X86/shrink_wrap_dbg_value.mir delete mode 100644 test/CodeGen/MIR/X86/simple-register-allocation-read-undef.mir delete mode 100644 test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir create mode 100644 test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll create mode 100644 test/CodeGen/Mips/GlobalISel/llvm-ir/ret.ll create mode 100644 test/CodeGen/Mips/dsp_msa_warning.ll create mode 100644 test/CodeGen/Mips/fastcc_byval.ll create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/calls.ll create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll create mode 100644 test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll create mode 100644 test/CodeGen/Mips/inlineasm-opcode-bad-y.ll create mode 100644 test/CodeGen/Mips/llvm-ir/abs.ll create mode 100644 test/CodeGen/Mips/llvm-ir/arith-fp.ll create mode 100644 test/CodeGen/Mips/llvm-ir/bitcast.ll create mode 100644 test/CodeGen/Mips/llvm-ir/cvt.ll create mode 100644 test/CodeGen/Mips/micromips-eva.mir create mode 100644 test/CodeGen/Mips/pr36061.ll create mode 100644 test/CodeGen/Mips/unsized-global.ll create mode 100644 test/CodeGen/NVPTX/read-global-variable-constant.ll create mode 100644 test/CodeGen/Nios2/add-sub.ll create mode 100644 test/CodeGen/Nios2/mul-div.ll create mode 100644 test/CodeGen/Nios2/shift-rotate.ll create mode 100644 test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll create mode 100644 test/CodeGen/PowerPC/coldcc.ll create mode 100644 test/CodeGen/PowerPC/coldcc2.ll create mode 100644 test/CodeGen/PowerPC/ctrloops-hot-exit.ll create mode 100644 test/CodeGen/PowerPC/fastcc_stacksize.ll create mode 100644 test/CodeGen/PowerPC/fp-int128-fp-combine.ll create mode 100644 test/CodeGen/PowerPC/memcmp-mergeexpand.ll create mode 100644 test/CodeGen/PowerPC/noPermuteFormasking.ll create mode 100644 test/CodeGen/PowerPC/non-simple-args-intrin.ll create mode 100644 test/CodeGen/PowerPC/pr33547.ll create mode 100644 test/CodeGen/PowerPC/pr36068.ll create mode 100644 test/CodeGen/PowerPC/pr36292.ll create mode 100644 test/CodeGen/RISCV/analyze-branch.ll create mode 100644 test/CodeGen/RISCV/branch-relaxation.ll create mode 100644 test/CodeGen/RISCV/frameaddr-returnaddr.ll create mode 100644 test/CodeGen/RISCV/get-setcc-result-type.ll create mode 100644 test/CodeGen/RISCV/inline-asm.ll create mode 100644 test/CodeGen/RISCV/large-stack.ll create mode 100644 test/CodeGen/RISCV/vararg.ll create mode 100644 test/CodeGen/SystemZ/Large/branch-01.ll create mode 100644 test/CodeGen/SystemZ/anyregcc-novec.ll create mode 100644 test/CodeGen/SystemZ/anyregcc-vec.ll create mode 100644 test/CodeGen/SystemZ/anyregcc.ll create mode 100644 test/CodeGen/SystemZ/asm-19.ll create mode 100644 test/CodeGen/SystemZ/load-and-test.mir create mode 100644 test/CodeGen/SystemZ/loop-04.ll create mode 100644 test/CodeGen/SystemZ/patchpoint-invoke.ll create mode 100644 test/CodeGen/SystemZ/patchpoint.ll create mode 100644 test/CodeGen/SystemZ/pr36164.ll create mode 100644 test/CodeGen/SystemZ/setcc-03.ll create mode 100644 test/CodeGen/SystemZ/setcc-04.ll create mode 100644 test/CodeGen/SystemZ/stack-size-section.ll create mode 100644 test/CodeGen/SystemZ/stackmap-nops.ll create mode 100644 test/CodeGen/SystemZ/stackmap-shadow-optimization.ll create mode 100644 test/CodeGen/SystemZ/stackmap.ll create mode 100644 test/CodeGen/SystemZ/store_nonbytesized_vecs.ll create mode 100644 test/CodeGen/SystemZ/vec-load-element.ll create mode 100644 test/CodeGen/Thumb/PR35481.ll create mode 100644 test/CodeGen/Thumb/frame-access.ll create mode 100644 test/CodeGen/Thumb/mvn.ll create mode 100644 test/CodeGen/Thumb/pr35836.ll create mode 100644 test/CodeGen/Thumb/pr35836_2.ll create mode 100644 test/CodeGen/Thumb/stm-scavenging.ll create mode 100644 test/CodeGen/Thumb2/cmp-frame.ll delete mode 100644 test/CodeGen/WebAssembly/comdat.ll create mode 100644 test/CodeGen/WebAssembly/i128-returned.ll create mode 100644 test/CodeGen/WebAssembly/import-module.ll create mode 100644 test/CodeGen/WebAssembly/libcalls.ll create mode 100644 test/CodeGen/WinCFGuard/cfguard.ll copy test/CodeGen/{MIR/X86 => WinCFGuard}/lit.local.cfg (100%) create mode 100644 test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir create mode 100644 test/CodeGen/X86/GlobalISel/inttoptr.ll delete mode 100644 test/CodeGen/X86/GlobalISel/legalize-GV.mir create mode 100644 test/CodeGen/X86/GlobalISel/ptrtoint.ll delete mode 100644 test/CodeGen/X86/GlobalISel/select-frameIndex.mir create mode 100644 test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir create mode 100644 test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir create mode 100644 test/CodeGen/X86/add-i64.ll create mode 100644 test/CodeGen/X86/addcarry2.ll create mode 100644 test/CodeGen/X86/asm-reject-rex.ll create mode 100644 test/CodeGen/X86/asm-reject-xmm16.ll create mode 100644 test/CodeGen/X86/bad-tls-fold.mir create mode 100644 test/CodeGen/X86/bitcnt-false-dep.ll create mode 100644 test/CodeGen/X86/cmpxchg8b.ll create mode 100644 test/CodeGen/X86/coff-no-dead-strip.ll create mode 100644 test/CodeGen/X86/combine-fabs.ll create mode 100644 test/CodeGen/X86/combine-smax.ll create mode 100644 test/CodeGen/X86/combine-smin.ll create mode 100644 test/CodeGen/X86/combine-umax.ll create mode 100644 test/CodeGen/X86/combine-umin.ll create mode 100644 test/CodeGen/X86/dynamic-regmask.ll create mode 100644 test/CodeGen/X86/fp-arith.ll create mode 100644 test/CodeGen/X86/haddsub-3.ll create mode 100644 test/CodeGen/X86/indirect-branch-tracking.ll create mode 100644 test/CodeGen/X86/inline-asm-modifier-V.ll create mode 100644 test/CodeGen/X86/legalize-shift.ll create mode 100644 test/CodeGen/X86/machine-outliner-disubprogram.ll create mode 100644 test/CodeGen/X86/memcmp-mergeexpand.ll create mode 100644 test/CodeGen/X86/mmx-build-vector.ll create mode 100644 test/CodeGen/X86/mmx-fold-zero.ll create mode 100644 test/CodeGen/X86/no-stack-arg-probe.ll rename test/CodeGen/{MIR => }/X86/opt_phis.mir (100%) delete mode 100644 test/CodeGen/X86/pr12312.ll create mode 100644 test/CodeGen/X86/pr29222.ll create mode 100644 test/CodeGen/X86/pr33747.ll create mode 100644 test/CodeGen/X86/pr34592.ll create mode 100644 test/CodeGen/X86/pr35316.ll create mode 100644 test/CodeGen/X86/pr35761.ll create mode 100644 test/CodeGen/X86/pr35763.ll create mode 100644 test/CodeGen/X86/pr35918.ll create mode 100644 test/CodeGen/X86/pr35972.ll create mode 100644 test/CodeGen/X86/pr35982.ll create mode 100644 test/CodeGen/X86/pr36199.ll create mode 100644 test/CodeGen/X86/pr36553.ll delete mode 100644 test/CodeGen/X86/pr37563.ll create mode 100644 test/CodeGen/X86/prefer-avx256-lzcnt.ll create mode 100644 test/CodeGen/X86/prefer-avx256-mask-extend.ll create mode 100644 test/CodeGen/X86/prefer-avx256-mask-shuffle.ll create mode 100644 test/CodeGen/X86/prefer-avx256-popcnt.ll create mode 100644 test/CodeGen/X86/prefer-avx256-shift.ll create mode 100644 test/CodeGen/X86/prefer-avx256-trunc.ll create mode 100644 test/CodeGen/X86/prefer-avx256-wide-mul.ll create mode 100644 test/CodeGen/X86/ptest.ll create mode 100644 test/CodeGen/X86/rdpid-schedule.ll create mode 100644 test/CodeGen/X86/rdpid.ll create mode 100644 test/CodeGen/X86/regalloc-advanced-split-cost.ll create mode 100644 test/CodeGen/X86/required-vector-width.ll create mode 100644 test/CodeGen/X86/retpoline-external.ll create mode 100644 test/CodeGen/X86/retpoline-regparm.ll create mode 100644 test/CodeGen/X86/retpoline.ll create mode 100644 test/CodeGen/X86/safestack_inline.ll create mode 100644 test/CodeGen/X86/schedule-x86-64-shld.ll create mode 100644 test/CodeGen/X86/select-1-or-neg1.ll create mode 100644 test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll create mode 100644 test/CodeGen/X86/shrink_wrap_dbg_value.mir create mode 100644 test/CodeGen/X86/simple-register-allocation-read-undef.mir create mode 100644 test/CodeGen/X86/test-vs-bittest.ll create mode 100644 test/CodeGen/X86/trunc-subvector.ll create mode 100644 test/CodeGen/X86/undef-globals-bss.ll create mode 100644 test/CodeGen/X86/undef-ops.ll create mode 100644 test/CodeGen/X86/unreachable-mbb-undef-phi.mir create mode 100644 test/CodeGen/X86/vec_cast3.ll create mode 100644 test/CodeGen/X86/vector-compare-simplify.ll create mode 100644 test/CodeGen/X86/vector-trunc-packus.ll create mode 100644 test/CodeGen/X86/vector-trunc-ssat.ll create mode 100644 test/CodeGen/X86/vector-trunc-usat.ll create mode 100644 test/CodeGen/X86/vmaskmov-offset.ll create mode 100644 test/CodeGen/X86/x86-64-bittest-logic.ll create mode 100644 test/CodeGen/X86/zext-demanded.ll create mode 100644 test/DebugInfo/COFF/const-unnamed-member.ll create mode 100644 test/DebugInfo/COFF/type-quals.ll create mode 100644 test/DebugInfo/COFF/types-cvarargs.ll create mode 100644 test/DebugInfo/Generic/debug-info-enum.ll create mode 100644 test/DebugInfo/Generic/discriminated-union.ll create mode 100644 test/DebugInfo/Generic/disubrange_vla.ll create mode 100644 test/DebugInfo/Generic/disubrange_vla_no_dbgvalue.ll create mode 100644 test/DebugInfo/Generic/inlined-strings.ll create mode 100644 test/DebugInfo/Generic/string-offsets-form.ll create mode 100644 test/DebugInfo/Generic/univariant-discriminated-union.ll create mode 100644 test/DebugInfo/Inputs/split-dwarf-no-skel-address.dwo create mode 100644 test/DebugInfo/Inputs/split-dwarf-no-skel-address.o create mode 100644 test/DebugInfo/MIR/Mips/last-inst-bundled.mir copy test/{CodeGen => DebugInfo/MIR}/Mips/lit.local.cfg (100%) create mode 100644 test/DebugInfo/MIR/X86/kill-after-spill.mir create mode 100644 test/DebugInfo/X86/accel-tables.ll create mode 100644 test/DebugInfo/X86/dwarfdump-debug-names.s create mode 100644 test/DebugInfo/X86/empty_macinfo.ll create mode 100644 test/DebugInfo/X86/fragment-offset-order.ll create mode 100644 test/DebugInfo/X86/global-sra-fp80-array.ll create mode 100644 test/DebugInfo/X86/global-sra-fp80-struct.ll create mode 100644 test/DebugInfo/X86/invalid-prologue-end.ll create mode 100644 test/DebugInfo/X86/linear-dbg-value.ll create mode 100644 test/DebugInfo/X86/live-debug-vars-discard-invalid.mir create mode 100644 test/DebugInfo/X86/sdag-combine.ll create mode 100644 test/DebugInfo/X86/string-offsets-multiple-cus.ll create mode 100644 test/DebugInfo/X86/string-offsets-table.ll create mode 100644 test/DebugInfo/X86/strip-broken-debuginfo.ll create mode 100644 test/DebugInfo/X86/vla-dependencies.ll create mode 100644 test/DebugInfo/X86/vla-global.ll create mode 100644 test/DebugInfo/X86/vla-multi.ll create mode 100644 test/DebugInfo/llvm-symbolizer-split-dwarf-no-skel-address.test create mode 100644 test/ExecutionEngine/RuntimeDyld/X86/COFF_x86_64_IMGREL.s create mode 100644 test/Feature/elf-linker-options.ll create mode 100644 test/FileCheck/check-empty2.txt create mode 100644 test/Instrumentation/DataFlowSanitizer/custom_fun_callback_attr [...] create mode 100644 test/Instrumentation/DataFlowSanitizer/custom_fun_varargs_attri [...] create mode 100644 test/Instrumentation/HWAddressSanitizer/alloca.ll create mode 100644 test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll create mode 100644 test/Instrumentation/HWAddressSanitizer/kernel-inline.ll create mode 100644 test/Instrumentation/HWAddressSanitizer/kernel.ll create mode 100644 test/Instrumentation/InstrProfiling/early-exit.ll create mode 100644 test/LTO/Resolution/X86/Inputs/not-prevailing.ll create mode 100644 test/LTO/Resolution/X86/cache-dso-local.ll create mode 100644 test/LTO/Resolution/X86/cache-dso-local2.ll create mode 100644 test/LTO/Resolution/X86/cache-prevailing.ll create mode 100644 test/LTO/Resolution/X86/not-prevailing-alias.ll create mode 100644 test/LTO/Resolution/X86/not-prevailing-variables.ll create mode 100644 test/LTO/Resolution/X86/not-prevailing.ll create mode 100644 test/LTO/Resolution/X86/setting-dso-local.ll create mode 100644 test/Linker/Inputs/metadata-source-a.ll create mode 100644 test/Linker/Inputs/metadata-source-b.ll create mode 100644 test/Linker/metadata-source.ll create mode 100644 test/MC/AArch64/SVE/addpl-diagnostics.s create mode 100644 test/MC/AArch64/SVE/addpl.s create mode 100644 test/MC/AArch64/SVE/addvl-diagnostics.s create mode 100644 test/MC/AArch64/SVE/addvl.s create mode 100644 test/MC/AArch64/SVE/and-diagnostics.s create mode 100644 test/MC/AArch64/SVE/and.s create mode 100644 test/MC/AArch64/SVE/dup-diagnostics.s create mode 100644 test/MC/AArch64/SVE/dup.s create mode 100644 test/MC/AArch64/SVE/mov-diagnostics.s create mode 100644 test/MC/AArch64/SVE/mov.s create mode 100644 test/MC/AArch64/SVE/ptrue-diagnostics.s create mode 100644 test/MC/AArch64/SVE/ptrue.s create mode 100644 test/MC/AArch64/SVE/ptrues-diagnostics.s create mode 100644 test/MC/AArch64/SVE/ptrues.s create mode 100644 test/MC/AArch64/SVE/rdvl-diagnostics.s create mode 100644 test/MC/AArch64/SVE/rdvl.s create mode 100644 test/MC/AArch64/csdb.s create mode 100644 test/MC/AMDGPU/buf-fmt-d16-packed.s create mode 100644 test/MC/AMDGPU/buf-fmt-d16-unpacked.s create mode 100644 test/MC/AMDGPU/hsa_isa_version_attrs.s create mode 100644 test/MC/AMDGPU/mimg-err.s create mode 100644 test/MC/AMDGPU/xnack-mask.s create mode 100644 test/MC/ARM/csdb-errors.s create mode 100644 test/MC/ARM/csdb.s create mode 100644 test/MC/ARM/type-directive-print.ll create mode 100644 test/MC/ARM/vmov-pair-diags.s create mode 100644 test/MC/AsmParser/debug-empty-source.s create mode 100644 test/MC/AsmParser/debug-no-source.s create mode 100644 test/MC/AsmParser/inline_macro_duplication.ll create mode 100644 test/MC/BPF/load-store-32.s create mode 100644 test/MC/COFF/symidx.s create mode 100644 test/MC/Disassembler/AArch64/csdb.txt create mode 100644 test/MC/Disassembler/AMDGPU/buf_fmt_packed_d16.txt create mode 100644 test/MC/Disassembler/AMDGPU/buf_fmt_unpacked_d16.txt create mode 100644 test/MC/Disassembler/ARM/csdb-arm.txt create mode 100644 test/MC/Disassembler/ARM/csdb-thumb.txt create mode 100644 test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt create mode 100644 test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt create mode 100644 test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt create mode 100644 test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt create mode 100644 test/MC/Disassembler/Mips/mips32/valid-fp64.txt create mode 100644 test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt create mode 100644 test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt create mode 100644 test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt create mode 100644 test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt create mode 100644 test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt create mode 100644 test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt create mode 100644 test/MC/Disassembler/X86/amd3dnow.txt create mode 100644 test/MC/ELF/debug-file-options.s create mode 100644 test/MC/ELF/debug-md5-err.s create mode 100644 test/MC/ELF/debug-md5.s create mode 100644 test/MC/ELF/debug-source.s create mode 100644 test/MC/ELF/uleb-ehtable.s create mode 100644 test/MC/Hexagon/J2_trap1_dep.s create mode 100644 test/MC/Hexagon/guest.s create mode 100644 test/MC/Mips/micromips/valid-fp64.s create mode 100644 test/MC/Mips/mips32r2/valid-fp64.s create mode 100644 test/MC/Mips/mips32r3/valid-fp64.s create mode 100644 test/MC/Mips/mips32r5/valid-fp64.s create mode 100644 test/MC/Mips/unsupported-relocation.s create mode 100644 test/MC/RISCV/cnop.s create mode 100644 test/MC/RISCV/csr-aliases.s create mode 100644 test/MC/RISCV/elf-flags.s create mode 100644 test/MC/RISCV/rv32-relaxation.s create mode 100644 test/MC/RISCV/rv64-relaxation.s create mode 100644 test/MC/RISCV/rv64dc-valid.s create mode 100644 test/MC/WebAssembly/blockaddress.ll create mode 100644 test/MC/WebAssembly/comdat.ll create mode 100644 test/MC/WebAssembly/global-ctor-dtor.ll delete mode 100644 test/MC/WebAssembly/init-fini-array.ll create mode 100644 test/MC/WebAssembly/libcall.ll create mode 100644 test/MC/X86/AVX512F_512-32.s create mode 100644 test/MC/X86/AVX512F_512-64.s create mode 100644 test/MC/X86/CET-32.s create mode 100644 test/MC/X86/CET-64.s create mode 100644 test/MC/X86/CLWB-32.s create mode 100644 test/MC/X86/CLWB-64.s create mode 100644 test/MC/X86/CLZERO-32.s create mode 100644 test/MC/X86/CLZERO-64.s create mode 100644 test/MC/X86/F16C-32.s create mode 100644 test/MC/X86/F16C-64.s create mode 100644 test/MC/X86/FXSAVE-32.s create mode 100644 test/MC/X86/FXSAVE-64.s create mode 100644 test/MC/X86/FXSAVE64-64.s create mode 100644 test/MC/X86/I186-32.s create mode 100644 test/MC/X86/I186-64.s create mode 100644 test/MC/X86/I286-32.s create mode 100644 test/MC/X86/I286-64.s create mode 100644 test/MC/X86/I386-32.s create mode 100644 test/MC/X86/I386-64.s create mode 100644 test/MC/X86/I486-32.s create mode 100644 test/MC/X86/I486-64.s create mode 100644 test/MC/X86/I86-32.s create mode 100644 test/MC/X86/I86-64.s create mode 100644 test/MC/X86/INVPCID-32.s create mode 100644 test/MC/X86/INVPCID-64.s create mode 100755 test/MC/X86/MMX-32.s create mode 100644 test/MC/X86/MMX-64.s create mode 100644 test/MC/X86/PKU-32.s create mode 100644 test/MC/X86/PKU-64.s create mode 100644 test/MC/X86/POPCNT-32.s create mode 100644 test/MC/X86/POPCNT-64.s create mode 100644 test/MC/X86/PPRO-32.s create mode 100644 test/MC/X86/PPRO-64.s create mode 100644 test/MC/X86/RTM.s create mode 100644 test/MC/X86/SGX-32.s create mode 100644 test/MC/X86/SGX-64.s create mode 100644 test/MC/X86/SHA-32.s create mode 100644 test/MC/X86/SHA-64.s create mode 100644 test/MC/X86/SVM-32.s create mode 100644 test/MC/X86/SVM-64.s create mode 100644 test/MC/X86/VMFUNC-32.s create mode 100644 test/MC/X86/VMFUNC-64.s create mode 100644 test/MC/X86/VTX-32.s create mode 100644 test/MC/X86/VTX-64.s create mode 100644 test/MC/X86/XSAVE-32.s create mode 100644 test/MC/X86/XSAVE-64.s create mode 100644 test/MC/X86/XSAVEC-32.s create mode 100644 test/MC/X86/XSAVEC-64.s create mode 100644 test/MC/X86/XSAVEOPT-32.s create mode 100644 test/MC/X86/XSAVEOPT-64.s create mode 100644 test/MC/X86/XSAVES-32.s create mode 100644 test/MC/X86/XSAVES-64.s create mode 100644 test/MC/X86/cfi-scope-unclosed.s create mode 100644 test/MC/X86/check-end-of-data-region.s create mode 100644 test/MC/X86/eval-fill.s create mode 100644 test/MC/X86/space-err.s create mode 100644 test/Object/AMDGPU/elf-header-flags-mach.yaml create mode 100644 test/Object/AMDGPU/elf-header-flags-xnack.yaml create mode 100644 test/Object/AMDGPU/elf-header-osabi.yaml delete mode 100644 test/Object/AMDGPU/elf32-r600-definitions.yaml delete mode 100644 test/Object/AMDGPU/elf64-amdgcn-amdhsa-definitions.yaml delete mode 100644 test/Object/AMDGPU/elf64-amdgcn-amdpal-definitions.yaml delete mode 100644 test/Object/AMDGPU/elf64-amdgcn-mesa3d-definitions.yaml delete mode 100644 test/Object/Inputs/invalid-sections-address-alignment.x86-64 create mode 100644 test/Object/wasm-duplicate-name.test create mode 100644 test/TableGen/MultiClass-defm-fail.td create mode 100644 test/TableGen/MultiClass-defm.td create mode 100644 test/TableGen/RelTest.td create mode 100644 test/TableGen/code.td create mode 100644 test/TableGen/foldl.td create mode 100644 test/TableGen/foreach-eval.td create mode 100644 test/TableGen/foreach-leak.td create mode 100644 test/TableGen/if-type.td create mode 100644 test/TableGen/size.td create mode 100644 test/TableGen/template-arg-dependency.td create mode 100644 test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll create mode 100644 test/ThinLTO/X86/Inputs/dicompositetype-unique2.ll create mode 100644 test/ThinLTO/X86/Inputs/dot-dumper.ll create mode 100644 test/ThinLTO/X86/dicompositetype-unique-alias.ll create mode 100644 test/ThinLTO/X86/dicompositetype-unique2.ll create mode 100644 test/ThinLTO/X86/dot-dumper.ll create mode 100644 test/ThinLTO/X86/linkonce_odr_unnamed_addr.ll create mode 100644 test/ThinLTO/X86/module_summary_graph_traits.ll create mode 100644 test/Transforms/AggressiveInstCombine/trunc_const_expr.ll create mode 100644 test/Transforms/AggressiveInstCombine/trunc_multi_uses.ll create mode 100644 test/Transforms/AggressiveInstCombine/trunc_unreachable_bb.ll create mode 100644 test/Transforms/ArgumentPromotion/musttail.ll create mode 100644 test/Transforms/ArgumentPromotion/naked_functions.ll create mode 100644 test/Transforms/BlockExtractor/extract-blocks.ll create mode 100644 test/Transforms/BlockExtractor/invalid-block.ll create mode 100644 test/Transforms/BlockExtractor/invalid-function.ll create mode 100644 test/Transforms/CallSiteSplitting/callsite-instructions-before-call.ll create mode 100644 test/Transforms/CallSiteSplitting/musttail.ll create mode 100644 test/Transforms/CallSiteSplitting/split-loop.ll create mode 100644 test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll create mode 100644 test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll create mode 100644 test/Transforms/Coroutines/coro-split-alloc.ll create mode 100644 test/Transforms/CorrelatedValuePropagation/pr35807.ll create mode 100644 test/Transforms/DeadArgElim/dbginfo-preserve-dbgloc.ll create mode 100644 test/Transforms/DeadArgElim/musttail-caller.ll create mode 100644 test/Transforms/DeadStoreElimination/debuginfo.ll create mode 100644 test/Transforms/EarlyCSE/debuginfo-dce.ll create mode 100644 test/Transforms/FunctionAttrs/naked_functions.ll create mode 100644 test/Transforms/GVN/pr36063.ll create mode 100644 test/Transforms/GlobalOpt/PowerPC/coldcc_coldsites.ll copy test/{Analysis/CostModel => Transforms/GlobalOpt}/PowerPC/lit.local.cfg (100%) create mode 100644 test/Transforms/GlobalOpt/coldcc_stress_test.ll create mode 100644 test/Transforms/GlobalOpt/musttail_cc.ll create mode 100644 test/Transforms/GlobalOpt/naked_functions.ll create mode 100644 test/Transforms/IPConstantProp/musttail-call.ll create mode 100644 test/Transforms/IPConstantProp/remove-call-inst.ll create mode 100644 test/Transforms/IRCE/optimistic_scev.ll create mode 100644 test/Transforms/IndVarSimplify/inner-loop.ll create mode 100644 test/Transforms/IndirectBrExpand/basic.ll delete mode 100644 test/Transforms/InstCombine/2008-05-22-NegValVector.ll delete mode 100644 test/Transforms/InstCombine/2017-07-07-UMul-ZExt.ll create mode 100644 test/Transforms/InstCombine/and-narrow.ll create mode 100644 test/Transforms/InstCombine/debuginfo-variables.ll create mode 100644 test/Transforms/InstCombine/fdiv-cos-sin.ll create mode 100644 test/Transforms/InstCombine/fdiv-sin-cos.ll create mode 100644 test/Transforms/InstCombine/gep-custom-dl.ll create mode 100644 test/Transforms/InstCombine/icmp-custom-dl.ll create mode 100644 test/Transforms/InstCombine/icmp-mul-zext.ll create mode 100644 test/Transforms/InstCombine/phi-timeout.ll delete mode 100644 test/Transforms/InstCombine/pr33765.ll create mode 100644 test/Transforms/InstCombine/pr36362.ll create mode 100644 test/Transforms/InstCombine/select-gep.ll create mode 100644 test/Transforms/InstCombine/should-change-type.ll create mode 100644 test/Transforms/InstCombine/struct-assign-tbaa-new.ll create mode 100644 test/Transforms/InstCombine/unsigned_saturated_sub.ll create mode 100644 test/Transforms/InstCombine/vector-udiv.ll create mode 100644 test/Transforms/InstCombine/vector-xor.ll create mode 100644 test/Transforms/InstSimplify/and-or-icmp-zero.ll delete mode 100644 test/Transforms/InstSimplify/exp-intrinsic.ll delete mode 100644 test/Transforms/InstSimplify/exp2-intrinsic.ll create mode 100644 test/Transforms/InstSimplify/fp-undef.ll create mode 100644 test/Transforms/InstSimplify/log-exp-intrinsic.ll delete mode 100644 test/Transforms/InstSimplify/log-intrinsic.ll delete mode 100644 test/Transforms/InstSimplify/log2-intrinsic.ll create mode 100644 test/Transforms/JumpThreading/ddt-crash.ll create mode 100644 test/Transforms/JumpThreading/ddt-crash2.ll create mode 100644 test/Transforms/JumpThreading/ddt-crash3.ll create mode 100644 test/Transforms/JumpThreading/ddt-crash4.ll create mode 100644 test/Transforms/JumpThreading/lvi-tristate.ll create mode 100644 test/Transforms/JumpThreading/pr36133.ll create mode 100644 test/Transforms/LCSSA/avoid-intrinsics-in-catchswitch.ll create mode 100644 test/Transforms/LoopDeletion/use-in-unreachable.ll create mode 100644 test/Transforms/LoopIdiom/struct-custom-dl.ll create mode 100644 test/Transforms/LoopIdiom/unroll-custom-dl.ll create mode 100644 test/Transforms/LoopInterchange/interchange-latch-no-exit.ll create mode 100644 test/Transforms/LoopInterchange/interchange-no-deps.ll create mode 100644 test/Transforms/LoopStrengthReduce/X86/macro-fuse-cmp.ll create mode 100644 test/Transforms/LoopVectorize/AArch64/pr36032.ll create mode 100644 test/Transforms/LoopVectorize/ARM/sphinx.ll create mode 100644 test/Transforms/LoopVectorize/X86/pr35432.ll create mode 100644 test/Transforms/LoopVectorize/interleaved-acess-with-remarks.ll create mode 100644 test/Transforms/LoopVectorize/pr35743.ll create mode 100644 test/Transforms/LoopVectorize/pr35773.ll create mode 100644 test/Transforms/LowerTypeTests/Inputs/blockaddr-import.yaml create mode 100644 test/Transforms/LowerTypeTests/Inputs/import-alias.yaml create mode 100644 test/Transforms/LowerTypeTests/blockaddr-import.ll create mode 100644 test/Transforms/LowerTypeTests/export-alias.ll create mode 100644 test/Transforms/LowerTypeTests/import-alias.ll create mode 100644 test/Transforms/MergeICmps/X86/last-block-produce-no-value.ll create mode 100644 test/Transforms/MergeICmps/X86/multiple-blocks-does-work.ll create mode 100644 test/Transforms/MergeICmps/X86/two-complex-bb.ll create mode 100644 test/Transforms/NewGVN/phi-of-ops-move-block.ll create mode 100644 test/Transforms/NewGVN/pr33367.ll create mode 100644 test/Transforms/PGOProfile/thinlto_samplepgo_icp_droppeddead.ll create mode 100644 test/Transforms/PhaseOrdering/scev-custom-dl.ll create mode 100644 test/Transforms/RewriteStatepointsForGC/unreachable-regression.ll create mode 100644 test/Transforms/SLPVectorizer/AArch64/matmul.ll create mode 100644 test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll create mode 100644 test/Transforms/SLPVectorizer/ARM/extract-insert.ll create mode 100644 test/Transforms/SLPVectorizer/X86/PR35628_1.ll create mode 100644 test/Transforms/SLPVectorizer/X86/PR35628_2.ll create mode 100644 test/Transforms/SLPVectorizer/X86/PR35777.ll create mode 100644 test/Transforms/SLPVectorizer/X86/PR35865.ll create mode 100644 test/Transforms/SLPVectorizer/X86/PR36280.ll create mode 100644 test/Transforms/SLPVectorizer/X86/external_user_jumbled_load.ll create mode 100644 test/Transforms/SLPVectorizer/X86/extract-shuffle.ll create mode 100644 test/Transforms/SLPVectorizer/X86/jumbled-load-shuffle-placement.ll create mode 100644 test/Transforms/SLPVectorizer/X86/jumbled-load-used-in-phi.ll create mode 100644 test/Transforms/SLPVectorizer/X86/reassociated-loads.ll create mode 100644 test/Transforms/SLPVectorizer/X86/sext.ll create mode 100644 test/Transforms/SLPVectorizer/X86/sign-extend.ll delete mode 100644 test/Transforms/SLPVectorizer/X86/visit-dominated.ll create mode 100644 test/Transforms/SLPVectorizer/X86/zext.ll create mode 100644 test/Transforms/SimplifyCFG/UncondBranchToHeader.ll create mode 100644 test/Transforms/SimplifyCFG/switch_create-custom-dl.ll create mode 100644 test/Transforms/StructurizeCFG/bug36015.ll create mode 100644 test/Transforms/SyntheticCountsPropagation/initial.ll create mode 100644 test/Transforms/SyntheticCountsPropagation/prop.ll create mode 100644 test/Transforms/SyntheticCountsPropagation/scc.ll create mode 100644 test/Transforms/ThinLTOBitcodeWriter/function-alias.ll create mode 100644 test/Transforms/ThinLTOBitcodeWriter/x86/lit.local.cfg create mode 100644 test/Transforms/ThinLTOBitcodeWriter/x86/module-asm.ll delete mode 100644 test/Verifier/2008-08-22-MemCpyAlignment.ll create mode 100644 test/Verifier/DIFile.ll create mode 100644 test/Verifier/invalid-disubrange-count-node.ll create mode 100644 test/Verifier/test_copy.mir create mode 100644 test/Verifier/test_copy_mismatch_types.mir create mode 100644 test/Verifier/variant-part.ll create mode 100755 test/tools/dsymutil/Inputs/invalid.o create mode 100644 test/tools/dsymutil/Inputs/invalid.s create mode 100644 test/tools/dsymutil/Inputs/label.o create mode 100755 test/tools/dsymutil/Inputs/objc.macho.x86_64 create mode 100644 test/tools/dsymutil/Inputs/objc.macho.x86_64.o create mode 100644 test/tools/dsymutil/Inputs/sibling.o create mode 100644 test/tools/dsymutil/PowerPC/lit.local.cfg create mode 100644 test/tools/dsymutil/PowerPC/sibling.test create mode 100644 test/tools/dsymutil/X86/label.test create mode 100644 test/tools/dsymutil/X86/minimize.test create mode 100644 test/tools/dsymutil/X86/objc.test create mode 100644 test/tools/dsymutil/X86/update-one-CU.test create mode 100644 test/tools/dsymutil/X86/update.test create mode 100644 test/tools/gold/X86/thinlto_no_objects.ll rename test/tools/gold/X86/v1.12/Inputs/{thinlto_emit_linked_objects.ll => thinlto [...] create mode 100644 test/tools/gold/X86/v1.12/Inputs/thinlto_emit_linked_objects3.ll create mode 100644 test/tools/llvm-ar/mri-delete.test create mode 100644 test/tools/llvm-ar/regex-cmd.test create mode 100644 test/tools/llvm-dwarfdump/X86/Inputs/debug_rnglists_short_section.s create mode 100644 test/tools/llvm-dwarfdump/X86/debug-names-find.s create mode 100644 test/tools/llvm-dwarfdump/X86/debug_rnglists.s create mode 100644 test/tools/llvm-dwarfdump/X86/debug_rnglists_empty.s create mode 100644 test/tools/llvm-dwarfdump/X86/debug_rnglists_invalid.s create mode 100644 test/tools/llvm-extract/extract-block.ll create mode 100644 test/tools/llvm-extract/extract-invalid-block.ll create mode 100644 test/tools/llvm-extract/extract-multiple-blocks.ll copy test/tools/{llvm-objdump => llvm-nm}/AArch64/Inputs/kextbundle.macho-aarch64 (100%) copy test/{Analysis/CostModel => tools/llvm-nm}/AArch64/lit.local.cfg (100%) create mode 100644 test/tools/llvm-nm/AArch64/macho-kextbundle.test create mode 100644 test/tools/llvm-objcopy/Inputs/alloc-symtab.o create mode 100644 test/tools/llvm-objcopy/add-gnu-debuglink.test delete mode 100644 test/tools/llvm-objcopy/basic-align-copy.test create mode 100644 test/tools/llvm-objcopy/binary-no-paddr.test create mode 100644 test/tools/llvm-objcopy/binary-out-error.test create mode 100644 test/tools/llvm-objcopy/binary-paddr.test create mode 100644 test/tools/llvm-objcopy/binary-segment-layout.test create mode 100644 test/tools/llvm-objcopy/marker-segment.test create mode 100644 test/tools/llvm-objcopy/strip-dwo-inplace.test create mode 100644 test/tools/llvm-objdump/Inputs/embedded-source create mode 100644 test/tools/llvm-objdump/embedded-source.test create mode 100644 test/tools/llvm-pdbdump/Inputs/PrettyFuncDumperTest.cpp create mode 100644 test/tools/llvm-pdbdump/Inputs/PrettyFuncDumperTest.pdb create mode 100644 test/tools/llvm-pdbdump/Inputs/TypeQualifiersTest.cpp copy bindings/python/llvm/__init__.py => test/tools/llvm-pdbdump/Inputs/TypeQualif [...] create mode 100644 test/tools/llvm-pdbdump/pretty-func-dumper.test create mode 100644 test/tools/llvm-pdbdump/type-qualifiers.test create mode 100644 test/tools/llvm-readobj/elf-linker-options.ll create mode 100644 test/tools/llvm-readobj/macho-needed-libs.test create mode 100644 test/tools/llvm-symbolizer/split-debug.test create mode 100644 tools/dsymutil/NonRelocatableStringpool.cpp create mode 100644 unittests/ADT/StatisticTest.cpp create mode 100644 unittests/CodeGen/GlobalISel/PatternMatchTest.cpp create mode 100644 unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp create mode 100644 unittests/ExecutionEngine/Orc/LegacyAPIInteropTest.cpp create mode 100644 unittests/IR/DeferredDominanceTest.cpp create mode 100644 unittests/Support/CheckedArithmeticTest.cpp create mode 100644 unittests/Support/DJBTest.cpp create mode 100644 unittests/Transforms/Utils/BasicBlockUtils.cpp copy {bindings/python/llvm => utils/UpdateTestChecks}/__init__.py (100%) create mode 100644 utils/UpdateTestChecks/asm.py create mode 100644 utils/UpdateTestChecks/common.py create mode 100755 utils/bugpoint_gisel_reducer.py create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-0.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-1.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-2.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-3.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-4.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-5.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r-error-6.txt create mode 100644 utils/lit/tests/Inputs/shtest-shell/diff-r.txt create mode 100755 utils/unicode-case-fold.py create mode 100644 utils/unittest/googletest/include/gtest/internal/custom/raw-ostream.h create mode 100755 utils/update_cc_test_checks.py