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from 8c00cc11f9c [x86] make horizontal binop matching clearer; NFCI new 0cccaa3bd10 [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256 [...] new 9099160b879 [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions

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Summary of changes: lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 10 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 351 +++++++++++++++++------- lib/Target/AMDGPU/SIInstrInfo.h | 32 ++- lib/Target/AMDGPU/SIInstrInfo.td | 8 + lib/Target/X86/X86ISelLowering.cpp | 12 +- test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 230 ++++++++++++++++ test/CodeGen/AMDGPU/mubuf-legalize-operands.mir | 239 ++++++++++++++++ test/CodeGen/X86/avg.ll | 101 ++++--- test/CodeGen/X86/pr35443.ll | 3 +- test/CodeGen/X86/vector-zext.ll | 14 +- 10 files changed, 820 insertions(+), 180 deletions(-) create mode 100644 test/CodeGen/AMDGPU/mubuf-legalize-operands.ll create mode 100644 test/CodeGen/AMDGPU/mubuf-legalize-operands.mir