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from 47b6d67 [InstCombine] use m_APInt to allow icmp eq (op X, Y), C folds [...] new 24c0d9d [Hexagon] Validate register class when doing bit simplification new df48bd9 [llvm-cov] Add some documentation for the -tab-size option new 1d5ec70 [WebAssembly] Check return value of getRegForValue in FastISel

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Summary of changes: docs/CommandGuide/llvm-cov.rst | 5 +++ lib/Target/Hexagon/HexagonBitSimplify.cpp | 43 ++++++++++++++++++++------ lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 13 ++++++++ test/CodeGen/Hexagon/bit-validate-reg.ll | 21 +++++++++++++ test/CodeGen/WebAssembly/fast-isel-noreg.ll | 35 +++++++++++++++++++++ tools/llvm-cov/CodeCoverage.cpp | 5 +-- 6 files changed, 110 insertions(+), 12 deletions(-) create mode 100644 test/CodeGen/Hexagon/bit-validate-reg.ll create mode 100644 test/CodeGen/WebAssembly/fast-isel-noreg.ll