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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allyesconfig in repository toolchain/ci/qemu.

from 3757b0d08b Merge tag 'pull-request-2022-05-18' of https://gitlab.com/th [...] adds d6cd3ae0eb target/riscv: Fix VS mode hypervisor CSR access adds 02b511985e target/riscv: rvv: Fix early exit condition for whole regist [...] adds 77046729f9 hw/intc: Pass correct hartid while updating mtimecmp adds 6047dcc245 target/riscv: Move Zhinx* extensions on ISA string adds a4a9a4432e target/riscv: Add short-isa-string option adds 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) adds 91a3387dc4 hw/riscv: Make CPU config error handling generous (sifive_e/ [...] adds 61cdf4593e target/riscv: Fix coding style on "G" expansion adds 1d398ab9dc target/riscv: Disable "G" by default adds 9f6b7da5d2 target/riscv: Change "G" expansion adds 1086504c6f target/riscv: FP extension requirements adds bc57381669 target/riscv: Move/refactor ISA extension checks adds 8f1b608798 hw/vfio/pci-quirks: Resolve redundant property getters adds 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors adds bb06941f95 target/riscv: check 'I' and 'E' after checking 'G' in riscv_ [...] adds 075eeda931 target/riscv: Fix typo of mimpid cpu option adds c1fbcecb3a target/riscv: Fix csr number based privilege checking adds 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken fr [...] adds 62cf02451e target/riscv: Set [m|s]tval for both illegal and virtual ins [...] adds d644e5e44f hw/riscv: virt: Fix interrupt parent for dynamic platform devices adds 5160bacc06 target/riscv: add zicsr/zifencei to isa_string adds d616889ece hw/core: Sync uboot_image.h from U-Boot v2022.01 adds 8fe63fe8e5 hw/core: loader: Set is_linux to true for VxWorks uImage adds 0cac736e73 Merge tag 'pull-riscv-to-apply-20220525' of github.com:alist [...] adds 3569664ee9 qga: add guest-get-diskstats command for Linux guests adds 323f3a8f22 trivial: qga: Log version on start adds 2e7b218958 tests: Bump Fedora image version for cross-compilation adds b9a002609f qga-win32: Add support for NVME bus type adds ffae6d9585 Merge tag 'qga-win32-pull-2022-05-25' of github.com:kostyanf [...] adds 60f1c8017a linux-user: Clean up arg_start/arg_end confusion adds c3a28d7122 linux-user/syscall.c: fix build without RLIMIT_RTTIME adds 2f6f4290e0 linux-user/elfload: Remove pointless non-const CPUArchState cast adds a0939b8916 linux-user: Have do_syscall() use CPUArchState* instead of void* adds 0effdc29b5 linux-user: Remove pointless CPU{ARCH}State casts adds 9a12adc704 linux-user/s390x: Fix unwinding from signal handlers adds 1a75b14038 tests/tcg/s390x: Test unwinding from signal handlers adds 565a84c1e6 linux-user/host/s390: Treat EX and EXRL as writes adds 6882d65161 Merge tag 'linux-user-for-7.1-pull-request' of https://gitla [...] adds 29320530cf docs: Correct the default thread-pool-size adds 7929f75f34 Merge tag 'block-pull-request' of https://gitlab.com/stefanh [...]

No new revisions were added by this update.

Summary of changes: docs/tools/virtiofsd.rst | 2 +- hw/core/loader.c | 15 ++ hw/core/uboot_image.h | 213 ++++++++++++++------- hw/intc/riscv_aclint.c | 3 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 28 +-- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 27 ++- hw/vfio/pci-quirks.c | 34 +--- linux-user/elfload.c | 12 +- linux-user/include/host/s390/host-signal.h | 7 + linux-user/linuxload.c | 12 +- linux-user/main.c | 4 +- linux-user/qemu.h | 12 +- linux-user/s390x/signal.c | 5 + linux-user/strace.c | 202 +++++++++---------- linux-user/strace.h | 4 +- linux-user/syscall.c | 83 ++++---- linux-user/uname.c | 4 +- linux-user/uname.h | 2 +- linux-user/user-internals.h | 18 +- qga/commands-posix.c | 123 ++++++++++++ qga/commands-win32.c | 11 ++ qga/main.c | 2 + qga/qapi-schema.json | 86 +++++++++ semihosting/arm-compat-semi.c | 4 +- target/riscv/cpu.c | 91 ++++++--- target/riscv/cpu.h | 12 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 26 +-- target/riscv/insn_trans/trans_rvv.c.inc | 58 +++--- target/riscv/translate.c | 17 +- tests/docker/dockerfiles/fedora-win32-cross.docker | 2 +- tests/docker/dockerfiles/fedora-win64-cross.docker | 2 +- tests/tcg/s390x/signals-s390x.c | 69 +++++-- 36 files changed, 802 insertions(+), 398 deletions(-)