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from 92a20faea1b [AMDGPU] Partial revert of rL348371: Turn on the DPP combin [...] new fd7ff8f4930 AMDGPU: Generate VALU ThreeOp Integer instructions

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Summary of changes: lib/Target/AMDGPU/VOP3Instructions.td | 47 ++++++++++ test/CodeGen/AMDGPU/add3.ll | 171 ++++++++++++++++++++++++++++++++++ test/CodeGen/AMDGPU/add_shl.ll | 115 +++++++++++++++++++++++ test/CodeGen/AMDGPU/and_or.ll | 112 ++++++++++++++++++++++ test/CodeGen/AMDGPU/or3.ll | 95 +++++++++++++++++++ test/CodeGen/AMDGPU/shl_add.ll | 94 +++++++++++++++++++ test/CodeGen/AMDGPU/shl_or.ll | 144 ++++++++++++++++++++++++++++ test/CodeGen/AMDGPU/sibling-call.ll | 3 +- test/CodeGen/AMDGPU/xor_add.ll | 94 +++++++++++++++++++ 9 files changed, 873 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/AMDGPU/add3.ll create mode 100644 test/CodeGen/AMDGPU/add_shl.ll create mode 100644 test/CodeGen/AMDGPU/and_or.ll create mode 100644 test/CodeGen/AMDGPU/or3.ll create mode 100644 test/CodeGen/AMDGPU/shl_add.ll create mode 100644 test/CodeGen/AMDGPU/shl_or.ll create mode 100644 test/CodeGen/AMDGPU/xor_add.ll