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from f322701e246 aarch64: Fix ordering of aarch64-cores.def new 30784833af0 RISC-V: Define __riscv_cmodel_medany for PIC mode. new 95e10b8aa10 arm: Add new vector mode macros

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Summary of changes: gcc/config/arm/arm.h | 41 +++++++++++++++++++ gcc/config/arm/iterators.md | 8 ---- gcc/config/arm/neon.md | 47 +--------------------- gcc/config/arm/vec-common.md | 42 +++---------------- gcc/config/riscv/riscv-c.c | 9 +++-- .../gcc.target/arm/armv8_2-fp16-arith-2.c | 20 +++++---- gcc/testsuite/gcc.target/riscv/predef-3.c | 6 +-- gcc/testsuite/gcc.target/riscv/predef-6.c | 6 +-- 8 files changed, 73 insertions(+), 106 deletions(-)