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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig in repository toolchain/ci/llvm-project.

from c38899fc26e [ARM] Move MVE VPT block tests into the Thumb2 directory. NFC adds d7504a1569d [GISel]: Attach missing range metadata while translating G_LOADs adds 630be14ac64 [SmallBitVector] Fix bug in find_next_unset for small types [...] adds e6cd20ba534 [InstCombine] Update comment I missed in r366649. NFC adds 73d641a23c2 [PowerPC][NFC] Regenerate test using script adds 86fa3270ef6 [X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_B [...] adds 3d68adebc57 [PowerPC][NFC] Precomit test case for upcoming patch adds ee5dc7e7ad8 [InstCombine] Add foldAndOfICmps test cases inspired by PR42691. adds 1a1af4392ac [analyzer] Fix -Wunused-function in NDEBUG builds with #ifd [...] adds 6ef23e65818 [utils] Clean up UpdateTestChecks/common.py adds c6c31da8677 [Loop Peeling] Fix the handling of branch weights of peeled [...] adds 3d72a58981e [PowerPC][NFC] Precommit a test case where ppc-mi-peepholes [...] adds 298500ae331 [AMDGPU] Save some work when an atomic op has no uses adds 6522a7df544 [llvm-readobj] - Stop using precompiled objects in file-hea [...] adds 6771a89fa01 [IPRA][ARM] Make use of the "returned" parameter attribute adds 88559637641 [OpenCL] Improve destructor support in C++ for OpenCL adds 3a52e50d737 Add location of SVN staging dir to git-llvm error output adds 0a42fe70a56 [AST] Treat semantic form of InitListExpr as implicit code [...] adds f94668e3360 [lldb][NFC] Tablegenify breakpoint adds af5d3b02fbc [clangd] Log input code of failed highlighting tests. NFC adds 1df6be211e4 [clangd] Set buffer name for main file. NFCI adds 5d4bc1293cc [ARM][test] Improve tests adds 13a364e1cc9 [yaml2obj] - Change how we handle implicit sections. adds bdb92955200 [X86][SSE] Add EltsFromConsecutiveLoads test case identifie [...] adds 006cf8c03d7 Added address-space mangling for stack related intrinsics adds 8d372008b13 AMDGPU/GlobalISel: Fix tests without asserts adds b3d719e1cf0 [X86] EltsFromConsecutiveLoads - support common source load [...] adds 1f5712ebb5d Revert the change to the [[nodiscard]] feature test macro value. adds 8c5e6fa6575 Updated the signature for some stack related intrinsics (CLANG) adds 8876a312a81 [ARM] Fix for MVE VPT block pass adds 937d0ee5d8d AMDGPU/GlobalISel: Remove unnecessary code adds 0166cff09b1 Reland [ELF] Loose a condition for relocation with a symbol new 5418be85e85 Update documentation for all CERT checks that correspond to [...] new 4668ea40722 AMDGPU/GlobalISel: Fix broken tests

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Summary of changes: clang-tools-extra/clangd/ClangdUnit.cpp | 11 +- .../clangd/unittests/SemanticHighlightingTests.cpp | 3 +- .../docs/clang-tidy/checks/cert-dcl21-cpp.rst | 16 +- .../docs/clang-tidy/checks/cert-err09-cpp.rst | 5 + .../docs/clang-tidy/checks/cert-oop11-cpp.rst | 6 + .../misc-throw-by-value-catch-by-reference.rst | 9 +- clang/include/clang/AST/DeclCXX.h | 14 +- clang/include/clang/AST/ExprCXX.h | 11 +- clang/include/clang/AST/RecursiveASTVisitor.h | 23 +- clang/include/clang/Basic/Attr.td | 2 +- clang/lib/AST/DeclCXX.cpp | 25 +- clang/lib/AST/ExprCXX.cpp | 7 + clang/lib/CodeGen/CGBuiltin.cpp | 24 +- clang/lib/CodeGen/CGCXXABI.h | 14 +- clang/lib/CodeGen/CGCall.cpp | 2 +- clang/lib/CodeGen/CGClass.cpp | 40 ++- clang/lib/CodeGen/CGDecl.cpp | 21 +- clang/lib/CodeGen/CGException.cpp | 3 +- clang/lib/CodeGen/CGExprCXX.cpp | 31 +- clang/lib/CodeGen/CodeGenFunction.h | 13 +- clang/lib/CodeGen/ItaniumCXXABI.cpp | 32 +- clang/lib/CodeGen/MicrosoftCXXABI.cpp | 30 +- clang/lib/Sema/SemaDeclCXX.cpp | 50 +-- clang/lib/Sema/SemaOverload.cpp | 4 +- clang/lib/StaticAnalyzer/Core/RegionStore.cpp | 6 +- clang/test/CodeGen/builtin-sponentry.c | 2 +- clang/test/CodeGen/exceptions-seh.c | 4 +- clang/test/CodeGen/integer-overflow.c | 8 +- clang/test/CodeGen/ms-intrinsics.c | 2 +- clang/test/CodeGen/ms-setjmp.c | 8 +- clang/test/CodeGenCXX/PR42665.cpp | 61 ++++ .../test/CodeGenOpenCL/builtins-generic-amdgcn.cl | 5 + clang/test/CodeGenOpenCLCXX/addrspace-ctor.cl | 14 - .../test/CodeGenOpenCLCXX/addrspace-with-class.cl | 59 +++ clang/test/Preprocessor/has_attribute.cpp | 2 +- .../InitListExprPreOrder.cpp | 19 +- lld/test/ELF/arm-bl-v6-inrange.s | 2 +- lld/test/ELF/arm-bl-v6.s | 2 +- lld/test/ELF/arm-blx.s | 2 +- lld/test/ELF/arm-branch-rangethunk.s | 4 +- lld/test/ELF/arm-branch.s | 2 +- lld/test/ELF/arm-copy.s | 10 +- lld/test/ELF/arm-execute-only.s | 10 +- lld/test/ELF/arm-exidx-canunwind.s | 16 +- lld/test/ELF/arm-exidx-discard.s | 2 +- lld/test/ELF/arm-exidx-gc.s | 18 +- lld/test/ELF/arm-exidx-order.s | 24 +- lld/test/ELF/arm-exidx-output.s | 2 +- lld/test/ELF/arm-exidx-relocatable.s | 2 +- lld/test/ELF/arm-exidx-shared.s | 2 +- lld/test/ELF/arm-extreme-range-pi-thunk.s | 58 +-- lld/test/ELF/arm-force-pi-thunk.s | 2 +- lld/test/ELF/arm-gnu-ifunc-plt.s | 46 +-- lld/test/ELF/arm-gnu-ifunc.s | 34 +- lld/test/ELF/arm-mov-relocs.s | 24 +- lld/test/ELF/arm-plt-reloc.s | 174 ++++----- .../ELF/{arm-data-relocs.s => arm-reloc-abs32.s} | 0 lld/test/ELF/arm-sbrel32.s | 6 +- lld/test/ELF/arm-static-defines.s | 2 +- lld/test/ELF/arm-target2.s | 8 +- lld/test/ELF/arm-thumb-blx.s | 2 +- lld/test/ELF/arm-thumb-branch-rangethunk.s | 2 +- lld/test/ELF/arm-thumb-branch.s | 2 +- lld/test/ELF/arm-thumb-condbranch-thunk.s | 2 +- lld/test/ELF/arm-thumb-interwork-thunk.s | 6 +- lld/test/ELF/arm-thumb-mix-range-thunk-os.s | 2 +- lld/test/ELF/arm-thumb-narrow-branch-check.s | 2 +- lld/test/ELF/arm-thumb-no-undefined-thunk.s | 2 +- lld/test/ELF/arm-thumb-range-thunk-os.s | 2 +- lld/test/ELF/arm-thumb-thunk-empty-pass.s | 2 +- lld/test/ELF/arm-thumb-thunk-symbols.s | 4 +- lld/test/ELF/arm-thumb-undefined-weak.s | 2 +- lld/test/ELF/arm-thunk-largesection.s | 2 +- lld/test/ELF/arm-thunk-linkerscript-dotexpr.s | 2 +- lld/test/ELF/arm-thunk-linkerscript-large.s | 2 +- lld/test/ELF/arm-thunk-linkerscript-orphan.s | 2 +- lld/test/ELF/arm-thunk-linkerscript-sort.s | 2 +- lld/test/ELF/arm-thunk-linkerscript.s | 2 +- lld/test/ELF/arm-thunk-multipass-plt.s | 2 +- lld/test/ELF/arm-thunk-multipass.s | 2 +- lld/test/ELF/arm-undefined-weak.s | 2 +- .../{pack-dyn-relocs2.s => pack-dyn-relocs-arm2.s} | 2 +- lldb/source/Commands/CommandObjectBreakpoint.cpp | 144 +------- .../Commands/CommandObjectBreakpointCommand.cpp | 14 +- lldb/source/Commands/Options.td | 243 +++++++++++++ lldb/utils/TableGen/LLDBOptionDefEmitter.cpp | 8 +- llvm/include/llvm/ADT/SmallBitVector.h | 2 +- llvm/include/llvm/IR/Intrinsics.td | 6 +- llvm/include/llvm/ObjectYAML/ELFYAML.h | 7 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 6 +- llvm/lib/CodeGen/SjLjEHPrepare.cpp | 5 +- llvm/lib/MC/ELFObjectWriter.cpp | 5 - llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp | 137 +++---- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 4 - llvm/lib/Target/ARM/ARMFrameLowering.cpp | 6 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 + llvm/lib/Target/ARM/ARMMachineFunctionInfo.h | 7 + llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 21 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 99 ++++-- llvm/lib/Target/X86/X86WinEHState.cpp | 5 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 2 +- .../Instrumentation/HWAddressSanitizer.cpp | 11 +- .../Instrumentation/SanitizerCoverage.cpp | 6 +- llvm/lib/Transforms/Utils/LoopUnrollPeel.cpp | 103 +++--- llvm/test/Bitcode/compatibility-3.6.ll | 2 +- llvm/test/Bitcode/compatibility-3.7.ll | 2 +- llvm/test/Bitcode/compatibility-3.8.ll | 2 +- llvm/test/Bitcode/compatibility-3.9.ll | 2 +- llvm/test/Bitcode/compatibility-4.0.ll | 2 +- llvm/test/Bitcode/compatibility-5.0.ll | 2 +- llvm/test/Bitcode/compatibility-6.0.ll | 2 +- llvm/test/Bitcode/compatibility.ll | 2 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 11 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 174 +-------- .../GlobalISel/inst-select-fmaxnum-ieee.s16.mir | 48 +++ .../GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir | 21 ++ .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 174 +-------- .../AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir | 48 +++ .../GlobalISel/inst-select-fmaxnum.v2s16.mir | 22 ++ .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 174 +-------- .../GlobalISel/inst-select-fminnum-ieee.s16.mir | 48 +++ .../GlobalISel/inst-select-fminnum-ieee.v2s16.mir | 22 ++ .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 174 +-------- .../AMDGPU/GlobalISel/inst-select-fminnum.s16.mir | 48 +++ .../GlobalISel/inst-select-fminnum.v2s16.mir | 22 ++ .../GlobalISel/regbankselect-atomicrmw-and.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-max.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-min.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-or.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-sub.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-umax.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-umin.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-xchg.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-xor.mir | 12 +- llvm/test/CodeGen/ARM/ipra-r0-returned.ll | 18 + .../MIR/PowerPC/peephole-miscompile-extswsli.mir | 66 ++++ llvm/test/CodeGen/PowerPC/dform-adjust.ll | 125 +++++++ llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 189 ++++++++-- llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir | 4 +- .../CodeGen/X86/clear_upper_vector_element_bits.ll | 300 ++++++---------- llvm/test/CodeGen/X86/load-partial.ll | 119 ++++--- .../Instrumentation/HWAddressSanitizer/alloca.ll | 2 +- .../HWAddressSanitizer/kernel-alloca.ll | 2 +- .../SanitizerCoverage/stack-depth.ll | 4 +- llvm/test/MC/ELF/basic-elf-32.s | 4 +- llvm/test/MC/ELF/compression.s | 4 +- llvm/test/MC/ELF/relocation-386.s | 2 +- llvm/test/MC/Mips/elf-relsym.s | 10 +- llvm/test/MC/Mips/xgot.s | 4 +- llvm/test/Transforms/InstCombine/and-or-icmps.ll | 39 ++ .../Transforms/LoopUnroll/peel-loop-pgo-deopt.ll | 16 +- llvm/test/Transforms/LoopUnroll/peel-loop-pgo.ll | 8 +- llvm/test/Verifier/intrinsic-immarg.ll | 2 +- .../tools/llvm-readobj/Inputs/magic.coff-unknown | Bin 450 -> 0 bytes .../llvm-readobj/Inputs/trivial.exe.coff-i386 | Bin 2560 -> 0 bytes .../llvm-readobj/Inputs/trivial.obj.coff-arm64 | Bin 141 -> 0 bytes .../llvm-readobj/Inputs/trivial.obj.elf-lanai | Bin 737 -> 0 bytes .../test/tools/llvm-readobj/coff-file-headers.test | 321 +++++++++++++++++ llvm/test/tools/llvm-readobj/elf-file-headers.test | 129 +++++++ llvm/test/tools/llvm-readobj/file-headers.test | 394 --------------------- .../tools/llvm-readobj/macho-file-headers.test | 160 +++++++++ .../test/tools/llvm-readobj/wasm-file-headers.test | 14 + llvm/tools/yaml2obj/yaml2elf.cpp | 71 ++-- llvm/unittests/ADT/BitVectorTest.cpp | 32 ++ llvm/utils/UpdateTestChecks/common.py | 12 +- llvm/utils/git-svn/git-llvm | 4 +- 170 files changed, 2876 insertions(+), 2235 deletions(-) create mode 100644 clang/test/CodeGenCXX/PR42665.cpp delete mode 100644 clang/test/CodeGenOpenCLCXX/addrspace-ctor.cl create mode 100644 clang/test/CodeGenOpenCLCXX/addrspace-with-class.cl rename lld/test/ELF/{arm-data-relocs.s => arm-reloc-abs32.s} (100%) rename lld/test/ELF/{pack-dyn-relocs2.s => pack-dyn-relocs-arm2.s} (99%) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir create mode 100644 llvm/test/CodeGen/ARM/ipra-r0-returned.ll create mode 100644 llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir create mode 100644 llvm/test/CodeGen/PowerPC/dform-adjust.ll delete mode 100644 llvm/test/tools/llvm-readobj/Inputs/magic.coff-unknown delete mode 100644 llvm/test/tools/llvm-readobj/Inputs/trivial.exe.coff-i386 delete mode 100644 llvm/test/tools/llvm-readobj/Inputs/trivial.obj.coff-arm64 delete mode 100644 llvm/test/tools/llvm-readobj/Inputs/trivial.obj.elf-lanai create mode 100644 llvm/test/tools/llvm-readobj/coff-file-headers.test create mode 100644 llvm/test/tools/llvm-readobj/elf-file-headers.test delete mode 100644 llvm/test/tools/llvm-readobj/file-headers.test create mode 100644 llvm/test/tools/llvm-readobj/macho-file-headers.test create mode 100644 llvm/test/tools/llvm-readobj/wasm-file-headers.test