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from a4b0c616f63 Sched model improving on btver2: JFPU01 resource, vtestp* f [...] new f8c0f51efe4 [RISCV] MC layer support for the standard RV32M instruction [...]

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Summary of changes: lib/Target/RISCV/RISCV.td | 13 +++++++++---- lib/Target/RISCV/RISCVInstrInfo.td | 6 ++++++ lib/Target/RISCV/RISCVInstrInfoM.td | 28 ++++++++++++++++++++++++++++ lib/Target/RISCV/RISCVSubtarget.h | 2 ++ test/MC/RISCV/rv32i-invalid.s | 3 +++ test/MC/RISCV/rv32m-valid.s | 33 +++++++++++++++++++++++++++++++++ 6 files changed, 81 insertions(+), 4 deletions(-) create mode 100644 lib/Target/RISCV/RISCVInstrInfoM.td create mode 100644 test/MC/RISCV/rv32m-valid.s