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from b366c9fe384 Daily bump. new 5821f378b58 RISC-V: Fix wrong check of register occurrences [PR109535] new eed151c062b Docs: Add vector register constarint for asm operands

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Summary of changes: gcc/config/riscv/riscv-vsetvl.cc | 14 +- gcc/doc/md.texi | 9 ++ gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C | 144 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c | 11 ++ 4 files changed, 177 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c