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from f307ab8b18c libgcc: Fix aarch64 build new 3fbed695027 [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

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Summary of changes: gcc/config/riscv/mips-insn.md | 35 +++++++ gcc/config/riscv/riscv-cores.def | 3 +- .../{riscv-ext-ventana.def => riscv-ext-mips.def} | 26 ++--- gcc/config/riscv/riscv-ext.def | 1 + gcc/config/riscv/riscv-ext.opt | 4 + gcc/config/riscv/riscv.cc | 107 ++++++++++++++------- gcc/config/riscv/riscv.md | 3 +- gcc/config/riscv/t-riscv | 3 +- gcc/doc/riscv-ext.texi | 4 + gcc/testsuite/gcc.target/riscv/mipscondmov.c | 29 ++++++ 10 files changed, 165 insertions(+), 50 deletions(-) create mode 100644 gcc/config/riscv/mips-insn.md copy gcc/config/riscv/{riscv-ext-ventana.def => riscv-ext-mips.def} (63%) create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c