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from e66042ff019 [X86][SSE] Reduce instruction/register usages for v4i32 vec [...] new bbebdb95807 [Hexagon] Mark HVX vector predicate bitwise ops as legal, a [...] new 5dc60d332df [Hexagon] Fix the order of operands when selecting QCAT

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Summary of changes: lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 38 +++++--- lib/Target/Hexagon/HexagonPatternsHVX.td | 74 ++++++++++------ test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll | 102 ++++++++++++++++++++++ test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll | 102 ++++++++++++++++++++++ 4 files changed, 279 insertions(+), 37 deletions(-) create mode 100644 test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll create mode 100644 test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll