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from ceb944ad4c3 Daily bump. new 35b1096896a RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1 new ecde8d50bea RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2 new 23ab7f632f4 Rename __{float,double}_u to __x86_{float,double}_u to avoi [...]

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Summary of changes: gcc/config/i386/emmintrin.h | 10 +- gcc/config/i386/xmmintrin.h | 6 +- gcc/testsuite/gcc.target/i386/pr115796.c | 24 ++ .../riscv/rvv/autovec/binop/vec_sat_arith.h | 42 ++++ .../riscv/rvv/autovec/binop/vec_sat_data.h | 256 +++++++++++++++++++++ .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c | 14 ++ .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c | 14 ++ .../{vec_sat_u_add-1.c => vec_sat_u_add_imm-3.c} | 9 +- .../{vec_sat_u_add-1.c => vec_sat_u_add_imm-4.c} | 9 +- .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c | 14 ++ .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c | 14 ++ .../{vec_sat_u_add-13.c => vec_sat_u_add_imm-7.c} | 9 +- .../{vec_sat_u_add-1.c => vec_sat_u_add_imm-8.c} | 9 +- .../rvv/autovec/binop/vec_sat_u_add_imm-run-1.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-2.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-3.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-4.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-5.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-6.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-7.c | 28 +++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-8.c | 28 +++ 21 files changed, 618 insertions(+), 36 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr115796.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-1.c => vec_sa [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-1.c => vec_sa [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-13.c => vec_s [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-1.c => vec_sa [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...]