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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/qemu.

from 91e8394415 Merge remote-tracking branch 'remotes/juanquintela/tags/migr [...] adds 0fdbb7d2c1 accel/tcg: Split out adjust_signal_pc adds f920ffdd8e accel/tcg: Move clear_helper_retaddr to cpu loop adds 5e38ba7dde accel/tcg: Split out handle_sigsegv_accerr_write adds 940b30904e accel/tcg: Fold cpu_exit_tb_from_sighandler into caller adds ba0e733362 configure: Merge riscv32 and riscv64 host architectures adds e6037d04c5 linux-user: Reorg handling for SIGSEGV adds 85442fce49 linux-user/host/x86: Populate host_signal.h adds 8cc7b85d56 linux-user/host/ppc: Populate host_signal.h adds 44c8f2cd90 linux-user/host/alpha: Populate host_signal.h adds 8b5bd46193 linux-user/host/sparc: Populate host_signal.h adds a30bfaa7bd linux-user/host/arm: Populate host_signal.h adds cf5f42fd07 linux-user/host/aarch64: Populate host_signal.h adds 66ee11d407 linux-user/host/s390: Populate host_signal.h adds b12161120a linux-user/host/mips: Populate host_signal.h adds 97be8c6a95 linux-user/host/riscv: Populate host_signal.h adds 7ce8e389ef target/arm: Fixup comment re handle_cpu_signal adds 4f3bbd9cfb linux-user/host/riscv: Improve host_signal_write adds 04de121aaf linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER adds 09e94676ad hw/core: Add TCGCPUOps.record_sigsegv adds 72d2bbf9ff linux-user: Add cpu_loop_exit_sigsegv adds 90113883af target/alpha: Implement alpha_cpu_record_sigsegv adds 5e98763c0e target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup adds 9b12b6b442 target/arm: Implement arm_cpu_record_sigsegv adds 5753605412 target/cris: Make cris_cpu_tlb_fill sysemu only adds 70863887a8 target/hexagon: Remove hexagon_cpu_tlb_fill adds 860e0b965b target/hppa: Make hppa_cpu_tlb_fill sysemu only adds f74bd157c6 target/i386: Implement x86_cpu_record_sigsegv adds 028772c45c target/m68k: Make m68k_cpu_tlb_fill sysemu only adds fd297732a2 target/microblaze: Make mb_cpu_tlb_fill sysemu only adds 52d4899bf3 target/mips: Make mips_cpu_tlb_fill sysemu only adds fac94cb36d target/nios2: Implement nios2_cpu_record_sigsegv adds d315712b69 linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE adds 12f0bc5579 target/openrisc: Make openrisc_cpu_tlb_fill sysemu only adds 1db8af5c87 target/ppc: Implement ppc_cpu_record_sigsegv adds 263e2ab20c target/riscv: Make riscv_cpu_tlb_fill sysemu only adds db9aab5783 target/s390x: Use probe_access_flags in s390_probe_access adds c8e7fef102 target/s390x: Implement s390_cpu_record_sigsegv adds cac720ec54 target/sh4: Make sh4_cpu_tlb_fill sysemu only adds caac44a52a target/sparc: Make sparc_cpu_tlb_fill sysemu only adds 6407f64fcf target/xtensa: Make xtensa_cpu_tlb_fill sysemu only adds eeca7dc566 accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu adds 644a9fece4 hw/core: Add TCGCPUOps.record_sigbus adds 12ed56407e linux-user: Add cpu_loop_exit_sigbus adds e7424abc20 target/alpha: Implement alpha_cpu_record_sigbus adds 39a099ca25 target/arm: Implement arm_cpu_record_sigbus adds ee8e0807de linux-user/hppa: Remove EXCP_UNALIGN handling adds b414df757d target/microblaze: Do not set MO_ALIGN for user-only adds 336e91f853 target/ppc: Move SPR_DSISR setting to powerpc_excp adds a7e3af1325 target/ppc: Set fault address in ppc_cpu_do_unaligned_access adds 996473e4a9 target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu adds 5057ae5636 linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling adds 5bcbf3561f target/s390x: Implement s390x_cpu_record_sigbus adds 0ee0942a78 target/sh4: Set fault address in superh_cpu_do_unaligned_access adds 9852112ee4 target/sparc: Remove DEBUG_UNALIGNED adds c0e0c6fe01 target/sparc: Split out build_sfsr adds aebe51538b target/sparc: Set fault address in sparc_cpu_do_unaligned_access adds fce3f47430 accel/tcg: Report unaligned atomics for user-only adds 9395cd0a38 accel/tcg: Report unaligned load/store for user-only adds 37e891e38f tcg: Add helper_unaligned_{ld,st} for user-only sigbus adds 742f07628c linux-user: Handle BUS_ADRALN in host_signal_handler adds 102f39b32d Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-2021 [...] adds e955acd91d MAINTAINERS: Add MIPS general architecture support entry adds 6cee54794d MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware adds f44d1d4ed9 MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware adds 06df015b69 target/mips: Fix MSA MADDV.B opcode adds 36b39a69b2 target/mips: Fix MSA MSUBV.B opcode adds bbc213b37c target/mips: Adjust style in msa_translate_init() adds 40f75c02d4 target/mips: Use dup_const() to simplify adds 340ee8b3f1 target/mips: Have check_msa_access() return a boolean adds 7e9db46d64 target/mips: Use enum definitions from CPUMIPSMSADataFormat enum adds d61566cf78 target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v adds 75094c334e target/mips: Convert MSA LDI opcode to decodetree adds b8e74816ec target/mips: Convert MSA I5 instruction format to decodetree adds 4701d23aef target/mips: Convert MSA BIT instruction format to decodetree adds a9e1795833 target/mips: Convert MSA SHF opcode to decodetree adds 7cc351ff9d target/mips: Convert MSA I8 instruction format to decodetree adds ce121fe234 target/mips: Convert MSA load/store instruction format to de [...] adds 5c5b64000c target/mips: Convert MSA 2RF instruction format to decodetree adds 675bf34a6f target/mips: Convert MSA FILL opcode to decodetree adds adcff99a6b target/mips: Convert MSA 2R instruction format to decodetree adds 7acb5c78a7 target/mips: Convert MSA VEC instruction format to decodetree adds ff29e5d3c0 target/mips: Convert MSA 3RF instruction format to decodetre [...] adds 2d5246f305 target/mips: Convert MSA 3RF instruction format to decodetre [...] adds 67bedef51a target/mips: Convert MSA 3R instruction format to decodetree [...] adds f18708a53a target/mips: Convert MSA 3R instruction format to decodetree [...] adds c79db8c239 target/mips: Convert MSA 3R instruction format to decodetree [...] adds 0a086d2e80 target/mips: Convert MSA 3R instruction format to decodetree [...] adds 0a510c934c target/mips: Convert MSA ELM instruction format to decodetree adds 2f2745c81a target/mips: Convert MSA COPY_U opcode to decodetree adds 97fe675519 target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree adds 62ba0e855a target/mips: Convert MSA MOVE.V opcode to decodetree adds 6f74237691 target/mips: Convert CFCMSA opcode to decodetree adds 643ec9022e target/mips: Convert CTCMSA opcode to decodetree adds 75d12c8c24 target/mips: Remove generic MSA opcode adds 73053f6228 target/mips: Remove one MSA unnecessary decodetree overlap group adds ba7b6f025b target/mips: Fix Loongson-3A4000 MSAIR config register adds 675cf7817c target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU adds d3647ef1fd usb/uhci: Misc clean up adds ece29df33b usb/uhci: Disallow user creating a vt82c686-uhci-pci device adds e4f5b93986 usb/uhci: Replace pci_set_irq with qemu_set_irq adds 4f3b0a4d75 hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts adds 6f08c9c531 Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOM [...] adds 157f75435e Merge remote-tracking branch 'remotes/philmd/tags/mips-20211 [...]

No new revisions were added by this update.

Summary of changes: MAINTAINERS | 37 +- accel/tcg/cpu-exec.c | 3 +- accel/tcg/user-exec.c | 859 +------ configure | 8 +- hw/usb/hcd-uhci.c | 14 +- hw/usb/hcd-uhci.h | 3 +- hw/usb/vt82c686-uhci-pci.c | 15 + include/exec/exec-all.h | 55 +- include/hw/core/tcg-cpu-ops.h | 71 +- include/tcg/tcg-ldst.h | 5 + linux-user/aarch64/cpu_loop.c | 12 +- linux-user/alpha/cpu_loop.c | 15 - linux-user/arm/cpu_loop.c | 30 +- linux-user/cris/cpu_loop.c | 10 - linux-user/elfload.c | 2 - linux-user/hexagon/cpu_loop.c | 24 +- linux-user/host/aarch64/host-signal.h | 74 + linux-user/host/alpha/host-signal.h | 42 + linux-user/host/arm/host-signal.h | 30 + linux-user/host/i386/host-signal.h | 25 + linux-user/host/mips/host-signal.h | 62 + linux-user/host/ppc/host-signal.h | 25 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 58 + linux-user/host/{riscv64 => riscv}/hostdep.h | 4 +- .../host/{riscv64 => riscv}/safe-syscall.inc.S | 0 linux-user/host/riscv32/hostdep.h | 11 - linux-user/host/s390/host-signal.h | 93 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 54 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 24 + linux-user/hppa/cpu_loop.c | 23 - linux-user/m68k/cpu_loop.c | 10 - linux-user/microblaze/cpu_loop.c | 10 - linux-user/mips/cpu_loop.c | 11 - linux-user/openrisc/cpu_loop.c | 25 +- linux-user/ppc/cpu_loop.c | 8 - linux-user/riscv/cpu_loop.c | 7 - linux-user/s390x/cpu_loop.c | 13 +- linux-user/sh4/cpu_loop.c | 8 - linux-user/signal.c | 129 +- linux-user/sparc/cpu_loop.c | 25 - linux-user/xtensa/cpu_loop.c | 9 - meson.build | 4 +- target/alpha/cpu.c | 7 +- target/alpha/cpu.h | 21 +- target/alpha/helper.c | 39 +- target/alpha/mem_helper.c | 30 +- target/arm/cpu.c | 7 +- target/arm/cpu_tcg.c | 7 +- target/arm/internals.h | 8 + target/arm/mte_helper.c | 6 +- target/arm/sve_helper.c | 2 +- target/arm/tlb_helper.c | 42 +- target/cris/cpu.c | 4 +- target/cris/cpu.h | 8 +- target/cris/helper.c | 18 - target/cris/meson.build | 7 +- target/hexagon/cpu.c | 23 - target/hppa/cpu.c | 2 +- target/hppa/cpu.h | 2 +- target/hppa/mem_helper.c | 15 - target/hppa/meson.build | 6 +- target/i386/tcg/helper-tcg.h | 6 + target/i386/tcg/tcg-cpu.c | 3 +- target/i386/tcg/user/excp_helper.c | 23 +- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 8 +- target/microblaze/helper.c | 13 +- target/microblaze/translate.c | 16 + target/mips/cpu-defs.c.inc | 2 +- target/mips/cpu.c | 2 +- target/mips/tcg/meson.build | 3 - target/mips/tcg/msa.decode | 243 +- target/mips/tcg/msa_helper.c | 64 +- target/mips/tcg/msa_translate.c | 2623 +++++--------------- target/mips/tcg/tcg-internal.h | 7 +- target/mips/tcg/user/meson.build | 3 - target/mips/tcg/user/tlb_helper.c | 59 - target/nios2/cpu.c | 6 +- target/nios2/cpu.h | 6 + target/nios2/helper.c | 7 +- target/openrisc/cpu.c | 2 +- target/openrisc/cpu.h | 7 +- target/openrisc/meson.build | 2 +- target/openrisc/mmu.c | 9 - target/ppc/cpu.h | 3 - target/ppc/cpu_init.c | 6 +- target/ppc/excp_helper.c | 41 +- target/ppc/internal.h | 17 +- target/ppc/user_only_helper.c | 15 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +- target/s390x/cpu.c | 7 +- target/s390x/s390x-internal.h | 9 + target/s390x/tcg/excp_helper.c | 45 +- target/s390x/tcg/mem_helper.c | 18 +- target/sh4/cpu.c | 2 +- target/sh4/cpu.h | 6 +- target/sh4/helper.c | 9 +- target/sh4/op_helper.c | 5 + target/sparc/cpu.c | 2 +- target/sparc/ldst_helper.c | 22 - target/sparc/meson.build | 2 +- target/sparc/mmu_helper.c | 115 +- target/xtensa/cpu.c | 2 +- target/xtensa/cpu.h | 2 +- target/xtensa/helper.c | 22 +- 112 files changed, 2163 insertions(+), 3539 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/alpha/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%) rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%) delete mode 100644 linux-user/host/riscv32/hostdep.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h delete mode 100644 target/mips/tcg/user/meson.build delete mode 100644 target/mips/tcg/user/tlb_helper.c