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from 50b5feaa94c tree-optimization/110777 - abnormals and recent PRE optimization new 42b17d00c33 VECT: Support floating-point in-order reduction for length [...] new 8390a2af139 RISC-V: Support in-order floating-point reduction

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Summary of changes: gcc/config/riscv/autovec.md | 39 ++++++++++++++++ gcc/config/riscv/riscv-protos.h | 13 +++++- gcc/config/riscv/riscv-v.cc | 53 ++++++++++++++++++---- .../rvv/autovec/reduc/reduc_strict-1.c} | 8 ++-- .../rvv/autovec/reduc/reduc_strict-2.c} | 6 +-- .../riscv/rvv/autovec/reduc/reduc_strict-3.c | 18 ++++++++ .../rvv/autovec/reduc/reduc_strict-4.c} | 4 +- .../rvv/autovec/reduc/reduc_strict-5.c} | 4 +- .../rvv/autovec/reduc/reduc_strict-6.c} | 7 +-- .../rvv/autovec/reduc/reduc_strict-7.c} | 6 +-- .../rvv/autovec/reduc/reduc_strict_run-1.c} | 6 +-- .../rvv/autovec/reduc/reduc_strict_run-2.c} | 6 +-- gcc/tree-vect-loop.cc | 41 +++++++++++++++-- 13 files changed, 169 insertions(+), 42 deletions(-) copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_1.c => riscv/rvv/autovec/r [...] copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_2.c => riscv/rvv/autovec/r [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_4.c => riscv/rvv/autovec/r [...] copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_5.c => riscv/rvv/autovec/r [...] copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_7.c => riscv/rvv/autovec/r [...] copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_9.c => riscv/rvv/autovec/r [...] copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_1_run.c => riscv/rvv/autov [...] copy gcc/testsuite/gcc.target/{aarch64/sve/reduc_strict_2_run.c => riscv/rvv/autov [...]