This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project.

from 780d30660e9 [VFS] Don't run symlink test on Windows, it may pass or fail adds 3213ce966b6 TailDuplication: Clear NoPHIs property adds 8fcce5ac73d Revert "[msan] Intercept qsort, qsort_r." adds ef7a659c21f Reland "[msan] Intercept qsort, qsort_r." adds c3d3569d4ca [mlir] Convert std.and/std.or ops to spv.LogicalAnd/spv.LogicalOr adds d8018233d1e Revert "CWG2352: Allow qualification conversions during ref [...] adds 596012b2567 [mlir][spirv] Update docs regarding how to define new ops a [...] adds e8c5600de8b [PowerPC][LoopVectorize]Add floating point reg usage test adds 1d891a32cf4 Support powerpc and sparc when building without init_array. adds c3dbd782f1e Revert "[ELF] Improve the condition to create .interp" adds b30d87a90ba [mlir][spirv] Add basic definitions for supporting availability adds 9acd9544db9 AMDGPU: Use Register adds e29ae3799ba TII: Fix using Register for a subregister index argument adds e9775bb5d81 Hexagon: Fix missing tablegen mode comment adds 5ce2ca524e9 AMDGPU/GlobalISel: Use SReg_32 for readfirstlane constraining adds 33a1b3d8fce [sanitizer] Link Sanitizer-x86_64-Test-Nolibc with -static adds dce7a362bed [ELF] Improve the condition to create .interp adds a33cab0f06e AMDGPU: Adjust test so it will work with GlobalISel adds c51b45e32ef DebugInfo: Fix rangesBaseAddress DICompileUnit bitcode seri [...] adds 22f34c7f34a lld: Remove explicit copy ops from AssociatedIterator, rely [...] adds f7910496c83 [Intrinsic] Delete tablegen rules of llvm.{sig,}{setjmp,longjmp} adds 044cc919f4b Delete setjmp_undefined_for_msvc workaround after llvm.setj [...] adds 0bc7665d988 [ADT] Fix FoldingSet documentation typos adds f83a8efe879 [mlir] Merge the successor operand count into BlockOperand. adds a3f89648132 [TargetLowering] Update comment to reference the correct co [...] adds d1b51c5de7a [PowerPC] Modify the hasSideEffects of some VSX instruction [...] adds 8612e92ed59 [lldb][NFC] Remove GetASTContext call in ClangDeclVendor adds 128f39da932 Fix crash in getFullyQualifiedName for inline namespace adds 34769e07835 SimplifyDemandedBits - Remove duplicate getOperand() call. NFC. adds a9ad65a2b34 [PowerPC] Change default for unaligned FP access for older [...]

No new revisions were added by this update.

Summary of changes: clang/include/clang/Basic/DiagnosticSemaKinds.td | 3 +- clang/lib/AST/QualTypeNames.cpp | 2 +- clang/lib/Sema/SemaExprCXX.cpp | 2 - clang/lib/Sema/SemaInit.cpp | 8 +- clang/lib/Sema/SemaOverload.cpp | 290 +++++++++--------- clang/test/CXX/drs/dr23xx.cpp | 33 +-- clang/test/CXX/drs/dr4xx.cpp | 11 +- clang/test/SemaObjCXX/arc-overloading.mm | 30 -- .../SemaOpenCL/address-spaces-conversions-cl2.0.cl | 18 +- clang/unittests/Tooling/QualTypeNamesTest.cpp | 11 + clang/www/cxx_dr_status.html | 4 +- clang/www/make_cxx_dr_status | 4 +- compiler-rt/lib/crt/crtbegin.c | 32 +- .../lib/sanitizer_common/tests/CMakeLists.txt | 2 +- lld/COFF/Chunks.h | 5 - .../ExpressionParser/Clang/ClangDeclVendor.cpp | 15 +- .../ExpressionParser/Clang/ClangDeclVendor.h | 8 +- .../Clang/ClangModulesDeclVendor.cpp | 6 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp | 11 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.h | 2 +- llvm/include/llvm/ADT/FoldingSet.h | 10 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +- llvm/include/llvm/IR/Intrinsics.td | 6 - llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 + llvm/lib/CodeGen/IntrinsicLowering.cpp | 8 - .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 18 +- llvm/lib/CodeGen/TailDuplication.cpp | 5 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 18 +- llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 2 +- llvm/lib/Target/PowerPC/PPC.td | 6 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 + llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 +- llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 + llvm/test/Assembler/dicompileunit.ll | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 4 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 2 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 2 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 2 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 8 +- .../CodeGen/AMDGPU/early-tailduplicator-nophis.mir | 41 +++ llvm/test/CodeGen/AMDGPU/read_register.ll | 16 +- llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll | 3 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 60 ++-- llvm/test/CodeGen/PowerPC/unaligned-floats.ll | 43 +++ llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- .../Transforms/LoopVectorize/PowerPC/reg-usage.ll | 91 ++++++ llvm/utils/TableGen/IntrinsicEmitter.cpp | 28 -- mlir/docs/Dialects/SPIR-V.md | 50 +++- mlir/include/mlir/Dialect/SPIRV/CMakeLists.txt | 16 +- mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td | 7 + .../mlir/Dialect/SPIRV/SPIRVAvailability.td | 86 ++++++ mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 154 +++++++++- .../mlir/Dialect/SPIRV/SPIRVNonUniformOps.td | 7 + mlir/include/mlir/Dialect/SPIRV/SPIRVOps.h | 23 +- mlir/include/mlir/IR/BlockSupport.h | 2 - mlir/include/mlir/IR/Operation.h | 16 +- mlir/include/mlir/IR/UseDefLists.h | 59 +++- .../Conversion/StandardToSPIRV/StandardToSPIRV.td | 16 +- mlir/lib/Dialect/SPIRV/CMakeLists.txt | 1 + mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 8 + mlir/lib/IR/Operation.cpp | 67 +---- mlir/lib/IR/Value.cpp | 33 +++ mlir/test/CMakeLists.txt | 1 + .../Conversion/StandardToSPIRV/std-to-spirv.mlir | 40 +++ mlir/test/Dialect/CMakeLists.txt | 1 + mlir/test/Dialect/SPIRV/CMakeLists.txt | 14 + mlir/test/Dialect/SPIRV/TestAvailability.cpp | 73 +++++ mlir/test/Dialect/SPIRV/availability.mlir | 31 ++ mlir/tools/mlir-opt/CMakeLists.txt | 1 + mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 328 ++++++++++++++++++++- 79 files changed, 1416 insertions(+), 538 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir create mode 100644 llvm/test/CodeGen/PowerPC/unaligned-floats.ll create mode 100644 mlir/include/mlir/Dialect/SPIRV/SPIRVAvailability.td create mode 100644 mlir/test/Dialect/CMakeLists.txt create mode 100644 mlir/test/Dialect/SPIRV/CMakeLists.txt create mode 100644 mlir/test/Dialect/SPIRV/TestAvailability.cpp create mode 100644 mlir/test/Dialect/SPIRV/availability.mlir