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from 988838da722 AVR: target/115065 - Tweak __clzhi2. new 3c9c52a1c0f [to-be-committed,RISC-V] Improve some shift-add sequences

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Summary of changes: gcc/config/riscv/riscv.md | 56 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/shift-add-1.c | 21 +++++++++++ 2 files changed, 77 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/shift-add-1.c