This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project.

from 0a2be46cfdb Modules: Invalidate out-of-date PCMs as they're discovered adds 2fd0d227f6b Fix slashes in path references in -Rmodule-import test from [...] adds b7db2e9f824 Stop relying on allocator behaviour in modules unit test adds 490975979be [ValueTracking] Move constant range computation into ValueT [...] adds e72381990e5 [git-llvm] Only use --force-interactive when supported adds b68566aec32 [runtime] Use --strip-all rather than --strip-sections adds 1a872f2b151 Recommit r355224 "[TableGen][SelectionDAG][X86] Add specifi [...] adds a2b144fc740 [TableGen] Make CheckImmAllOnesVMatcher and CheckImmAllZero [...] adds 369a011cee0 [lldb] [test] Make 2lwp_process_SIGSEGV test more portable adds bfec0d610cb [AArch64] Add tests for saddsat/ssubsat; NFC adds 0dc8c52d4e9 [X86] Remove dead code from the handler for INTR_TYPE_SCALA [...] adds 93e15dfacce [X86] Make lowering of intrinsics with rounding mode strict [...] adds 66c9690ad6e [X86] Remove unused variable. NFC adds 7d8260feb60 [CGP] fix comments; NFC adds 26e06e859e2 [x86] add x86-specific opcodes to extractelement scalarizat [...]

No new revisions were added by this update.

Summary of changes: clang/test/Modules/implicit-invalidate-chain.c | 46 +- clang/test/Modules/relative-import-path.c | 12 +- .../Serialization/InMemoryModuleCacheTest.cpp | 17 +- .../netbsd-core/2lwp_process_SIGSEGV.amd64 | Bin 15816 -> 16344 bytes .../netbsd-core/2lwp_process_SIGSEGV.amd64.core | Bin 121208 -> 121216 bytes .../postmortem/netbsd-core/2lwp_process_SIGSEGV.c | 7 +- .../postmortem/netbsd-core/TestNetBSDCore.py | 6 +- llvm/include/llvm/Analysis/ValueTracking.h | 5 + llvm/include/llvm/CodeGen/SelectionDAGISel.h | 2 + llvm/include/llvm/Target/TargetSelectionDAG.td | 13 +- llvm/lib/Analysis/InstructionSimplify.cpp | 239 +---- llvm/lib/Analysis/ValueTracking.cpp | 238 +++++ llvm/lib/CodeGen/CodeGenPrepare.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 + llvm/lib/Target/SystemZ/SystemZOperators.td | 20 +- llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 126 +-- llvm/lib/Target/X86/X86InstrAVX512.td | 88 +- llvm/lib/Target/X86/X86InstrSSE.td | 2 +- llvm/lib/Target/X86/X86InstrVecCompiler.td | 2 +- llvm/runtimes/llvm-strip-link.in | 2 +- llvm/test/CodeGen/AArch64/sadd_sat.ll | 73 ++ llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 923 ++++++++++++++++++++ llvm/test/CodeGen/AArch64/ssub_sat.ll | 74 ++ llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 965 +++++++++++++++++++++ .../CodeGen/X86/avx512-fma-intrinsics-upgrade.ll | 48 +- llvm/test/CodeGen/X86/avx512-fma-intrinsics.ll | 48 +- .../CodeGen/X86/avx512-intrinsics-fast-isel.ll | 40 +- llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 144 +-- llvm/test/CodeGen/X86/avx512-intrinsics-x86_64.ll | 24 +- llvm/test/CodeGen/X86/avx512-intrinsics.ll | 228 ++--- .../CodeGen/X86/avx512dq-intrinsics-upgrade.ll | 8 +- llvm/test/CodeGen/X86/avx512dq-intrinsics.ll | 24 +- llvm/test/CodeGen/X86/extractelement-fp.ll | 14 +- llvm/test/CodeGen/X86/fma-fneg-combine.ll | 12 +- llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll | 66 +- llvm/test/CodeGen/X86/vector-reduce-fmax.ll | 66 +- llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll | 66 +- llvm/test/CodeGen/X86/vector-reduce-fmin.ll | 66 +- llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 16 +- llvm/utils/TableGen/DAGISelMatcher.cpp | 23 + llvm/utils/TableGen/DAGISelMatcher.h | 36 + llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 10 + llvm/utils/TableGen/DAGISelMatcherGen.cpp | 21 + llvm/utils/git-svn/git-llvm | 5 +- 45 files changed, 2987 insertions(+), 851 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sadd_sat.ll create mode 100644 llvm/test/CodeGen/AArch64/sadd_sat_vec.ll create mode 100644 llvm/test/CodeGen/AArch64/ssub_sat.ll create mode 100644 llvm/test/CodeGen/AArch64/ssub_sat_vec.ll