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from adf4ac8b228 Revert "[InstCombine] Fold 'check for [no] signed truncatio [...] new 34ada1b5236 Add PowerPC e500(v2) core scheduler and directives. new e0adf6dabf3 Complete the SPE instruction set patterns new c486a43e863 Introduce codegen for the Signal Processing Engine

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Summary of changes: lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 20 + .../PowerPC/Disassembler/PPCDisassembler.cpp | 73 ++ lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h | 3 + lib/Target/PowerPC/PPC.td | 37 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 27 + lib/Target/PowerPC/PPCCallingConv.td | 42 +- lib/Target/PowerPC/PPCFastISel.cpp | 148 ++- lib/Target/PowerPC/PPCFrameLowering.cpp | 34 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 78 +- lib/Target/PowerPC/PPCISelLowering.cpp | 119 +- lib/Target/PowerPC/PPCISelLowering.h | 9 + lib/Target/PowerPC/PPCInstrInfo.cpp | 27 +- lib/Target/PowerPC/PPCInstrInfo.td | 117 +- lib/Target/PowerPC/PPCInstrSPE.td | 1209 +++++++++++++------- lib/Target/PowerPC/PPCRegisterInfo.cpp | 11 + lib/Target/PowerPC/PPCRegisterInfo.td | 25 + lib/Target/PowerPC/PPCSchedule.td | 3 + .../{PPCScheduleE500mc.td => PPCScheduleE500.td} | 195 ++-- lib/Target/PowerPC/PPCScheduleE500mc.td | 440 +++---- lib/Target/PowerPC/PPCScheduleP9.td | 5 +- lib/Target/PowerPC/PPCSubtarget.cpp | 11 + lib/Target/PowerPC/PPCSubtarget.h | 3 + test/CodeGen/PowerPC/2008-10-28-f128-i32.ll | 20 +- test/CodeGen/PowerPC/fast-isel-cmp-imm.ll | 9 + test/CodeGen/PowerPC/fast-isel-conversion.ll | 25 + test/CodeGen/PowerPC/fast-isel-load-store.ll | 13 + test/CodeGen/PowerPC/spe.ll | 542 +++++++++ .../Disassembler/PowerPC/ppc64-encoding-e500.txt | 515 ++++++++- test/MC/PowerPC/ppc64-encoding-spe.s | 160 ++- 29 files changed, 3084 insertions(+), 836 deletions(-) copy lib/Target/PowerPC/{PPCScheduleE500mc.td => PPCScheduleE500.td} (60%) create mode 100644 test/CodeGen/PowerPC/spe.ll