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from 11a2ca6eea8 [NFC] Remove overconfident assert from IRCE new e8a15e2fd6a [Doc] Guideline on adding exception handling support for a target new d1c00f71096 [DAGCombiner] Bail out if vector size is not a multiple new 959cee720da [Metadata] Extend 'count' field of DISubrange to take a met [...] new 20b5be1d099 [llvm-opt-fuzzer] Add couple of popular passes

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Summary of changes: docs/ExceptionHandling.rst | 63 +++++++++++++++++ docs/LangRef.rst | 16 +++++ include/llvm/IR/DIBuilder.h | 1 + include/llvm/IR/DebugInfoMetadata.h | 38 ++++++++-- lib/AsmParser/LLParser.cpp | 89 +++++++++++++++++++++++- lib/Bitcode/Reader/MetadataLoader.cpp | 25 +++++-- lib/Bitcode/Writer/BitcodeWriter.cpp | 5 +- lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 4 +- lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 4 +- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++ lib/FuzzMutate/FuzzerCLI.cpp | 8 +++ lib/IR/AsmWriter.cpp | 11 ++- lib/IR/DIBuilder.cpp | 4 ++ lib/IR/DebugInfoMetadata.cpp | 13 +++- lib/IR/LLVMContextImpl.h | 27 +++++-- lib/IR/Verifier.cpp | 7 +- test/Assembler/invalid-disubrange-count-node.ll | 4 ++ test/Bitcode/disubrange-v0.ll | 41 +++++++++++ test/Bitcode/disubrange-v0.ll.bc | Bin 0 -> 1492 bytes test/Bitcode/disubrange.ll | 49 +++++++++++++ test/CodeGen/AMDGPU/concat_vectors.ll | 12 ++++ test/Verifier/invalid-disubrange-count-node.ll | 37 ++++++++++ unittests/IR/MetadataTest.cpp | 29 +++++++- 23 files changed, 457 insertions(+), 34 deletions(-) create mode 100644 test/Assembler/invalid-disubrange-count-node.ll create mode 100644 test/Bitcode/disubrange-v0.ll create mode 100644 test/Bitcode/disubrange-v0.ll.bc create mode 100644 test/Bitcode/disubrange.ll create mode 100644 test/Verifier/invalid-disubrange-count-node.ll