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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig in repository toolchain/ci/qemu.

from 63b38f6c85 Merge tag 'pull-target-arm-20220707' of https://git.linaro.o [...] adds 7a867dd57a target/arm: Handle SME in aarch64_cpu_dump_state adds e67cd1cac2 target/arm: Add infrastructure for disas_sme adds 75fe83564a target/arm: Trap non-streaming usage when Streaming SVE is active adds 7160c8c55a target/arm: Mark ADR as non-streaming adds 39001c6b9b target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming adds ca363d233f target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as [...] adds 4464ee3634 target/arm: Mark PMULL, FMMLA as non-streaming adds 7272e98a74 target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming adds d79f3d5f2f target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming adds 46feb36151 target/arm: Mark string/histo/crypto as non-streaming adds 765ff97df3 target/arm: Mark gather/scatter load/store as non-streaming adds e1d1a64326 target/arm: Mark gather prefetch as non-streaming adds ccb1cefc38 target/arm: Mark LDFF1 and LDNF1 as non-streaming adds 3ebc26e79d target/arm: Mark LD1RO as non-streaming adds 3d74825f4d target/arm: Add SME enablement checks adds 285b1d5fce target/arm: Handle SME in sve_access_check adds 0d93576034 target/arm: Implement SME RDSVL, ADDSVL, ADDSPL adds ad939afbfa target/arm: Implement SME ZERO adds e9ad3ef19e target/arm: Implement SME MOVA adds 7390e0e9ab target/arm: Implement SME LD1, ST1 adds 8713f73e53 target/arm: Export unpredicated ld/st from translate-sve.c adds 4c46a5f12c target/arm: Implement SME LDR, STR adds bc4420d9bd target/arm: Implement SME ADDHA, ADDVA adds 558e956c71 target/arm: Implement FMOPA, FMOPS (non-widening) adds 920f640d39 target/arm: Implement BFMOPA, BFMOPS adds 3916841ac7 target/arm: Implement FMOPA, FMOPS (widening) adds 23a5e3859f target/arm: Implement SME integer outer product adds 598ab0b24c target/arm: Implement PSEL adds 7dbfafc157 target/arm: Implement REVD adds 6b5a3bdf3a target/arm: Implement SCLAMP, UCLAMP adds 04fbce7639 target/arm: Reset streaming sve state on exception boundaries adds 78cb977666 target/arm: Enable SME for -cpu max adds 95aa4fdd58 linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS adds 2a98579711 linux-user/aarch64: Reset PSTATE.SM on syscalls adds 4a29c36316 linux-user/aarch64: Add SM bit to SVE signal context adds 5726597c3b linux-user/aarch64: Tidy target_restore_sigframe error return adds affb1a50b9 linux-user/aarch64: Do not allow duplicate or short sve records adds 8e5e19ee41 linux-user/aarch64: Verify extra record lock succeeded adds d3b4f7170f linux-user/aarch64: Move sve record checks into restore adds 78fd56ba13 linux-user/aarch64: Implement SME signal handling adds fd72f5d0ba linux-user: Rename sve prctls adds 24d87c187c linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL adds 4630353559 target/arm: Only set ZEN in reset if SVE present adds 78011586b9 target/arm: Enable SME for user-only adds f9982ceaf2 linux-user/aarch64: Add SME related hwcap entries adds 9fed1bca6b Merge tag 'pull-target-arm-20220711' of https://git.linaro.o [...] adds ba8924113c tcg: Fix returned type in alloc_code_gen_buffer_splitwx_memfd() adds b0f650f047 accel/tcg: Fix unaligned stores to s390x low-address-protect [...] adds 08c8a31214 Merge tag 'pull-tcg-20220712' of https://gitlab.com/rth7680/ [...] adds f085ba292b gitlab-ci/cirrus: Update freebsd to python 3.9 packages adds 05b47eec90 iotests: fix copy-before-write for macOS and FreeBSD adds 9548cbefff iotests/copy-before-write: specify required_fmts

No new revisions were added by this update.

Summary of changes: .gitlab-ci.d/cirrus/freebsd-12.vars | 3 +- .gitlab-ci.d/cirrus/freebsd-13.vars | 3 +- accel/tcg/cputlb.c | 8 +- docs/system/arm/emulation.rst | 4 + linux-user/aarch64/cpu_loop.c | 9 + linux-user/aarch64/signal.c | 241 +++++- linux-user/aarch64/target_cpu.h | 5 +- linux-user/aarch64/target_prctl.h | 62 +- linux-user/elfload.c | 20 + linux-user/syscall.c | 28 +- target/arm/cpu.c | 35 +- target/arm/cpu.h | 7 + target/arm/cpu64.c | 11 + target/arm/helper-sme.h | 126 +++ target/arm/helper-sve.h | 4 + target/arm/helper.c | 56 +- target/arm/helper.h | 18 + target/arm/meson.build | 3 + target/arm/sme-fa64.decode | 60 ++ target/arm/sme.decode | 88 +++ target/arm/sme_helper.c | 1140 ++++++++++++++++++++++++++++ target/arm/sve.decode | 41 +- target/arm/sve_helper.c | 28 + target/arm/translate-a64.c | 103 ++- target/arm/translate-a64.h | 45 ++ target/arm/translate-sme.c | 373 +++++++++ target/arm/translate-sve.c | 393 ++++++++-- target/arm/translate-vfp.c | 12 + target/arm/translate.c | 2 + target/arm/translate.h | 16 + target/arm/vec_helper.c | 24 + tcg/region.c | 2 +- tests/qemu-iotests/tests/copy-before-write | 8 +- 33 files changed, 2837 insertions(+), 141 deletions(-) create mode 100644 target/arm/sme-fa64.decode create mode 100644 target/arm/sme.decode create mode 100644 target/arm/translate-sme.c