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from 5571fe4bfcf [AMDGPU] Fix the mis-handling of `vreg_1` copied from scala [...] new e0b950eae9b AMDGPU: Don't enable all lanes with non-CSR VGPR spills

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Summary of changes: lib/Target/AMDGPU/SIFrameLowering.cpp | 88 +++++++++++++++++-------------- test/CodeGen/AMDGPU/callee-frame-setup.ll | 16 ++++++ 2 files changed, 65 insertions(+), 39 deletions(-)