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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig in repository toolchain/ci/llvm-project.

from f314bcffa3c [llvm-reduce][test] Make remove-alias.ll CHECK patterns mor [...] adds 553d4d08d2b [MC] Report locations for .symver errors adds e4c360a897f [MC][ELF] Drop MCSymbol::isExternal call sites adds 29eb3dcfe62 [PowerPC] Materialize i64 constants by enumerated patterns. adds 7b9890e17e9 [MC][ELF] Remove unneeded MCSymbol::setExternal calls adds 26d378b801f [PowerPC][NFC] Added assertion of shift exponent is too lar [...] adds e0963ae274b [AsmParser] make .ascii support spaces as separators adds 3183add5343 [RISCV] Define the remaining vector fixed-point arithmetic [...] adds e2303a448e2 [FastRA] Fix handling of bundled MIs adds 8ffda237a66 MCContext::reportError: don't call report_fatal_error adds 1635dea266c [AsmPrinter] Replace a reachable report_fatal_error with MC [...] adds f6c7ebe76ac [MLIR][SPIRVToLLVM] Updated documentation on entry points a [...] adds 3bf7d47a977 [NFC][InstructionCost] Remove isValid() asserts in SLPVecto [...] adds 27b7d646886 [clang][cli] Streamline MarshallingInfoFlag description adds 70410a26494 [clang][cli] Let denormalizer decide how to render the opti [...] adds 5a85526728c [clang] Use enum for LangOptions::SYCLVersion instead of unsigned adds 93da221eaf7 [VP][NFC] ISD::VP_Sub -> ISD::VP_SUB adds cd608dc8d3e [VPlan] Use VPDef for VPInterleaveRecipe. adds d99e4a4840d [VE] Support RETURNADDR adds 5e273b845bc [VE] Support STACKSAVE and STACKRESTORE adds d6abd7317a2 [flang][driver] Make the names of files created in unit tes [...] adds 06b83fd6c75 [TableGen] NFC: Switch to range-based for loops in OptParse [...] adds 164bcbd40e6 [TableGen] NFC: Rename variables in OptParserEmitter adds a3a896d1cdc [VE] Optimize LEA combinations adds b2ba6867eac Refactoring the attribute plugin example to fit the new API adds 6f45049fb6e [Statepoints] Disable VReg lowering for values used on exce [...] adds f2508923737 [VPlan] Make VPRecipeBase inherit from VPDef. adds 8c2ad9e85f6 [VE] Correct VMP allocation in calling conv adds d6118759f30 [InstSimplify] add tests for inverted logic operands; NFC adds 38ca7face67 [InstSimplify] reduce logic with inverted add/sub ops adds 3a675c777dd [TableGen] Add the !substr() bang operator adds 88c5b500606 [AggressiveInstCombine] Generalize foldGuardedRotateToFunne [...] adds d56982b6f5f Remove unused variables. adds 554eb1f6dc4 Revert "[TableGen] Add the !substr() bang operator" adds e25afcfa51a [ELF][PPC64] Detect missing R_PPC64_TLSGD/R_PPC64_TLSLD and [...] adds fb3c1b3de5c [ELF] Reject local-exec TLS relocations for -shared adds 9a93f95fce9 [clang] Fix expected errors in plugin attribute example adds 26c8f9081b6 [mlir[[vector] Extend Transfer read/write ops to support te [...] adds a323682dcbf [AMDGPU][MC][NFC] Lit tests cleanup adds 8ab5770a17f [AMDGPU][MC][NFC] Parser refactoring adds f4f49d9d0d6 [AMDGPU][MC][NFC] Fix for sanitizer error in 8ab5770 adds bb8d20d9f3b [cuda][hip] Fix typoes in header wrappers. adds dfa40840e0e scudo: Remove ANDROID_EXPERIMENTAL_MTE macro. adds 43def795aac Update references to 'master' branch. adds 82bd64fff63 [AA] byval argument is identified function local adds 3fa2d37eb3f [clangd][NFC] Improve clangd status messages adds 3f3ab03ab7b [lldb] Remove anonymous namespace from NativeRegisterContex [...] adds a817594de92 [lld-macho][nfc] Clean up tests adds 0f8224c2104 [lld-macho][nfc] Remove %T from headerpad.s adds 8f933a4e931 [openacc] Use TableGen enum for default clause value adds b7ae1d3d2b1 [mlir][Linalg] Revisit the Linalg on tensors abstraction adds bd2e83333ec [lldb] [Process/FreeBSDRemote] Remove anonymous namespace adds 9d2529a38b3 [MLIR][Docs] Fix a small typo in documentation. adds 7c7b55b9851 [mlir][vector] Extend vector unroll to all element-wise ops adds ffba47df764 Revert "[AMDGPU][HIP] Switch default DWARF version to 5" adds 76f4f42ebaf [NewPM] Add TargetMachine method to add alias analyses adds d33abc337c7 Migrate MCContext::createTempSymbol call sites to AlwaysAdd [...] adds d9a0c40bce5 [MC] Split MCContext::createTempSymbol, default AlwaysAddSu [...] adds 9a8cab8bacc [mlir][sparse] adjust output tensor to synthetic tensor adds ed73a78924a [RISCV] Define the vand, vor and vxor RVV intrinsics adds 0935b0c8695 [NFC] Remove unused function adds be961374611 [MLIR][SPIRVToLLVM] Updated documentation on spirv-cpu-runner adds 4ad0cfd4de4 llvm-profgen: Parse command line arguments after initializi [...] adds 7f40bb3b044 HowToReleaseLLVM: Update document to match the current rele [...] adds 6bbb04a732c [Driver] Default Generic_GCC ppc/ppc64/ppc64le to -fasynchr [...] adds c60a58f8d43 [InstCombine] Add check of i1 types in select-to-zext/sext [...] adds 83274a0773f [mlir] Add SmallVector sizes adds 704981b4373 [RISCV] Update vmv.v.v-rv32.ll and vmv.v.v-rv64.ll to test [...] adds e18734f87a6 [RISCV] Use more precise type constraints for the vmv.v.v a [...] adds d7a6f3a1056 [LoopNest] Extend `LPMUpdater` and adaptor to handle loop-n [...] adds 8c85aae6c5b [MC][test] Reorganize .cfi_* tests adds 6e2af4d6046 Revert "[mlir] Add SmallVector sizes" adds b15ba2cf6fd [RISCV] Add intrinsics for vmacc/vnmsac/vmadd/vnmsub instructions adds 13f439a1872 [lld/mac] Implement support for private extern symbols adds dbb01536f6f scan-view: Remove Reporter.py and associated AppleScript files new ec17c4f0755 [CSKY 3/n] Add bare-bones C-SKY MCTargetDesc

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: clang-tools-extra/clangd/ClangdServer.cpp | 8 +- clang-tools-extra/clangd/TUScheduler.cpp | 2 +- clang/docs/ReleaseNotes.rst | 4 + clang/examples/Attribute/Attribute.cpp | 49 +- clang/include/clang/Basic/LangOptions.def | 2 +- clang/include/clang/Basic/LangOptions.h | 5 + clang/include/clang/Driver/Options.td | 44 +- clang/lib/Driver/ToolChains/AMDGPU.h | 2 +- clang/lib/Driver/ToolChains/Gnu.cpp | 3 + clang/lib/Driver/ToolChains/HIP.h | 2 +- clang/lib/Frontend/CompilerInvocation.cpp | 88 +- clang/lib/Frontend/InitPreprocessor.cpp | 2 +- clang/lib/Headers/cuda_wrappers/algorithm | 2 +- clang/lib/Headers/cuda_wrappers/new | 2 +- clang/test/Driver/amdgpu-toolchain.c | 2 +- clang/test/Driver/hip-toolchain-dwarf.hip | 2 +- clang/test/Driver/ppc-features.cpp | 12 +- clang/test/Frontend/plugin-attribute.cpp | 39 +- clang/tools/scan-view/CMakeLists.txt | 3 - clang/tools/scan-view/share/FileRadar.scpt | Bin 18418 -> 0 bytes clang/tools/scan-view/share/GetRadarVersion.scpt | 0 clang/tools/scan-view/share/Reporter.py | 251 --- .../unittests/Frontend/CompilerInvocationTest.cpp | 44 +- compiler-rt/lib/scudo/standalone/linux.cpp | 9 +- compiler-rt/lib/scudo/standalone/memtag.h | 29 +- flang/include/flang/Parser/dump-parse-tree.h | 6 +- flang/include/flang/Parser/parse-tree.h | 3 +- flang/lib/Parser/openacc-parsers.cpp | 6 +- flang/lib/Parser/unparse.cpp | 4 +- flang/lib/Semantics/resolve-directives.cpp | 4 +- flang/unittests/Frontend/FrontendActionTest.cpp | 4 +- lld/ELF/InputFiles.h | 4 + lld/ELF/Relocations.cpp | 61 +- lld/MachO/Driver.cpp | 2 +- lld/MachO/InputFiles.cpp | 30 +- lld/MachO/Options.td | 2 +- lld/MachO/SymbolTable.cpp | 19 +- lld/MachO/SymbolTable.h | 5 +- lld/MachO/Symbols.h | 35 +- lld/MachO/SyntheticSections.cpp | 49 +- lld/MachO/SyntheticSections.h | 1 + lld/test/ELF/Inputs/i386-static-tls-model4.s | 9 - lld/test/ELF/aarch64-tls-le.s | 8 + lld/test/ELF/arm-tls-le32.s | 7 + lld/test/ELF/i386-static-tls-model.s | 8 - lld/test/ELF/i386-tls-le.s | 57 +- lld/test/ELF/i386-zrel-zrela.s | 8 +- lld/test/ELF/mips-tls-hilo.s | 6 +- lld/test/ELF/ppc64-local-exec-tls.s | 12 + lld/test/ELF/ppc64-tls-missing-gdld.s | 85 +- lld/test/ELF/riscv-tls-le.s | 7 + lld/test/ELF/tls.s | 20 + lld/test/ELF/x86-64-reloc-tpoff32-fpic.s | 14 - lld/test/MachO/Inputs/libfunction.s | 6 - lld/test/MachO/archive.s | 30 +- lld/test/MachO/common-symbol-resolution.s | 3 +- lld/test/MachO/dylink-lazy.s | 2 +- lld/test/MachO/filelist.s | 22 +- lld/test/MachO/force-load.s | 22 +- lld/test/MachO/framework.s | 12 +- lld/test/MachO/headerpad.s | 46 +- lld/test/MachO/invalid/archive-no-index.s | 25 +- lld/test/MachO/invalid/bad-archive-member.s | 3 +- lld/test/MachO/lto-archive.ll | 3 +- lld/test/MachO/objc.s | 4 +- lld/test/MachO/order-file.s | 1 - lld/test/MachO/private-extern.s | 143 ++ lld/test/MachO/resolution.s | 16 +- lld/test/MachO/section-merge.s | 41 +- lld/test/MachO/stabs.s | 3 +- lld/test/MachO/subsections-section-relocs.s | 12 +- lld/test/MachO/subsections-symbol-relocs.s | 37 +- lld/test/MachO/symbol-order.s | 42 +- lld/test/MachO/symtab.s | 35 +- lld/test/MachO/weak-definition-direct-fetch.s | 22 +- lld/test/MachO/weak-definition-indirect-fetch.s | 24 +- lld/test/MachO/weak-definition-order.s | 21 +- lld/test/MachO/weak-definition-over-dysym.s | 35 +- lld/test/MachO/weak-private-extern.s | 38 + .../NativeRegisterContextFreeBSD_x86_64.cpp | 8 +- .../Linux/NativeRegisterContextLinux_x86_64.cpp | 12 +- llvm/docs/CodingStandards.rst | 2 +- llvm/docs/DeveloperPolicy.rst | 4 +- llvm/docs/FAQ.rst | 2 +- llvm/docs/GettingStarted.rst | 10 +- llvm/docs/GitBisecting.rst | 6 +- llvm/docs/GlobalISel/IRTranslator.rst | 2 +- llvm/docs/HowToReleaseLLVM.rst | 67 +- llvm/docs/LibFuzzer.rst | 4 +- llvm/docs/TestingGuide.rst | 2 +- llvm/docs/TypeMetadata.rst | 2 +- llvm/include/llvm/Analysis/AliasAnalysis.h | 3 - llvm/include/llvm/Analysis/LazyCallGraph.h | 1 - llvm/include/llvm/Frontend/OpenACC/ACC.td | 8 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 79 +- llvm/include/llvm/IR/VPIntrinsics.def | 2 +- llvm/include/llvm/MC/MCAssembler.h | 7 +- llvm/include/llvm/MC/MCContext.h | 16 +- llvm/include/llvm/MC/MCSymbol.h | 3 +- llvm/include/llvm/Option/OptParser.td | 12 +- llvm/include/llvm/Passes/PassBuilder.h | 3 + llvm/include/llvm/Target/TargetMachine.h | 5 + .../llvm/Transforms/Scalar/LoopPassManager.h | 105 +- llvm/lib/Analysis/AliasAnalysis.cpp | 10 +- llvm/lib/Analysis/InstructionSimplify.cpp | 33 + llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 4 +- llvm/lib/CodeGen/MachineModuleInfo.cpp | 3 +- llvm/lib/CodeGen/RegAllocFast.cpp | 43 + .../CodeGen/SelectionDAG/StatepointLowering.cpp | 24 +- llvm/lib/MC/ELFObjectWriter.cpp | 19 +- llvm/lib/MC/MCContext.cpp | 23 +- llvm/lib/MC/MCDwarf.cpp | 10 +- llvm/lib/MC/MCELFStreamer.cpp | 16 +- llvm/lib/MC/MCObjectStreamer.cpp | 2 +- llvm/lib/MC/MCParser/AsmParser.cpp | 13 +- llvm/lib/MC/MCSection.cpp | 2 +- llvm/lib/MC/MCStreamer.cpp | 2 +- llvm/lib/Passes/PassBuilder.cpp | 4 + .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 171 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +- .../lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 2 - llvm/lib/Target/CSKY/CMakeLists.txt | 2 + llvm/lib/Target/CSKY/CSKYInstrInfo.td | 6 +- llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt | 15 + .../Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp | 69 + llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h | 39 + .../CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp | 45 + .../lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp | 25 + llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h | 29 + .../Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp | 71 + .../Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h | 61 + .../Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp | 62 + .../Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h | 48 + llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp | 5 - llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 532 ++--- llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 3 +- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 3 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 129 ++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 1 + llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 1 + llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp | 4 +- llvm/lib/Target/VE/VECallingConv.td | 4 +- llvm/lib/Target/VE/VEISelLowering.cpp | 26 + llvm/lib/Target/VE/VEInstrInfo.td | 4 + .../AggressiveInstCombine.cpp | 71 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 4 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 5 +- llvm/lib/Transforms/Scalar/LoopPassManager.cpp | 11 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 30 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 12 +- llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h | 4 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 48 +- llvm/lib/Transforms/Vectorize/VPlan.h | 204 +- llvm/lib/Transforms/Vectorize/VPlanValue.h | 35 +- llvm/test/Analysis/BasicAA/noalias-param.ll | 4 +- .../AMDGPU/GlobalISel/lds-zero-initializer.ll | 4 +- llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir | 26 + llvm/test/CodeGen/AMDGPU/lds-initializer.ll | 4 +- llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll | 4 +- .../llvm.amdgcn.ds.gws.barrier-fastregalloc.ll | 19 + llvm/test/CodeGen/PowerPC/aix-cc-abi.ll | 2 +- llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll | 4 +- llvm/test/CodeGen/PowerPC/bperm.ll | 26 +- llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll | 11 +- llvm/test/CodeGen/PowerPC/constants-i64.ll | 145 +- llvm/test/CodeGen/PowerPC/f128-fma.ll | 8 +- llvm/test/CodeGen/PowerPC/f128-passByValue.ll | 4 +- llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll | 6 +- llvm/test/CodeGen/PowerPC/fp-strict-f128.ll | 6 +- llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll | 8 +- .../PowerPC/fp128-bitcast-after-operation.ll | 12 +- llvm/test/CodeGen/PowerPC/funnel-shift.ll | 12 +- .../PowerPC/memCmpUsedInZeroEqualityComparison.ll | 8 +- llvm/test/CodeGen/PowerPC/negctr.ll | 7 +- llvm/test/CodeGen/PowerPC/ori_imm32.ll | 2 +- llvm/test/CodeGen/PowerPC/ori_imm64.ll | 9 +- llvm/test/CodeGen/PowerPC/p10-spill-crun.ll | 4 +- .../PowerPC/pcrel-call-linkage-with-calls.ll | 20 +- llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll | 80 +- .../test/CodeGen/PowerPC/pcrel-linkeropt-option.ll | 8 +- llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll | 48 +- .../PowerPC/pcrel-relocation-plus-offset.ll | 8 +- llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll | 4 +- llvm/test/CodeGen/PowerPC/pcrel.ll | 4 +- llvm/test/CodeGen/PowerPC/pr43976.ll | 2 +- llvm/test/CodeGen/PowerPC/pr45448.ll | 5 +- .../rematerializable-instruction-machine-licm.ll | 147 +- llvm/test/CodeGen/PowerPC/sms-grp-order.ll | 36 +- llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 72 +- .../PowerPC/tailcall-speculatable-callee.ll | 6 +- .../CodeGen/PowerPC/unaligned-addressing-mode.ll | 5 +- llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll | 1441 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll | 1761 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll | 1441 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll | 1761 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll | 1945 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll | 2377 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll | 1441 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll | 1761 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll | 1441 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll | 1761 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll | 1261 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll | 1513 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll | 1261 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll | 1513 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll | 662 +++--- llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll | 706 +++--- llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll | 1189 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll | 1621 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll | 1189 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll | 1621 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll | 1261 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll | 1513 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll | 1261 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll | 1513 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll | 1945 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll | 2377 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 1441 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll | 1761 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll | 1945 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll | 2377 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll | 1945 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll | 2377 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll | 1945 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll | 2377 ++++++++++++++++++++ llvm/test/CodeGen/VE/Scalar/lea-opt.ll | 63 + llvm/test/CodeGen/VE/Scalar/returnaddr.ll | 91 + llvm/test/CodeGen/VE/Scalar/stacksave.ll | 26 + llvm/test/CodeGen/VE/Vector/fastcc_callee.ll | 8 + llvm/test/CodeGen/X86/equiv_with_vardef.ll | 5 +- llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll | 45 +- llvm/test/CodeGen/XCore/section-name.ll | 4 +- llvm/test/MC/AMDGPU/flat-gfx9.s | 1 - llvm/test/MC/AMDGPU/flat-global.s | 1 - llvm/test/MC/AMDGPU/flat.s | 6 - llvm/test/MC/AMDGPU/fma-mix.s | 4 - llvm/test/MC/AMDGPU/literal16.s | 1 + llvm/test/MC/AMDGPU/mad-mix.s | 4 - llvm/test/MC/AMDGPU/smem.s | 1 - llvm/test/MC/AMDGPU/vop1-gfx9-err.s | 1 - llvm/test/MC/AMDGPU/vop1.s | 2 +- llvm/test/MC/AsmParser/directive_ascii.s | 8 + llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt | 2 +- llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt | 2 +- llvm/test/MC/ELF/{fde.s => cfi-fde-encoding.s} | 0 .../return-column.s => ELF/cfi-return-column.s} | 0 llvm/test/MC/{X86 => ELF}/cfi-scope-errors.s | 0 .../cfi-scope-errors2.s} | 7 +- llvm/test/MC/{X86 => ELF}/expand-var.s | 0 llvm/test/MC/ELF/invalid-symver.s | 7 - llvm/test/MC/ELF/multiple-different-symver.s | 6 - llvm/test/MC/ELF/multiple-equiv-symver.s | 6 - llvm/test/MC/ELF/symver-err.s | 12 + llvm/test/MC/X86/{pr38826.s => cfi_offset-eip.s} | 0 ...ef_cfa-crash.s => compact-unwind-cfi_def_cfa.s} | 0 llvm/test/MC/X86/fde-reloc.s | 11 - llvm/test/TableGen/directive1.td | 13 + .../Transforms/AggressiveInstCombine/funnel.ll | 118 +- .../Transforms/AggressiveInstCombine/rotate.ll | 11 +- llvm/test/Transforms/InstSimplify/AndOrXor.ll | 324 ++- llvm/tools/llvm-profgen/llvm-profgen.cpp | 4 +- .../Transforms/Scalar/LoopPassManagerTest.cpp | 77 +- llvm/unittests/Transforms/Vectorize/VPlanTest.cpp | 57 +- llvm/utils/TableGen/DirectiveEmitter.cpp | 22 + llvm/utils/TableGen/OptParserEmitter.cpp | 41 +- mlir/docs/Dialects/Linalg.md | 110 +- mlir/docs/PatternRewriter.md | 2 +- mlir/docs/SPIRVToLLVMDialectConversion.md | 188 +- .../Dialect/Linalg/Analysis/DependenceAnalysis.h | 14 +- mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h | 15 +- mlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h | 1 + mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h | 9 +- .../mlir/Dialect/Linalg/IR/LinalgStructuredOps.td | 122 +- .../Linalg/IR/LinalgStructuredOpsInterface.td | 632 +++--- mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h | 166 -- mlir/include/mlir/Dialect/StandardOps/IR/Ops.td | 20 +- mlir/include/mlir/Dialect/Vector/VectorOps.h | 2 +- mlir/include/mlir/Dialect/Vector/VectorOps.td | 65 +- mlir/include/mlir/Dialect/Vector/VectorUtils.h | 4 +- mlir/include/mlir/IR/OpBase.td | 5 + mlir/include/mlir/Interfaces/VectorInterfaces.td | 28 +- .../Dialect/Linalg/CPU/test-tensor-matmul.mlir | 2 +- .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp | 16 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 46 +- .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 6 +- mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp | 41 +- .../Dialect/Linalg/Analysis/DependenceAnalysis.cpp | 94 +- mlir/lib/Dialect/Linalg/EDSC/Builders.cpp | 65 +- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 390 ++-- mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp | 113 +- .../lib/Dialect/Linalg/Transforms/DropUnitDims.cpp | 17 +- .../Linalg/Transforms/ElementwiseToLinalg.cpp | 62 +- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 50 +- .../Dialect/Linalg/Transforms/FusionOnTensors.cpp | 152 +- .../Dialect/Linalg/Transforms/Generalization.cpp | 8 +- mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp | 4 +- mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 11 +- .../Dialect/Linalg/Transforms/Sparsification.cpp | 20 +- mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp | 58 +- mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp | 17 +- .../Dialect/Linalg/Transforms/Vectorization.cpp | 11 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 6 - mlir/lib/Dialect/StandardOps/IR/Ops.cpp | 4 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 154 +- .../Dialect/Vector/VectorTransferOpTransforms.cpp | 4 +- mlir/lib/Dialect/Vector/VectorTransforms.cpp | 57 +- mlir/lib/Dialect/Vector/VectorUtils.cpp | 12 +- mlir/test/Dialect/Linalg/bufferize.mlir | 88 +- .../Linalg/canonicalize-duplicate-inputs.mlir | 38 +- mlir/test/Dialect/Linalg/canonicalize.mlir | 9 +- .../Linalg/convert-elementwise-to-linalg.mlir | 72 +- .../test/Dialect/Linalg/drop-unit-extent-dims.mlir | 61 +- mlir/test/Dialect/Linalg/fold-unit-trip-loops.mlir | 21 +- mlir/test/Dialect/Linalg/fusion-tensor.mlir | 439 ++-- mlir/test/Dialect/Linalg/generalize-named-ops.mlir | 12 +- mlir/test/Dialect/Linalg/invalid.mlir | 137 +- mlir/test/Dialect/Linalg/parallel-loops.mlir | 4 +- mlir/test/Dialect/Linalg/reshape_fusion.mlir | 211 +- .../Linalg/reshape_linearization_fusion.mlir | 206 +- mlir/test/Dialect/Linalg/roundtrip.mlir | 68 +- mlir/test/Dialect/Linalg/sparse_1d.mlir | 81 +- mlir/test/Dialect/Linalg/sparse_2d.mlir | 81 +- mlir/test/Dialect/Linalg/sparse_3d.mlir | 101 +- mlir/test/Dialect/Linalg/sparse_invalid.mlir | 112 +- mlir/test/Dialect/Linalg/sparse_parallel.mlir | 12 +- mlir/test/Dialect/Linalg/sparse_storage.mlir | 5 +- mlir/test/Dialect/Linalg/tile-and-distribute.mlir | 4 +- .../test/Dialect/Linalg/tile-and-fuse-tensors.mlir | 8 +- mlir/test/Dialect/Linalg/tile-tensors.mlir | 6 +- mlir/test/Dialect/Vector/invalid.mlir | 12 +- mlir/test/Dialect/Vector/ops.mlir | 48 + mlir/test/Dialect/Vector/vector-transforms.mlir | 36 +- mlir/test/EDSC/builder-api-test.cpp | 12 +- mlir/test/lib/Transforms/TestVectorTransforms.cpp | 5 +- .../mlir-linalg-ods-gen/test-linalg-ods-gen.tc | 3 - .../mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp | 28 +- 338 files changed, 61430 insertions(+), 4912 deletions(-) delete mode 100644 clang/tools/scan-view/share/FileRadar.scpt delete mode 100644 clang/tools/scan-view/share/GetRadarVersion.scpt delete mode 100644 clang/tools/scan-view/share/Reporter.py delete mode 100644 lld/test/ELF/Inputs/i386-static-tls-model4.s delete mode 100644 lld/test/ELF/x86-64-reloc-tpoff32-fpic.s delete mode 100644 lld/test/MachO/Inputs/libfunction.s create mode 100644 lld/test/MachO/private-extern.s create mode 100644 lld/test/MachO/weak-private-extern.s create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp create mode 100644 llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h create mode 100644 llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/lea-opt.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/returnaddr.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/stacksave.ll rename llvm/test/MC/ELF/{fde.s => cfi-fde-encoding.s} (100%) rename llvm/test/MC/{X86/return-column.s => ELF/cfi-return-column.s} (100%) rename llvm/test/MC/{X86 => ELF}/cfi-scope-errors.s (100%) rename llvm/test/MC/{X86/cfi-open-within-another-crash.s => ELF/cfi-scope-errors2. [...] rename llvm/test/MC/{X86 => ELF}/expand-var.s (100%) delete mode 100644 llvm/test/MC/ELF/invalid-symver.s delete mode 100644 llvm/test/MC/ELF/multiple-different-symver.s delete mode 100644 llvm/test/MC/ELF/multiple-equiv-symver.s create mode 100644 llvm/test/MC/ELF/symver-err.s rename llvm/test/MC/X86/{pr38826.s => cfi_offset-eip.s} (100%) rename llvm/test/MC/X86/{cfi_def_cfa-crash.s => compact-unwind-cfi_def_cfa.s} (100%) delete mode 100644 llvm/test/MC/X86/fde-reloc.s delete mode 100644 mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h