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from 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. new 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. new 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...]

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Summary of changes: gcc/ChangeLog | 82 ++++++++ gcc/config/arm/arm-builtins.c | 20 ++ gcc/config/arm/arm_mve.h | 202 ++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 18 ++ gcc/config/arm/mve.md | 206 ++++++++++++++++++++- gcc/testsuite/ChangeLog | 35 ++++ .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqrshr.c} | 8 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 ++ .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 ++ .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshl.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshr.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 8 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 ++ .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 ++ .../arm/mve/intrinsics/{vbicq_n_u32.c => uqshl.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 8 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 8 +- .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 11 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 11 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 11 +- .../intrinsics/{vaddq_x_n_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 16 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 11 +- gcc/testsuite/lib/target-supports.exp | 6 + 29 files changed, 704 insertions(+), 85 deletions(-) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_x_n_u16.c => vshlcq_m_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%)