This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os-vs-Os_LTO in repository toolchain/ci/binutils-gdb.

from 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script adds f0c1efa53d Automatic date update in version.in adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test. adds 0e7620dcdc sim: bfin: delete accidental ADI copyright adds a75a6a4164 [GOLD] powerpc assertion failure adds 30845f113a PowerPC use_local_plt adds 0c4e2c6c88 [gdb/testsuite] Fix gdb.arch/i386-mpx.exp with -m32 adds 1485212328 [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32 adds c98de297b3 libctf, ld: fix data symbol test with newer GCC adds e05a3e5a49 libctf: lookup_by_name: do not return success for nonexisten [...] adds 26503e2f5e libctf, create: fix ctf_type_add of structs with unnamed members adds ccbe4c82d5 Use gdb::array_view for setting value bytes in trad-frame adds c65ca138c4 sim: ppc: update version script usage adds bdec2917b1 Convert some frame functions to use gdb::array_view. adds a9a87d3525 trad-frame cleanups adds 1c3b85ad28 use DISABLE_COPY_AND_ASSIGN in switch_thru_all_uis adds 11321a0505 Automatic date update in version.in adds 8bd10d6b16 PowerPC64 synthetic symbols adds 4bd7c90276 PowerPC: Don't generate unused section symbols adds 037e8112b9 [gdb/server] Don't overwrite fs/gs_base with -m32 adds 6f52fdf404 Fix a few stap parser issues and add a new test for probe ex [...] adds 1402665c8f [gdb/testsuite] Skip gdb.rust/*.exp for target board unix/-m32 adds 7c794afd54 [gdb/testsuite] Fix gdb.python/py-format-string.exp with -m32 adds 6571ffc620 gdb/testsuite: add links for handled control sequences in li [...] adds c3e96aa78f gdb/testsuite: rename _cur_x/_cur_y to _cur_col/_cur_row in [...] adds 3f0781f389 Automatic date update in version.in adds a6c11cbb14 gdb/remote.c: address conflicting enum and method name adds 6bd434d6ca gdb: make some variables static adds 17e593e966 gdb/dwarf: add some logging in dwarf2/read.c adds de53369b2e gdb/dwarf: add assertion in maybe_queue_comp_unit adds f9e9ba90b3 gdb/testsuite: use multi_line in gdb.base/skip.exp adds d4dd4fca16 gdb: change debug_bfd_cache to bool adds c78eec4424 mips XPASS pr26936 adds 498ff0328f PR27218, memory access violation in dwarf2dbg.c adds be07043ea8 PR27221, 058430b4a1 warnings while assembling the Linux kernel adds 7cb6d92a3f gdb: convert arm to new-style debug macros adds 325d39e4e0 Add Python support for hardware breakpoints adds a72d0f3d69 gdb/doc: reorder and group sections relating to aliases adds 730af66356 gdb/testsuite: improve logging in lib/tuiterm.exp adds 439706e6a9 gdb: use interruptible_select when connecting to a remote adds 1e15fcac94 gdb: convert bfd-cache to new-style debug macros adds d3abc0cee0 gdb: remove unused f77_array_offset_tbl from f-valprint.c adds a59902a7c1 gdb: convert auto-load to new-style debug macros adds d5d24e12f9 Fix build errors for armhf adds cd211c75cb Handle additional connection error adds e534c7e8c4 Automatic date update in version.in adds c651f0a614 MAINTAINERS: Update my e-mail address adds cc4bc93e52 gdb/doc: down case contents of @var adds fe461d2f70 gdb/doc: move @menu to the end of the node adds 5b7d941b90 gdb: add owner-related methods to struct type adds 3062502019 gdb: remove TYPE_OBJFILE_OWNED macro adds 344e9841d9 gdb: remove TYPE_OBJFILE macro adds baf2b57f18 gdb: move set remote commands to remote.c adds cda09ec9f9 gdb: move remote_debug to remote.{h,c} adds 02349803fc gdb: change remote_debug to bool adds 2189c31265 gdb: add remote_debug_printf adds d8c4766d31 gdb/doc: don't rely on @menu item within the docs adds e7b430724d gdb: don't print escape characters when a style is disabled adds 9d2d8a16e1 gdb: add new version style adds 0ac85db529 gdb/testsuite: eliminate gdb_suppress_tests mechanism adds 705646c074 Fix expected output of gdb.base/line65535.exp with dwarf-5 adds e753591581 Automatic date update in version.in adds 1af4c9c420 Disable bracketed paste mode in GDB tests adds ef45cb65a7 Use readline's variant of Windows patch adds d3ee35dbf7 Improve gdb_tilde_expand logic. adds dd5ca05f47 gdb: fix regression in copy_type_recursive adds c99d72de18 Automatic date update in version.in adds 9f7f6cb8d2 Remove call to reset from compile_to_object adds 18454c151f DWARF-5: Fix parsing DWARF-5 line number tables adds 3637a558a5 Use std::vector for "registers_used" in compile feature adds b10bae1875 Avoid crash when "compile" expression uses cooked register adds 68fcee4fa7 PR27228, .reloc wrong symbol emitted for undefined local symbol adds 9b351c9bc9 Minor updates to the 'how to make a release' document adds eea133e655 gas: Add a testcase for PR gas/27228 adds 940d0202fd DWARF-5: Ignore empty range in DWARF-5 line number tables adds 123b18bf62 Automatic date update in version.in adds b8df69003d Update linker scripts with the names of new DWARF-5 debug sections. adds 04de9f3e31 gdb/doc: move @menu blocks to the end of their enclosing @node adds 9e42b97628 Add some more DWARF-5 sections adds acd6125f01 Add test case for symbol menu for local enumerators adds 191849105b Specially handle array contexts in Ada expression resolution adds a625a8c9eb Fix fixed-point regression with recent GCC adds f3bdc2dbb9 gdb/docs: add parentheses in Python examples using print adds 9f6c202e57 [gdb/symtab] Handle DW_AT_ranges with DW_FORM_sec_off in par [...] adds 01a01e0ab3 Automatic date update in version.in adds d0021af39c [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 adds 4ca40594f9 [gdb/testsuite] Fix gdb.threads/killed-outside.exp with -m32 adds d56834cbfb arc: Log "pc" value in "arc_skip_prologue" adds e37709f090 Fix thinko in objcopy's memory freeing code. adds ac3571d941 Fix the date for the last entry in gdb/ChangeLog adds d0cc52bdf2 gdb: Add default reggroups for ARC adds 4287950e54 pr27228 testcase adds 9886ff0319 gas byte test adds a45ef9a30b gas testsuite tidy adds 1c9c9b9b55 PR27226, ld.bfd contains huge .rodata section adds c3ffb8f340 Segmentation fault i386-gen adds 4cb1265b3f bfd: add elfcore_write_file_note adds 4ef367bffd Use debug_prefixed_printf_cond in windows-nat.c adds 1f583bc2fc nios2: Don't disable relaxation with --gdwarf-N adds c22788d614 Automatic date update in version.in adds 2eda57ef61 ld: Fix a typo in testsuite/ld-x86-64/bnd-plt-1.d adds 67965ba289 Simplify the code at the end of objcopy's main() function. adds f04ce15e83 ld: depend on libctf adds bb3c2d4d94 Remove extra space after @pxref in gdb.texinfo adds 807f647cac GDB: aarch64: Add ability to displaced step over a BR/BLR in [...] adds 59b59f08f6 Avoid use after free with logging and debug redirect. adds 07b8b9e7c5 Automatic date update in version.in adds 22efa3d307 [gdb/testsuite] Fix ERROR in gdb.dwarf2/dw2-out-of-range-end [...] adds 2f985dd1ac [gdb/testsuite] Fix gdb.ada/out_of_line_in_inlined.exp with [...] adds def97fb945 PR27259, SHF_LINK_ORDER self-link adds 2a7f6487d0 [gdb/breakpoints] Fix longjmp master breakpoint with separat [...] adds 24cf63899b gdb: update comment for execute_command_to_string adds 47918cca26 gdb/testsuite: unset XDG_CONFIG_HOME adds 0318cca493 gold: Skip address size and segment selector for DWARF5 adds a7ad3cb1ff Fix binutils tools so that they can cope with the special /d [...] adds 53e556e5b4 ld: Add a test for PR ld/27259 adds cc3edc5274 Improve windres's handling of pathnames containing special c [...] adds 6ac373717c gdb: rename type::{arch,objfile} -> type::{arch_owner,objfil [...] adds 8ee511afd8 gdb: rename get_type_arch to type::arch adds c47b145e1a [gdb/testsuite] Fix g0 search in gdb.arch/i386-sse-stack-align.exp adds cdeba395cf [gdb/testsuite] Fix gdb.arch/i386-gnu-cfi.exp adds f237f998d1 gdb/tui: remove special handling of locator/status window adds 0f93c3a25b gdb: remove unneeded switch_to_thread from thr_try_catch_cmd adds 986dbd541a Automatic date update in version.in adds c4566785ac PR27271, c6x-uclinux-ld segfaults linking ld-uClibc-1.0.37.so adds 620ec3caae [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 a [...] adds ebde6f2ddc [gdb/breakpoint] Fix stepping past non-stmt line-table entries adds 6efcd6f329 Automatic date update in version.in adds 008a02e36d sim: readd myself as a maintainer adds 481fac96bd sim: common: sort nltvals.def adds f4dd74915b sim: hw: replace fgets with getline adds 88f68ee277 sim: m68hc11: stop making hardware conditional adds 18d4b488f4 sim: profile: fix bucketing with 64-bit targets adds d4e3adda12 sim: watchpoints: change sizeof_pc to sizeof(sim_cia) adds ee64caae5b sim: m68hc11: include stdlib.h for prototypes adds fb8d4e59af sim: m68hc11: tweak printf-style funcs adds b9e016f517 sim: m68hc11: localize a few functions adds 683b8d961e sim: m68hc11: fix printf size warnings adds ca51543cf5 Automatic date update in version.in adds 9a7ba4aa0e sim: common: change gennltvals helper to Python adds 3c811346e9 sim: moxie: cleanup build warnings adds 44b30b7f0e sim: v850: fix handling of SYS_times adds 5f05936d9b sim: v850: cleanup build warnings adds 5bc4f5ca15 sim: cgen-accfp: Fix pointer sign warnings adds ba2f0de216 sim: bpf/or1k: fix CGEN_TRACE_EXTRACT name adds bccec180ce sim: bpf: fix mainloop extract call adds 6451541244 sim: cgen-trace: tweak printf call adds 4ebf566ea5 Automatic date update in version.in adds 7bba67ec7c PR27283 gas for alpha fails to build with gcc 11 adds 49daa38f31 Re: ld: Add a test for PR ld/27259 adds a5f92c6756 ldgram.y low_level_library_NAME_list adds 82a1fd3a49 gdb: unify parts of the Linux and FreeBSD core dumping code adds 40726f16a8 ld script expression parsing adds fb6c220ebd ld --defsym adds 72a51a0603 Small updates to the 'how to make a release' document follow [...] adds 34c10233cd Wrong operand for SADDR (rl78) adds c39c86378f [gdb/testsuite] Fix gdb.dwarf2/fission-reread.exp with .gdb_index adds 1f568f9a0d Add Genode target support adds 82e3e87da4 Automatic date update in version.in adds 2bd3e4b8d2 [gdb/symtab] Fix assert in write_one_signatured_type adds 9918bff7cf PR27311, ld.bfd (symbol from plugin): undefined reference adds 5424d7ed94 readelf: Add 'R' and 'D' to "Key to Flags:" adds a0c1eeba9b gdb/dwarf: change read_loclist_index complaints into errors adds 5e4d9bbc4b gdb/dwarf: fix bound check in read_rnglist_index adds 05787bad36 gdb/dwarf: add missing bound check to read_loclist_index adds 0c800c6ebc gdb/dwarf: remove unnecessary check in read_{rng,loc}list_index adds b1829e1bf2 gdb/dwarf: few fixes for handling DW_FORM_{rng,loc}listx adds a1c4010369 gdb/dwarf: read correct rnglist/loclist header in read_{rng, [...] adds 962effa790 gdb/testsuite: add .debug_rnglists tests adds 6b0933da34 gdb/testsuite: DWARF assembler: add context parameters to _location adds ecfda20dcc gdb/testsuite: add .debug_loclists tests adds 2b0c7f41d1 gdb/dwarf: split dwarf2_cu::ranges_base in two adds e57933dc9c gdb/dwarf: make read_{loc,rng}list_index return sect_offset adds 9307efbe9e gdb/testsuite: add test for .debug_{rng,loc}lists section wi [...] adds e0bd9202fb gdb/testsuite: use proc_with_prefix in gdb.base/scope.exp adds 2e3773ff54 Inferior without argument prints detail of current inferior. adds 0e33957abf Automatic date update in version.in adds 2ab76a181f Fix attaching in non-stop mode (PR gdb/27055) adds 621cc31071 Fix "target extended-remote" + "maint set target-non-stop" + [...] adds 92234eb192 Testcase for attaching in non-stop mode adds b0083dd72f Fix a couple vStopped pending ack bugs adds 7e9cf1fe36 gdbserver: spurious SIGTRAP w/ detach while step-over in progress adds d758e62c0e Factor out after-stop event handling code from stop_all_threads adds 9147506842 prepare_for_detach: don't release scoped_restore at the end adds 8ff531399b prepare_for_detach and ongoing displaced stepping adds e87f0fe823 detach and breakpoint removal adds ac7d717c1e detach with in-line step over in progress adds 408f66864a detach in all-stop with threads running adds a71501e25f Testcase for detaching while stepping over breakpoint adds 6955136728 PR27311 again, ld.bfd (symbol from plugin): undefined reference adds 95b91a043a pr27270 and pr27284, ar segfaults and wrong file mode adds f01fb44c06 Re: PR27311, ld.bfd (symbol from plugin): undefined reference adds 61ecbbae8e IBM Z: Add missing vector formats to .insn docs adds 72d383bb08 gdb: infrun: move stop_soon variable to inner scoped in hand [...] adds e3714e037b Automatic date update in version.in adds 7d409ac001 PR27311, (symbol from plugin): undefined reference, hidden sym adds 24075dcc85 RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. adds 37707bd822 ld: Restore PR ld/15146 tests adds 1a2f1b54a5 x86-64: Provide more info when failed to convert GOTPCREL adds 35a01a0454 libctf, ld: fix symtypetab and var section population under ld -r adds 78f28b89e8 libctf: rip out dead code handling typedefs with no name adds caa170493e libctf: prohibit nameless ints, floats, typedefs and forwards adds 5dacd11ddc libctf: fix uninitialized variable in symbol serialization e [...] adds ee87f50b8d libctf: always name nameless types "", never NULL adds 6b36ddeb1e gdb: make async event handlers clear themselves adds baa8575b29 gdb: make remote target clear its handler in remote_target::wait adds 85d3ad8e0b gdb: make record-btrace clear event handler in wait adds fdbc5215e7 gdb: make record-full clear async handler in wait adds 3eccb1c8bf gdb: Use correct feature in tdesc-regs for ARC adds 6ff267e186 gdb: make target_is_non_stop_p return bool adds a9ab6e2ea0 Automatic date update in version.in adds b9249c461c sim: riscv: new port adds 04b4939b03 gdb: riscv: enable sim integration adds c180f095f3 PR27345, binutils/arsup.c: lstat() not available on all targets adds cb4ff67af3 RISC-V: PR27348, Remove obsolete Xcustom support. adds 5f40035fb8 RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM. adds 554c30abef ld testsuite on x86_64 with --enable-shared adds 887854bae4 Fix typos in comments added in PR 27252 fix adds fc9a13fbdd [gdb/symtab] Fix indentation in create_cus_from_debug_names_list adds d3b54e63f4 [gdb/symtab] Fix duplicate CUs in create_cus_from_debug_names_list adds ae71049661 [gdb/exp] Fix assert when adding ptr to imaginary unit adds a22ec6e8a4 [gdb/testsuite] Add KFAILs for PR symtab/24549 adds e37d88e5e5 Remove Richard Henderson as the Alpha maintainer adds 1b30f42106 Extract symbol-writing function from parsers adds bdfea17ea9 Return unique_ptr from language_defn::get_compile_context adds 0e857c8288 [gdb/breakpoints] Fix segfault for catch syscall -1 adds e77b0004dd [gdb/symtab] Handle DW_TAG_type_unit in process_psymtab_comp_unit adds 7c6944ab9b [gdb/breakpoints] Handle glibc with debuginfo in create_exce [...] adds 0110ec824e gdb: symmisc.c: remove std_{in,out,err} adds 9c9d63b15a gnulib: update to 776af40e0 adds 51a2525281 PR27349, ar breaks symlinks adds 2c6f2aa664 Automatic date update in version.in adds aa09469fc6 sim: drop use of bfd/configure.host adds 7a36eeea26 sim: common: switch AC_CONFIG_HEADERS adds 8e25beb4af sim: igen: drop libiberty linkage adds cd89c53f6d sim: add ChangeLog entries for last commits adds 4c0d76b9c4 sim: watchpoints: use common sim_pc_get adds 7a9bd3b4e2 sim: erc32/m32c/rl78: add sim_memory_map stub for gdb adds c0e5674584 [gdb/testsuite] Fix gdb.tui/tui-layout-asm.exp with -m32 adds cca043e071 Automatic date update in version.in adds de8d420310 asan: unwind-ia64.c: stack buffer overflow adds 83962f8340 Also compare frame_id_is_next in frapy_richcompare adds 5fc2d6aa06 Refresh regs window in display_registers_from adds 3537bc23d9 Don't fill regs window with a negative number of spaces adds 4cf28e918a Don't draw register sub windows outside the visible area adds 38a143aa8c ld: Remove x86 ISA level run-time tests adds d6f2700b48 Automatic date update in version.in adds 5fb9763991 gdb/testsuite: fix implementation of delete line in tuiterm.exp adds cd074e0415 gdb/tui: fix issue with handling the return character adds 0309f9549d sim/rx: define sim_memory_map adds 93a01471f3 sim/rx: fix an issue where we try to modify a const string adds 1c3e93a41f sim/rx: fill in missing 'void' for empty argument lists adds 73d4725f21 sim/rx: mark some functions as static adds 4b42639636 sim/rx: delete an unused function adds b9fe995797 sim/rx: provide a format string for printf adds 783a7b12d3 sim/rx: move some variable declarations to the start of the block adds ae41b4ce9f sim/rx: use PRIx64 in printf format string adds fab2b376e3 sim/rx: add some missing includes adds da9ecd6085 sim/rx: avoid pointer arithmetic on void * pointers adds 6bf99988c6 sim/rx: enable build with warnings adds 2708dbbd58 gdb/python: reformat an error string adds a53a265752 gdb/tui: restore delete of window objects adds 1cf2399651 gdb/tui: don't add windows to global list from tui_layout:wi [...] adds e0c23e11da gdb/python: don't allow the user to delete window title attributes adds 29db1eb339 gdb: return true in TuiWindow.is_valid only if TUI is enabled adds 9b3e4b5d74 gdb: Do not interrupt atomic sequences for ARC adds 4001d90dde [gdb/testsuite] Use DW_FORM_ref_addr in gdb.dwarf2/enqueued- [...] adds 80b652efa2 Fix an illegal memory access when parsing a corrupt assembler file. adds 3d4aae4860 Build gdb.base/gnu-ifunc.exp with lazy binding adds bfd428bc12 opcodes: tic54x: namespace exported variables adds 32d5141c70 Automatic date update in version.in adds 52563b0f1c Add a test for PR 27355 - where corrupt assembler .file dire [...] adds 4a68fcd7f7 Prevent a bad .Psize expression from triggering a memory acc [...] adds a57d17732e Remove arm-symbianelf adds 9b87f84a35 [binutils] Handle DW_UT_skeleton/split_compile in process_de [...] adds 284beb431f Add a sanity check of files include by .incbin. adds 5f128a25f2 [binutils] Handle DW_FORM_ref_sig8 in get_type_abbrev_from_form adds a4f0544b1b Avoid crash in resolve_dynamic_struct adds f73e424f7b Avoid crash from coerce_unspec_val_to_type adds b61f78118a [testsuite] Don't use 'testfile' before 'standard_testfile'. adds 03642b7189 gdb: revert "gdb: unify parts of the Linux and FreeBSD core [...] adds cf2b207529 [gdb/symtab] Fix element type modification in read_array_type adds 238ebeb127 Automatic date update in version.in adds 9bb305b389 Fix typo in stap_parse_argument_conditionally adds 01e8b831f5 Remove debugging code accidentally included with the fix for [...] adds ee4c3d8801 [gdb/testsuite] Fix tcl ERROR in gdb_load_no_complaints adds 52ff20fe7b [binutils] Handle presence of both .debug_ranges and .debug_ [...] adds ebbc3a7d56 gdb: Delete SYMBOL_OBJ_SECTION and MSYMBOL_OBJ_SECTION adds a52d653e91 gdb: delete SYMBOL_SECTION and MSYMBOL_SECTION macros adds 830c5a1ffb intl: Allow building both with old bison and bison >= 3 [PR92008] adds adda0248ed intl: Unbreak intl build with bison 3 when no regeneration i [...] adds 53d4244ec0 intl: always picify adds aee224d643 intl: turn LIBINTL into -L / -l form adds 9514861402 bfd, opcodes, libctf: support --with-included-gettext adds cbd8f5bbcc libctf: require a Tcl capable of try/catch to run tests adds 758f590744 libctf: add missing header in BFD ELF check adds e92c8eb86d gdb/fortran: add parser support for lbound and ubound adds d9d9d8ef8c [binutils] Handle absolute DW_AT_dwo_name adds 933feaf37e Re: Remove arm-symbianelf adds 18b8df43bd gdb: Remove arm-symbianelf support adds 25ad1e83c8 gdb/testsuite: use "set sysroot" in gdb.multi/multi-target.exp.tcl adds 10ed138aa3 Automatic date update in version.in adds 160fe19337 gdb: adjust comment in gdb.multi/multi-target.exp.tcl adds 6db658c517 PR27291, integer overflow in bfd_get_section_contents adds 1cfcf3004e PR27290, PR27293, PR27295, various avr objdump fixes adds 31c711a2b3 PR27294, avr OOM adds 1db66e348a gdb: add obj_section function to bound_minimal_symbol adds f4be677293 gdb/testsuite: split 'maint info sections' tests to a new file adds 4790db1496 gdb: 'maint info sections' - handle the no executable case adds bf3386f0c1 gdb: change 'maint info section' to use command options adds a1670b7263 gdb/testsuite: remove old comment adds 769c253f45 Revert "ia64: Check UNDEFWEAK_NO_DYNAMIC_RELOC" adds 234b98ced2 Remove ia64 from obsolete list adds b260f8d60c Fix two Fortran regressions adds 05f68f52ef [gdb/symtab] Handle DW_FORM_strx in form_requires_reprocessing adds a5a310d616 Automatic date update in version.in adds d60f79984a [binutils] Print DWO ID adds 95abb3944c [binutils] Fix printing of .debug_str_offsets adds 528a4f87c6 [binutils] Fix typo in comment in dwarf.h adds 3c1d41015b gas testsuite: adjust recently added tests for hppa adds 8f054a7a5a binutils test pr25662: don't use single character labels adds 17e04eff81 binutils testsuite: replace unresolved with unsupported adds 96df3e28b8 gdb/fortran: support ALLOCATED builtin adds c46b706620 Change the readelf and objdump programs so that they will au [...] adds c054dcd552 Minor constification in gdbreplay adds 089436f787 [gdb/threads] Fix lin_thread_get_thread_signals for glibc 2.28 adds 77fba254d9 Add stdio support to gdbreplay adds ceda7cf7f7 Automatic date update in version.in adds adeab0c5b3 config/debuginfod: do not include pkg.m4 directly adds 652f80e07b sim: common: delete unused aclocal.m4 adds 136da8cd9c sim: switch to AC_CONFIG_MACRO_DIRS adds 9ee455572d sim: rx: mitigate fread warning adds b0dcd7d832 sim: testsuite: push $arch out to targets adds f5b2658b0f Automatic date update in version.in adds 5b1f6c9570 ld testsuite: change unresolved to unsupported/fail adds 0d0a0d86c8 Regen for binutils/aclocal.m4 change adds 1944212b42 objdump: don't add an extra entry to syms array adds d7a7af8ff4 Modernise _bfd_elf_mips_get_relocated_section_contents adds a5e6af6d17 Automatic date update in version.in adds 8b78cbec31 alpha_ecoff_get_relocated_section_contents adds 1781a9d0f3 nds32_elf_get_relocated_section_contents adds 208599d928 objdump: don't cache section contents in load_specific_debug [...] adds 8c6740616c bfd: use $(LN_S) in favor of "cp -p" when populating pre-bui [...] adds ba2b480f10 IBM Z: Implement instruction set extensions adds 94ae6062ab Automatic date update in version.in adds 7043388668 demand_copy_C_string NUL check adds 9a12b194b0 PR27426, More bugs in dwarf2dbg.c adds 7b54caddca ubsan: shift exponent is too large adds e6ca18783f Dwarf: fix build with old gcc adds c2f1204d1f x86: make 16-bit ENQCMD test actually test ENQCMD adds b818b220e4 x86: have preprocessor expand macros adds cbe6869656 x86: make common property tests common adds 014d61ea14 x86: record register use for SIMD insns without respective e [...] adds 3d70986f21 x86: honor template rather than actual operands when updatin [...] adds 394ae71f02 x86: CVTPI2PD has special behavior adds ca1289b9f3 gas: Allow SHF_GNU_RETAIN on all sections adds 7d2e5095c6 Correction of gdb.dwarf2/pr13961.S adds 0b5500cdd5 Automatic date update in version.in adds 0d6aab7776 RISC-V: PR27200, allow the first input non-ABI binary to be [...] adds b9b204b311 read_leb128 overflow checking adds 089485ff86 h8300 complains about new section defined without attributes adds 22e6d16f9b [PR cli/17290] gdb/doc: Fix show remote interrupt-*. adds afadac6170 Automatic date update in version.in adds 6a780b6766 Fix completion related libstdc++ assert when using -D_GLIBCXX_DEBUG adds 3d73d29e4e RISC-V: Add bfd/cpu-riscv.h to support all spec versions con [...] adds b0e4d2bd9b gdb: add missing full stops in --help adds a364a116f9 ld: remove stray debug fprintf adds acde209241 gdb/testsuite: only run gdb.arch/i386-biarch-core.exp on sui [...] adds 8568422270 Fix a problem merging empty annobin notes on ppc64le targets. adds 26f53cd385 Introduce expression::evaluate adds 668c18f17f Automatic date update in version.in adds 3685de750e binutils: Avoid renaming over existing files adds 0be51eb4c3 pr26548 test adds 2f973f134d Wrong ELF class plugin vs. gcc ld version adds 5a9f5403c7 RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types [...] adds 8488c357ce amd64-linux-siginfo.c: Adjust include order to avoid gnulib error adds 0257c2ff4f Fix compile time warnings when building riscv assembler. adds ca6afb81ca Automatic date update in version.in adds c3bf9dc5aa Include ld-lib.exp from ctf-lib.exp adds 4d496013a2 Fail run_dump_test when an error is expected but not seen adds 8c3853d9e8 readelf: Replace procesor with processor adds 3e8bb3e934 sim: merge configure.tgt into configure.ac adds f4f60336da libctf, include: find types of symbols by name adds 03c653093d libctf: add a NEWS adds f9eb406771 Automatic date update in version.in adds 93993f6784 libctf AC_CANONICAL_TARGET adds 89753bbf81 Warn when a script redefines a symbol adds 760b3e8bc9 sim: common: split up acinclude.m4 into individual m4 files adds 48ef615826 Automatic date update in version.in adds e9d18e0649 Don't handle BFD_RELOC_16 in XCOFF reloc_type_lookup adds de146e1946 gdb: push target earlier in procfs_target::attach (PR 27435) adds f53fc42716 gdb: add asserts in thread code adds 15908a11ba Change target_bfd_reopen to take a gdb_bfd_ref_ptr adds f16ccf47d8 Automatic date update in version.in adds 897608ed56 gdb: linux-nat: make linux_nat_filter_event return void adds 1a48f0027d gdbserver: linux-low: make linux_process_target::filter_even [...] adds 616c069a3f gdb/dwarf: don't enqueue CU in maybe_queue_comp_unit if alre [...] adds 08ac57714c gdb/dwarf: create and destroy dwarf2_per_bfd's CUs-to-expand queue adds cca8873dd5 PR27456, lstat in rename.c on MinGW adds c42c71a152 Use make_tempname file descriptor in smart_rename adds 55add51eef PR23691, gas .y files vs. automatic make dependencies adds 8139dc77d9 Automatic date update in version.in adds 93af1b046b PR27459, segmentation fault in go32exe_check_format adds c74147bbe0 Remove support for old v1 & v2 style GNU build notes. adds 9d3fcfe068 Fix a potential integer overflow when adding together sectio [...] adds bc3c0632a2 gdb: call value_ind for pointers to dynamic types in UNOP_IN [...] adds 895b7b4e4b gdb/riscv: select rv32 target by default when requested adds 02a7930992 gdb: add a new 'maint info target-sections' command adds 19cf757a87 gdb: spread a little 'const' through the target_section_table code adds b91919ac8b gdb/testsuite: enable gdb.base/sect-cmd.exp test for all targets adds 02f7d26b0b gdb: make the target_sections table private within program_space adds 336aa7b740 gdb: move get_section_table from exec_target to dummy_target adds dd80d75040 gdb: use std::string instead of a fixed size buffer adds 665af52ec2 Fix aarch64-linux-hw-point.c build problem adds 268c77c1b0 Add comment regarding include order of <sys/ptrace.h> and <a [...] adds aa659cfad6 [gdb/symtab] Handle DW_AT_decl_file with form DW_FORM_implic [...] adds 40b02646ec Re: Use make_tempname file descriptor in smart_rename adds 39b0759693 Automatic date update in version.in adds bbaddd4bbe PR27441, inconsistency in weak definitions adds 170f4b23b6 gdb/fortran: add support for legacy .xor. operator adds faeb9f13c1 gdb/fortran: add support for ASSOCIATED builtin adds 68337b8be3 gdb/fortran: don't access non-existent type fields adds 3c27360bc4 ld: correct description of behavior for symbols redefined by script adds 30c80d8833 [gdb/symtab] Fix wrong unit_type Dwarf Error adds 2450ad54ce gdb/mi: Remove extra \n from tsv and and traceframe notifications adds d4ff3cbfdb gdb/testsuite: Add a missing -wrap in gdb_test_multiple adds e38332c286 Add initial support for .debug_sup sections. adds 64d38fdd99 Fix initial thread state of non-threaded remote targets adds dffdd8b51f gdb: relax assertion in target_mourn_inferior adds 0f977b7715 Add comment regarding include order of <sys/ptrace.h> and <a [...] adds 26b43ca6e6 Fix date in ChangeLog adds 06172a2c98 Automatic date update in version.in adds 8255cf421c libctf regen for NEWS adds bfece7562d Add PR27441 testcase adds cb51b708fd testsuite: note on use_gdb_stub usage adds 32e4f96cec Add support for the split DWARF forms. adds f821878623 testsuite: Remove extra \n from expected output of tsv notif [...] adds 0e12f6c802 Add support for decoding DWARF v5 DW_AT_addr_base tags. adds fe0171d248 Correct an error message in the ARM assembler. adds 7fe1b1388f nm: Add --quiet to suppress "no symbols" diagnostic adds 0cf9ea0b16 Automatic date update in version.in adds 573dc0cc43 Minor fix in skip_ctf_tests adds bb3a4efe13 [PR gdb/27393] set directories: handle empty dirs. adds b2287f90e4 Automatic date update in version.in adds f8069d55c1 sim: delete redundant SIM_EXTRA_ALL adds ed30adf750 sim: delete unused SIM_EXTRA_LIBDEPS adds ebe9564b99 sim: require AC_PROG_CPP explicitly adds a3e2cc64a6 sim: use AC_CHECK_TOOL to find ar adds c25ea03dd6 sim: set up build-time compiler settings adds 9ea3e81ca0 sim: igen: delete unused FOR_BUILD vars adds 88d7273afd sim: igen: delete more unused toolchain settings adds 9f34b60a43 sim: igen: drop config.h & header checking adds 1dbde357be Add missing changes to Makefile.tpl adds cf850febf6 Automatic date update in version.in adds 6a1224ec76 PR27128, nm -P portable output format regression adds 7824c1d22f Weak references to __start_/__stop_ symbols adds 8ee10e8609 PR27451, -z start_stop_gc adds ecd65684f5 Warn for missing separate debug files only if needed adds ba6eb62ff0 Add DWARF-5 section names to PE and PEP linker scripts. adds ec11fcffc0 Automatic date update in version.in adds f5b9c288a3 PowerPC64 undefined weak visibility vs GOT optimisation adds b80e421f91 PR27451, -z start_stop_gc for powerpc64 adds eaa2913a7a libctf: ctf_archive_next should set the parent name consistently adds ac36e134d9 libctf: reimplement many _iter iterators in terms of _next adds fd12633780 libctf: fix ChangeLog date adds 8915c559d4 libctf, include: remove the nondeduplicating CTF linker adds 478c04a55e libctf: remove reference to "unconflicted link mode". adds f5060e5633 libctf: add a deduplicator-specific type mapping table adds 4659554b28 libctf: minor error-handling fixes adds cf6a0b989a libctf: fix signed/unsigned comparison confusion adds 8e7e446446 libctf: free ctf_dynsyms properly adds 211bcd0133 bfd, ld, libctf: skip zero-refcount strings in CTF string reporting adds ca8f6bc629 Fix the BFD library's parsing of DIEs where specification at [...] adds 1228719f31 Check objfile->sf in ada-lang.c adds bdcccc5639 Use new for ada_symbol_cache adds 886d459fbe Simplify resolve_subexp by using C++ algorithms adds d1183b064c Return a vector from ada_lookup_symbol_list adds 5f9febe0f6 Use std::string rather than grow_vect adds bbcdf9ab73 Rewrite GNAT-encoded fixed point types in DWARF reader adds b4f26d541a Import GNU Readline 8.1 adds 19a9185537 Fix Readline 8.1 build on mingw adds ca87bad0e9 Automatic date update in version.in adds dc83f2d20e Split relocation defines out of coff/internal.h adds 270f32fc50 ld-gc tests on underscore targets adds 5789f845fb --gc-sections with groups and start/stop syms adds fd5c076a06 PR27493, objcopy --weaken-symbol does not weaken undefined symbols adds b93a3ed0a8 testsuite: extend nopie handling to add -fno-pie to compiler flags adds e71dbd0304 testsuite, gdb.btrace: remove assembly-check in delta.exp adds f0778fc1cf testsuite, gdb.btrace: pass rn-dl-bind.exp with clang adds c7c7253a47 testsuite, gdb.btrace: move -Wl,-x to ldflags adds d2c5f24eed testsuite, gdb.btrace: adjust expected output to pass with clang adds 26ed1478d1 testsuite, gdb.btrace: remove implicit debug option in stepi.exp adds 32c5299909 testsuite, gdb.btrace: adjust expected source line in non-stop.exp adds 8233378104 gdb, testsuite: enforce lazy binding for gdb.btrace/rn-dl-bind.exp adds 75363b6d60 x86: infer operand count of templates adds 1bfa81acbf Minor Ada-related cleanups adds 0b7733b665 binutils fails to compile on AIX due to mismatched declaration adds a2126563ea Automatic date update in version.in adds 168bb18858 GNU strip fails to set sh_link and sh_info on Solaris SPARC64 adds ca0e11aa4b Gate the displaying of non-debug sections in separate debugi [...] adds 1178743e4c Use "bool" in ada-lang.c adds 6fa7408d72 ld: don't generate base relocations in PE output for absolut [...] adds 6b5465b917 bfd: prune COFF/PE section flags setting adds d4e5db4e50 ld: adjust ld-scripts/map-address.* adds d1e93af64a gdb: set current thread in sparc_{fetch,collect}_inferior_re [...] adds 7a39bd53dc Automatic date update in version.in adds b01b5d9a0b Move x86_64 PE changes out of bfd_perform_relocation adds d296b73620 Fix the dislay of .debug_macro.dwo sections. adds 2017f38777 Add support for the DW_FORM_strx* forms to the BFD library. adds f3a5df7bd6 gdb: unify parts of the Linux and FreeBSD core dumping code adds b63a5e38ef bfd/binutils: support for gdb target descriptions in the core file adds 95ce627aeb gdb: write target description into core file adds 0897bb7d6d bfd/riscv: prepare to handle bare metal core dump creation adds fb8f3fc0c3 gdb/riscv: introduce bare metal core dump support adds db6092f3ae bfd/binutils: add support for RISC-V CSRs in core files adds d782d24b32 gdb/riscv: make riscv target description names global adds b2668f28ee gdb/riscv: write CSRs into baremetal core dumps adds 019989fdf1 Automatic date update in version.in adds 844be3f240 CTF: set up debug info for function arguments adds dd99cf0c58 CTF: add all members of an enum type to psymtab adds b0a8c2ff9c Make valgrind tests more robust by adding --wait=1 to vgdb i [...] adds 8c0546e928 elf/x86-64: Subtract __ImageBase for R_AMD64_IMAGEBASE adds 4444f40757 Micro-optimize abbrev reading and storage adds c2a62a3d88 Create new file dwarf2/sect-names.h adds fbedd54644 Change section_is_p to a method on dwarf2_section_names adds a7308ce01e Avoid crash on missing dwz file adds 1803565556 Include scoped_fd.h in debuginfod-support.h adds 9938d15a01 Move dwarf2_get_dwz_file to dwarf2/dwz.h adds 01573d7360 Fix build bug in ada-lang.c adds 7ce45db691 Automatic date update in version.in adds 6bddc3e8b4 sim: switch top level to automake adds 6c57b87fc4 sim: testsuite: merge into toplevel automake adds f4df849f1d Regenerated adds d3dacd0faf Automatic date update in version.in adds 2916e3e18f sim: igen: update options API adds 8c9b6e7689 sim: delete unused BUILD_LIBS setting adds ea2d29f7bc Split out eval_op_scope adds 50b98adc3c Split out eval_op_var_entry_value adds c0df928969 Split out eval_op_var_msym_value adds 9b1d8af683 Split out eval_op_func_static_var adds ffff730bf6 Split out eval_op_register adds 14a1c64a13 Split out eval_op_string adds f871bae1ae Split out eval_op_objc_selector adds 5c2f201e8d Split out eval_op_concat adds f960a6176a Split out eval_op_ternop adds 3e96c4fc0f Split out eval_op_structop_struct adds fb461aa39e Split out eval_op_structop_ptr adds b7a96ed22e Split out eval_op_member adds aedaf9ac06 Split out eval_op_add adds d9790e22f4 Split out eval_op_sub adds 7cdcdd02b3 Split out eval_op_binary adds 288d26bcd8 Split out eval_op_subscript adds 0cc96de858 Split out eval_op_equal adds 1fcb355938 Split out eval_op_notequal adds 6cad134942 Split out eval_op_less adds 1f78d732ec Split out eval_op_gtr adds 96e3efd9b2 Split out eval_op_geq adds 60cdd4871a Split out eval_op_leq adds eed70b1c37 Split out eval_op_repeat adds 39f288bea9 Split out eval_op_plus adds 606d105ff1 Split out eval_op_neg adds 1f09ec811e Split out eval_op_complement adds 24338fb9d9 Split out eval_op_lognot adds 786f70ee4d Split out eval_op_ind adds acee94686b Split out eval_op_alignof adds 3aef2a0768 Split out eval_op_memval adds 00f508843c Split out eval_op_preinc adds 9e1361b760 Split out eval_op_predec adds abffe11606 Split out eval_op_postinc adds a220ead5d4 Split out eval_op_postdec adds aec95807f1 Split out eval_op_type adds cc05c68ee0 Split out eval_op_f_abs adds e08109f24b Split out eval_op_f_mod adds 3dc41f3cdf Split out eval_op_f_ceil adds 9f1a1f3c4f Split out eval_op_f_floor adds 93b2b5fae2 Split out eval_op_f_modulo adds 00f2db6f7d Split out eval_op_f_cmplx adds 216f6fcbef Split out eval_op_f_kind adds 3c18c49c63 Split out fortran_require_array adds 9cbd1c2011 Split out eval_op_f_allocated adds d148f80354 Change parameters to rust_range adds 984af2cb26 Change parameters to rust_subscript adds d123f9e4a3 Split out eval_op_rust_ind adds 6fa9831f89 Split out eval_op_rust_complement adds 051042333d Split out eval_op_rust_array adds 575cae2335 Split out eval_op_rust_struct_anon adds 1fa41fc710 Split out eval_op_rust_structop adds 13ea014aee Split helper functions adds 41bdced5ae Split out eval_op_m2_high adds a49881f73e Split out eval_op_m2_subscript adds fb5ba2ab26 Split out eval_binop_assign_modify adds 5e80600ed0 Split out eval_op_objc_msgcall adds 3634f66996 Split out eval_opencl_assign adds 62d4bd947e Split out eval_ternop_in_range adds 82390ab88c Split out ada_unop_neg adds 7efc87ffcb Split out ada_unop_in_range adds 020dbabe22 Split out ada_atr_tag adds 68c757358f Split out ada_atr_size adds d05e24e61a Split out ada_abs adds faa1dfd751 Split out ada_mult_binop adds 214b13ac3b Split out ada_equal_binop adds 5ce19db80f Split out ada_ternop_slice adds b467efaa91 Split out ada_binop_in_bounds adds b84564fc8c Split out ada_unop_atr adds 38dc70cfee Split out ada_binop_minmax adds 3848abd6e1 Change value_val_atr to ada_val_atr adds dd5fd28346 Split out ada_binop_exp adds c0d7ed8ca8 Split out eval_multi_subscript adds e18c58f290 Split gen_expr_binop_rest adds e2803273a0 Introduce class operation adds de401988ae Implement dumping adds 75f9892d43 Add two agent expression helper functions adds cae26a0cb0 Introduce float_const_operation adds d5ab122c48 Introduce scope_operation adds d336c29e3f Introduce long_const_operation adds 0c8effa32e Introduce var_msym_value_operation adds b5cc3923de Introduce var_entry_value_operation adds 176793957a Introduce func_static_var_operation adds 247d935b83 Introduce last_operation adds 55bdbff857 Introduce register_operation adds e6985c5e45 Introduce bool_operation adds e6e01e16c5 Introduce internalvar_operation adds b50db09ff9 Introduce string_operation adds 1594e0bb3d Introduce ternop_slice_operation adds 9186293fd6 Introduce ternop_cond_operation adds 72d0a71134 Add c-exp.h and c_string_operation adds 06dc61b9df Introduce objc_nsstring_operation adds 09db370026 Introduce objc_selector_operation adds 8cfd3e95b7 Introduce complex_operation adds 808b22cfd7 Introduce structop_operation adds ab0609be83 Introduce structop_ptr_operation adds 07f724a8c6 Introduce structop_member_operation and structop_mptr_operation adds e51e26a090 Introduce concat_operation adds a94323b607 Introduce add_operation adds 5133d78b7b Introduce sub_operation adds 373907ffb2 Introduce binop_operation adds 224d6424ba Introduce subscript_operation adds 46916f2bcb Implement binary comparison operations adds d4eff4c122 Introduce repeat_operation adds ae64ba58b3 Introduce comma_operation adds 9307d17b7a Implement some unary operations adds 6d89e2962a Implement unary increment and decrement operations adds 876469ffa1 Introduce unop_ind_operation adds 5b5f5140e1 Introduce type_operation adds 4efc574cb9 Introduce typeof_operation adds 0af8829eb1 Introduce decltype_operation adds 929f3aa742 Introduce typeid_operation adds 14aff815df Introduce unop_addr_operation adds 85d23bda83 Introduce unop_sizeof_operation adds ae4bb61e19 Introduce unop_alignof_operation adds cbc18219d3 Implement UNOP_MEMVAL and UNOP_MEMVAL_TYPE adds f6b4232691 Introduce op_this_operation adds 44b675c89b Introduce type_instance_operation adds 4078678289 Introduce assign_operation adds e5946e1604 Introduce assign_modify_operation adds 165a813a3a Introduce unop_cast_operation adds 292382f47e Introduce unop_cast_type_operation adds d9ad79d880 Implement C++ cast operations adds e82a5afced Introduce var_value_operation adds 085734dd95 Introduce objc_msgcall_operation adds 821e72d775 Introduce multi_subscript_operation adds 03070ee9c7 Introduce ada_wrapped_operation adds 42fecb6183 Introduce ada_string_operation adds cc6bd32eea Introduce ada_qual_operation adds fc715eb288 Introduce ada_ternop_range_operation adds 9dcd3e2957 Implement several Fortran operations adds 6fab435953 Implement some Rust operations adds 11dd3dce44 Introduce rust_unop_ind_operation adds 6ce1ad679a Introduce rust_subscript_operation adds 9db6b6ddbd Introduce rust_range_operation adds e4407a202d Implement Rust field operations adds 5947d337d6 Introduce rust_aggregate_operation adds 2bc9b40ce1 Add two simple Modula-2 operations adds 5019124b1d Implement the "&&" and "||" operators adds 7c15d377de Implement some Ada unary operations adds 95d49dfbba Introduce ada_unop_range_operation adds e447908052 Introduce class adl_func_operation adds 1c02eb3035 Introduce array_operation adds a00b7254fb Implement function call operations adds 638fd74a61 Implement Rust funcall operation adds 2f98abe174 Introduce fortran_undetermined adds 58a76c7264 Introduce classes for Fortran bound intrinsics adds eb4c927182 Implement Fortran associated operations adds f403a4e4a5 Implement fortran_allocated_operation adds e967770468 Introduce opencl_cast_type_operation adds a88c3c8dd3 Implement OpenCL binary operations adds 2492ba36f6 Introduce opencl_notequal_operation adds 33b7921462 Introduce opencl_structop_operation adds 944fd3b812 Implement OpenCL logical binary operations adds cf12b17fd0 Implement OpenCL ternary conditional operator adds cd9a314824 Split out some Ada type resolution code adds 73796c7326 Introduce ada_binop_addsub_operation adds d9e7db065e Implement Ada multiplicative operators adds 6e8fb7b723 Implement Ada equality operators adds 039e4b76be Introduce ada_bitwise_operation adds 1b1ebfab47 Introduce ada_ternop_slice adds 82c3886e24 Introduce ada_binop_in_bounds adds 60fa02ca6f Implement some Ada OP_ATR_ operations adds 99a3b1e77b Introduce ada_var_value_operation adds 3f4a0053d9 Introduce ada_var_msym_value_operation adds 6ad3b8bf3b Implement Ada min and max operations adds 7992accc6e Refactor value_pos_atr adds 7631cf6cc8 Introduce ada_pos_operation adds 9e99f48f27 Introduce ada_atr_val_operation adds 065ec8268d Introduce ada_binop_exp_operation adds e8c33fa16a Introduce ada_unop_ind_operation adds ebc06ad8f4 Introduce ada_structop_operation adds efe3af2f9a Implement function calls for Ada adds d8a4ed8ad1 Implement Ada resolution adds a88c43542d Implement Ada assignment adds b0f9164cc6 Remove use of op_string adds 413403fc34 Add an expr::operation_up to struct expression adds 4933522da0 Add completion for operations adds 8227d9e2f4 Add operation-related methods to parser_state adds 482ddd69c5 Convert dtrace probes to use operations adds 4c5e7a930a Convert stap probes to create operations adds c1299a2344 Convert rust-exp.y to use operations adds d182f27979 Convert c-exp.y to use operations adds bb4e057488 Convert go-exp.y to use operations adds 9412fdcc2a Convert d-exp.y to use operations adds 3163898ec8 Convert p-exp.y to use operations adds f1b8ceef1b Convert m2-exp.y to use operations adds d308ba78cf Convert f-exp.y to use operations adds 08a057e64b Convert ada-exp.y to use operations adds aa1da9ed50 Remove now-unused Rust evaluator code adds a99be8c199 Remove now-unused Fortran evaluator code adds 5871f0a38d Remove now-unused Modula-2 evaluator code adds d3c54a1ce8 Remove now-unused Ada evaluator code adds f2a98603a8 Remove now-unused C evaluator code adds 1eaebe02cf Remove union exp_element adds 0922dc847e Remove two Ada opcodes adds d357570da8 Remove unused Modula-2 opcodes adds 5d9ba98236 Remove unused Ada opcodes adds 43f542e321 Remove OP_EXTENDED0 adds 48fa6f23ec Remove OP_UNUSED_LAST adds 79ab486e97 Remove BINOP_END adds b9d06571f9 Inline expression constructor adds ce284361a2 Inline expr_builder methods adds 96db551d06 Merge namespace scopes in eval.c adds 0b2b0b8220 Remove EVAL_SKIP adds 40d07d07d0 Change exp_uses_objfile to return bool adds 9c79936b3d Use bound_minimal_symbol in var_msym_value_operation adds 3dd93bf837 Remove some null checks adds 8c379db285 Enable maintainer mode for sim adds 500e7d4cb3 Automatic date update in version.in adds 87fa7d568d bfd: don't silently wrap or truncate PE image section RVAs adds e93a3b27b2 x86-64: make SYSEXIT handling similar to SYSRET's adds 742732c7f0 x86: fold some prefix related attributes into a single one adds e14816a8ba gdb/fortran: add support for RANK keyword adds 7ba155b370 gdb/fortran: add support for 'SIZE' keyword adds eef32f5998 gdb/fotran: add support for the 'shape' keyword adds 611aa09d99 gdb/fortran: Add 'LOC' intrinsic support. adds fbb1aaceba gdb: fix field names of GDB's type main_type structure adds 5dc75cf325 ld: adjust PE base relocations testcase adds ccdc02ed07 Fix function call regression in new evaluator adds 2dfa8341e0 ELF DWARF in PE output adds 3044062c34 Automatic date update in version.in adds 67b0f68480 bfd: strip symbols not representable in COFF/PE symbol table adds 319419837c x86: correct decoding of nop/reserved space (0f18 ... 0x1f) adds 00ec187565 x86: re-arrange order of decode for various legacy opcodes adds 14d10c6ccc x86: re-arrange order of decode for various VEX opcodes adds 13954a3119 x86: re-arrange order of decode for various mask reg opcodes adds fc681dd6a1 x86: re-arrange order of decode for various EVEX opcodes adds 066f82b96a x86: reuse VEX entries for EVEX vperm{q,pd} adds 85ba7507f6 x86: reuse further VEX entries for EVEX adds 32e31ad7da x86: re-arrange enumerator and table entry order adds b763d508db x86/Intel: correct AVX512 S/G disassembly adds 7056f312d0 Use bool for "parse_completion" adds 0b9f3e5463 Automatic date update in version.in adds ebdcad3fdd RISC-V: Improve multiple relax passes problem. adds da944c8a70 x86: remove stray uses of xmmq_mode adds ac7a231133 x86: drop a few redundant EVEX-related checks adds fd1fd06186 x86: re-order logic in OP_XMM() adds 1e1e17e5e2 Automatic date update in version.in adds 68cb21837f PE image base fallout adds 78c84bf926 Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f) adds 8aa2d0236a bfd: add missing smclass when creating csect for xcoff64 adds 6d4d932867 bfd: use default coff_write_object_contents for XCOFF64 adds 0c929e83c1 bfd: move xcoff64_ppc_relocate_section after the HOWTO table adds 2c1bef53de aix: correct HOWTO table and add missing relocations adds 4a403be0c1 aix: implement R_TOCU and R_TOCL relocations adds 1b2cb8e2ee aix: implement TLS relocation for gas and ld adds e3141a4d89 gdb/testsuite: make test names unique in gdb.python/py-mi.exp adds 5fc5a1b882 gdb/testsuite: make test names unique in gdb.python/py-forma [...] adds 22d3e7f629 gdb/testsuite: make test names unique in gdb.python/py-strfns.exp adds f35d6971cd gdb/testsuite: make test names unique in gdb.python/py-finis [...] adds 93598ea43d gdb/testsuite: make test names unique in gdb.python/py-explore.exp adds 8b12ded4e6 gdb/testsuite: make test names unique in gdb.python/py-pp-maint.exp adds 2cb60e747b gdb/testsuite: make test names unique in gdb.python/py-block.exp adds e3e48d8fdb gdb/testsuite: make test names unique in gdb.python/py-prompt.exp adds 79d041578d gdb/testsuite: make test names unique in gdb.python/py-symtab.exp adds 0125fabc7a gdb/testsuite: remove a duplicate test adds 66bb1dd9cd gdb/testsuite: make test names unique in gdb.python/py-explo [...] adds 8a4efb366f gdb/testsuite: check the correct Python variable in test adds 323b848c51 gdb/testsuite: remove duplicate test from gdb.python/py-valu [...] adds 7f99d636c2 gdb/testsuite: resolve remaining duplicate test names in gdb [...] adds 203a206d14 riscv --enable-targets=all on 32-bit host adds 7fce7ea986 aarch64: Add few missing system registers adds be3b926d8d Add values for NetBSD .note.netbsd.ident notes (PaX). adds fece451c2a Use RAII to set the per-thread SIGSEGV handler adds 8673b5d2e0 Automatic date update in version.in adds 367c5eb750 sim: drop dep on configure-gdb adds c6c7769d9d sim: introduce {COMPILE,LINK}_FOR_BUILD adds e7d9022ba8 sim: rename BUILD_LDFLAGS to LDFLAGS_FOR_BUILD adds 27012aba8a Remove Irix 6 workaround from DWARF abbrev reader adds 7c32eebb87 Constify abbrev_table::lookup_abbrev adds 933721ed0c Automatic date update in version.in adds a9f172c6b7 Set dwarf2_per_cu_data::m_header_read_in adds 0280fdcc08 Minor tweak to use die_reader_specs::abfd adds 7c290a04a2 Use cu_header consistently in read_attribute_value adds e838b3ca21 Automatic date update in version.in adds ba6a0ef349 gdb: use make_scoped_restore to restore gdbpy_current_objfile adds c68b1842bd ld: don't chance overrunning PE .reloc section content adds 8d624a9d80 gdb/fortran: Fix quad floating-point type for Intel compilers. adds 1996d0f12c Add a symbols-only mode to nm. adds 207582c075 Fix bug in Ada aggregate assignment adds 1ac7452264 Fix Ada assignment resolution adds 9863c3b5fc Fix regression in Ada ptype adds c04da66c26 Implement Ada operator overloading adds 3b5c4de0cf Call ada_ensure_varsize_limit in indirection adds 6813ceb03f Fix unary + in Ada adds eb5dd73748 gdb: remove dw2_get_file_names_reader's info_ptr parameter adds 850ed749b4 gdb: add logging to dwarf2_initialize_objfile adds 4800761a71 gdb: remove spurious colon in create_debug_type_hash_table d [...] adds 675da9a57e Fix GDB build with GCC 4.8.2

No new revisions were added by this update.

Summary of changes: ChangeLog | 23 + Makefile.def | 2 +- Makefile.in | 2 +- Makefile.tpl | 5 + bfd/ChangeLog | 518 + bfd/Makefile.am | 2 +- bfd/Makefile.in | 2 +- bfd/bfd-in2.h | 12 + bfd/bfd.c | 11 + bfd/coff-alpha.c | 26 +- bfd/coff-rs6000.c | 551 +- bfd/coff-stgo32.c | 4 +- bfd/coff-x86_64.c | 67 +- bfd/coff64-rs6000.c | 1161 +- bfd/coffcode.h | 88 +- bfd/cofflink.c | 11 + bfd/coffswap.h | 11 +- bfd/compress.c | 3 +- bfd/config.bfd | 13 +- bfd/configure | 13 +- bfd/configure.ac | 13 +- bfd/cpu-riscv.c | 123 +- bfd/cpu-riscv.h | 81 + bfd/doc/Makefile.am | 44 +- bfd/doc/Makefile.in | 44 +- bfd/dwarf2.c | 243 +- bfd/elf-bfd.h | 13 +- bfd/elf-linker-x86.h | 3 + bfd/elf-strtab.c | 4 +- bfd/elf.c | 95 +- bfd/elf32-arm.c | 1091 +- bfd/elf32-avr.c | 16 +- bfd/elf32-ft32.c | 3 +- bfd/elf32-i386.c | 36 + bfd/elf32-nds32.c | 5 +- bfd/elf32-ppc.c | 55 +- bfd/elf32-rl78.c | 2 +- bfd/elf64-ppc.c | 95 +- bfd/elf64-sparc.c | 20 + bfd/elf64-x86-64.c | 46 +- bfd/elflink.c | 62 +- bfd/elfnn-ia64.c | 20 +- bfd/elfnn-riscv.c | 516 +- bfd/elfxx-mips.c | 114 +- bfd/elfxx-riscv.c | 69 +- bfd/elfxx-riscv.h | 20 +- bfd/elfxx-x86.c | 50 +- bfd/elfxx-x86.h | 4 + bfd/libbfd-in.h | 2 + bfd/libbfd.c | 23 +- bfd/libbfd.h | 14 + bfd/libxcoff.h | 3 +- bfd/linker.c | 1 + bfd/pe-x86_64.c | 32 +- bfd/peXXigen.c | 12 +- bfd/po/SRC-POTFILES.in | 1 + bfd/reloc.c | 50 +- bfd/rs6000-core.c | 2 +- bfd/section.c | 6 +- bfd/targets.c | 4 - bfd/version.h | 2 +- bfd/wasm-module.c | 27 +- bfd/xcofflink.c | 18 + binutils/ChangeLog | 483 + binutils/MAINTAINERS | 9 +- binutils/Makefile.in | 3 +- binutils/NEWS | 44 + binutils/README-how-to-make-a-release | 64 +- binutils/aclocal.m4 | 1 + binutils/ar.c | 25 +- binutils/arsup.c | 48 +- binutils/bucomm.c | 15 + binutils/bucomm.h | 3 +- binutils/config.in | 3 + binutils/configure | 29 +- binutils/configure.ac | 14 + binutils/doc/Makefile.in | 3 +- binutils/doc/binutils.texi | 105 +- binutils/doc/debug.options.texi | 21 +- binutils/dwarf.c | 451 +- binutils/dwarf.h | 5 +- binutils/elfedit.c | 14 + binutils/nm.c | 144 +- binutils/objcopy.c | 130 +- binutils/objdump.c | 126 +- binutils/od-elf32_avr.c | 127 +- binutils/od-xcoff.c | 3 +- binutils/readelf.c | 442 +- binutils/rename.c | 215 +- binutils/testsuite/binutils-all/ar.exp | 22 +- binutils/testsuite/binutils-all/compress.exp | 39 +- binutils/testsuite/binutils-all/objcopy.exp | 22 +- binutils/testsuite/binutils-all/objdump.WK2 | 2 +- binutils/testsuite/binutils-all/objdump.WK3 | 2 - binutils/testsuite/binutils-all/objdump.exp | 10 +- binutils/testsuite/binutils-all/pr25662.s | 4 +- binutils/testsuite/binutils-all/pr26548.d | 13 + binutils/testsuite/binutils-all/pr26548.s | 40 + binutils/testsuite/binutils-all/pr26548e.d | 11 + binutils/testsuite/binutils-all/readelf.exp | 90 +- binutils/testsuite/binutils-all/readelf.wKis | 2 - binutils/testsuite/binutils-all/retain1a.d | 2 + binutils/testsuite/lib/binutils-common.exp | 687 +- binutils/unwind-ia64.c | 4 + binutils/windres.c | 31 +- config/ChangeLog | 5 +- config/debuginfod.m4 | 2 - configure | 3 - configure.ac | 3 - gas/ChangeLog | 487 + gas/Makefile.am | 151 +- gas/Makefile.in | 148 +- gas/NEWS | 2 + gas/config/bfin-lex-wrapper.c | 2 +- gas/config/bfin-lex.l | 2 +- gas/config/obj-elf.c | 22 +- gas/config/tc-alpha.c | 2 +- gas/config/tc-arm.c | 8 +- gas/config/tc-i386.c | 46 +- gas/config/tc-nios2.c | 4 - gas/config/tc-ppc.c | 384 +- gas/config/tc-ppc.h | 17 + gas/config/tc-riscv.c | 809 +- gas/config/tc-riscv.h | 6 +- gas/config/tc-s390.c | 2 + gas/config/tc-tic54x.c | 28 +- gas/config/te-symbian.h | 22 - gas/configure | 8 +- gas/configure.ac | 8 +- gas/configure.tgt | 5 +- gas/doc/as.texi | 7 - gas/doc/c-riscv.texi | 160 +- gas/doc/c-s390.texi | 57 +- gas/dwarf2dbg.c | 59 +- gas/listing.c | 20 +- gas/po/POTFILES.in | 2 +- gas/read.c | 16 +- gas/testsuite/gas/aarch64/illegal-sysreg-7.d | 2 + gas/testsuite/gas/aarch64/illegal-sysreg-7.l | 2 + gas/testsuite/gas/aarch64/illegal-sysreg-7.s | 2 + gas/testsuite/gas/aarch64/sysreg-7.d | 25 + gas/testsuite/gas/aarch64/sysreg-7.s | 20 + gas/testsuite/gas/all/byte.d | 4 - gas/testsuite/gas/all/byte.l | 3 - gas/testsuite/gas/all/byte.s | 2 - gas/testsuite/gas/all/gas.exp | 7 +- gas/testsuite/gas/all/local-label-overflow.d | 5 +- gas/testsuite/gas/all/none.d | 2 +- gas/testsuite/gas/all/pr27381.d | 4 + gas/testsuite/gas/all/pr27381.err | 2 + gas/testsuite/gas/all/pr27381.s | 1 + gas/testsuite/gas/all/pr27384.d | 4 + gas/testsuite/gas/all/pr27384.err | 4 + gas/testsuite/gas/all/pr27384.s | 4 + gas/testsuite/gas/all/sleb128-2.d | 2 +- gas/testsuite/gas/all/sleb128-4.d | 3 +- gas/testsuite/gas/all/sleb128-5.d | 2 +- gas/testsuite/gas/all/sleb128-7.d | 2 +- gas/testsuite/gas/all/sleb128-9.d | 2 +- gas/testsuite/gas/all/string.d | 2 +- gas/testsuite/gas/arm/arch4t-eabi.d | 2 +- gas/testsuite/gas/arm/arch4t.d | 2 +- gas/testsuite/gas/arm/got_prel.d | 2 +- gas/testsuite/gas/arm/mapdir.d | 2 +- gas/testsuite/gas/arm/mapmisc.d | 2 +- gas/testsuite/gas/arm/mapsecs.d | 2 +- gas/testsuite/gas/arm/mapshort-eabi.d | 2 +- gas/testsuite/gas/arm/pr27411.d | 2 + gas/testsuite/gas/arm/pr27411.l | 6 + gas/testsuite/gas/arm/pr27411.s | 14 + gas/testsuite/gas/arm/thumb-eabi.d | 2 +- gas/testsuite/gas/arm/thumb.d | 2 +- gas/testsuite/gas/arm/thumbrel.d | 2 +- gas/testsuite/gas/elf/bignums.d | 2 +- gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/elf/dwarf2-20.d | 4 - gas/testsuite/gas/elf/elf.exp | 9 +- gas/testsuite/gas/elf/group0c.d | 2 +- gas/testsuite/gas/elf/group1a.d | 2 +- gas/testsuite/gas/elf/missing-build-notes.d | 2 +- gas/testsuite/gas/elf/pr27228.d | 10 + gas/testsuite/gas/elf/pr27228.s | 5 + gas/testsuite/gas/elf/pr27355.d | 3 + gas/testsuite/gas/elf/pr27355.err | 5 + gas/testsuite/gas/elf/pr27355.s | 4 + gas/testsuite/gas/elf/section-symbol-redef.d | 2 +- gas/testsuite/gas/elf/section0.d | 2 +- gas/testsuite/gas/elf/section1.d | 2 +- gas/testsuite/gas/elf/section10.d | 2 +- gas/testsuite/gas/elf/section11.d | 4 +- gas/testsuite/gas/elf/section15.d | 2 +- gas/testsuite/gas/elf/section28.d | 16 + gas/testsuite/gas/elf/section28.s | 11 + gas/testsuite/gas/elf/section29.d | 11 + gas/testsuite/gas/elf/section29.s | 4 + gas/testsuite/gas/elf/section4.d | 2 +- gas/testsuite/gas/elf/section6.d | 2 +- gas/testsuite/gas/elf/section7.d | 2 +- gas/testsuite/gas/elf/symtab.d | 4 +- gas/testsuite/gas/elf/symtab.s | 2 +- gas/testsuite/gas/elf/warn-2.s | 7 - gas/testsuite/gas/i386/avx512f-intel.d | 256 +- gas/testsuite/gas/i386/avx512f_vl-intel.d | 384 +- gas/testsuite/gas/i386/avx512pf-intel.d | 256 +- gas/testsuite/gas/i386/enqcmd-16bit.d | 27 +- gas/testsuite/gas/i386/enqcmd-16bit.s | 2 +- gas/testsuite/gas/i386/i386.exp | 35 +- gas/testsuite/gas/i386/nops-8.d | 2327 +++ gas/testsuite/gas/i386/nops-8.s | 19 + gas/testsuite/gas/i386/noreg-intel64.l | 1 + gas/testsuite/gas/i386/noreg64-data16.d | 1 + gas/testsuite/gas/i386/noreg64-data16.e | 4 +- gas/testsuite/gas/i386/noreg64-rex64.d | 1 + gas/testsuite/gas/i386/noreg64.d | 1 + gas/testsuite/gas/i386/noreg64.l | 1 + gas/testsuite/gas/i386/noreg64.s | 1 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/i386/prefetch-intel.d | 8 +- gas/testsuite/gas/i386/prefetch.d | 8 +- gas/testsuite/gas/i386/property-12.d | 2 +- gas/testsuite/gas/i386/property-4.d | 2 +- gas/testsuite/gas/i386/property-5.d | 2 +- gas/testsuite/gas/i386/property-cvtpi2pd.d | 9 + gas/testsuite/gas/i386/property-cvtpi2pd.s | 2 + gas/testsuite/gas/i386/property-cvtpi2ps.d | 9 + gas/testsuite/gas/i386/property-cvtpi2ps.s | 2 + gas/testsuite/gas/i386/property-ldmxcsr.d | 9 + gas/testsuite/gas/i386/property-ldmxcsr.s | 2 + gas/testsuite/gas/i386/property-vldmxcsr.d | 9 + gas/testsuite/gas/i386/property-vldmxcsr.s | 2 + gas/testsuite/gas/i386/property-vzeroall.d | 9 + gas/testsuite/gas/i386/property-vzeroall.s | 2 + gas/testsuite/gas/i386/sse-check-error.l | 91 +- gas/testsuite/gas/i386/sse-check-warn.e | 17 +- gas/testsuite/gas/i386/sse-check.d | 2 + gas/testsuite/gas/i386/sse-check.s | 4 + gas/testsuite/gas/i386/sse2avx.d | 2 + gas/testsuite/gas/i386/sse2avx.s | 2 + gas/testsuite/gas/i386/x86-64-avx512f-intel.d | 260 +- gas/testsuite/gas/i386/x86-64-avx512f_vl-intel.d | 448 +- gas/testsuite/gas/i386/x86-64-avx512pf-intel.d | 256 +- gas/testsuite/gas/i386/x86-64-prefetch-intel.d | 8 +- gas/testsuite/gas/i386/x86-64-prefetch.d | 8 +- gas/testsuite/gas/i386/x86-64-property-10.d | 10 - gas/testsuite/gas/i386/x86-64-property-11.d | 10 - gas/testsuite/gas/i386/x86-64-property-12.d | 10 - gas/testsuite/gas/i386/x86-64-property-13.d | 10 - gas/testsuite/gas/i386/x86-64-property-2.d | 10 - gas/testsuite/gas/i386/x86-64-property-3.d | 10 - gas/testsuite/gas/i386/x86-64-property-4.d | 10 - gas/testsuite/gas/i386/x86-64-property-5.d | 10 - gas/testsuite/gas/i386/x86-64-property-6.d | 10 - gas/testsuite/gas/i386/x86-64-sse-check-error.l | 94 +- gas/testsuite/gas/i386/x86-64-sse2avx.d | 2 + gas/testsuite/gas/i386/x86-64-sse2avx.s | 2 + gas/testsuite/gas/i386/x86-64-sysenter-amd.d | 2 + gas/testsuite/gas/i386/x86-64-sysenter-amd.l | 4 +- gas/testsuite/gas/i386/x86-64-sysenter-amd.s | 6 +- gas/testsuite/gas/i386/x86-64-sysenter-intel.d | 6 +- gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/m68hc11/indexed12.d | 4 - gas/testsuite/gas/mach-o/sections-1.d | 2 +- gas/testsuite/gas/macros/irp.d | 2 +- gas/testsuite/gas/macros/repeat.d | 2 +- gas/testsuite/gas/macros/rept.d | 2 +- gas/testsuite/gas/macros/test2.d | 2 +- gas/testsuite/gas/macros/test3.d | 1 - gas/testsuite/gas/macros/vararg.d | 2 +- gas/testsuite/gas/nios2/relax.d | 25 + gas/testsuite/gas/nios2/relax.s | 5 + gas/testsuite/gas/ppc/power4.d | 1 - gas/testsuite/gas/ppc/test1elf32.d | 1 - gas/testsuite/gas/ppc/test1elf64.d | 1 - gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 - gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 - gas/testsuite/gas/riscv/bitmanip-insns.s | 58 - gas/testsuite/gas/riscv/insn.d | 26 +- gas/testsuite/gas/riscv/insn.s | 24 +- gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gas/testsuite/gas/s390/s390.exp | 1 + gas/testsuite/gas/s390/zarch-arch14.d | 31 + gas/testsuite/gas/s390/zarch-arch14.s | 24 + gas/testsuite/gas/xgate/insns-dwarf2.d | 2 +- gas/write.c | 4 +- gdb/ChangeLog | 3284 ++++ gdb/MAINTAINERS | 5 +- gdb/Makefile.in | 11 +- gdb/NEWS | 23 + gdb/aarch64-linux-tdep.c | 74 +- gdb/aarch64-tdep.c | 73 +- gdb/aclocal.m4 | 1 + gdb/ada-exp.h | 729 + gdb/ada-exp.y | 787 +- gdb/ada-lang.c | 3933 ++--- gdb/ada-lang.h | 57 +- gdb/ada-typeprint.c | 58 +- gdb/ada-valprint.c | 22 +- gdb/alpha-mdebug-tdep.c | 4 +- gdb/alpha-tdep.c | 8 +- gdb/amd64-fbsd-tdep.c | 2 +- gdb/amd64-linux-tdep.c | 43 +- gdb/amd64-obsd-tdep.c | 2 +- gdb/arc-linux-tdep.c | 81 +- gdb/arc-tdep.c | 24 +- gdb/arch/aarch64-insn.h | 9 + gdb/arm-linux-tdep.c | 47 +- gdb/arm-symbian-tdep.c | 132 - gdb/arm-tdep.c | 50 +- gdb/async-event.c | 1 - gdb/async-event.h | 9 + gdb/auto-load.c | 148 +- gdb/auto-load.h | 13 +- gdb/avr-tdep.c | 6 +- gdb/ax-gdb.c | 1144 +- gdb/ax-gdb.h | 1 - gdb/bfd-target.c | 14 +- gdb/bfd-target.h | 9 +- gdb/break-catch-syscall.c | 2 + gdb/breakpoint.c | 313 +- gdb/c-exp.h | 220 + gdb/c-exp.y | 714 +- gdb/c-lang.c | 347 +- gdb/c-lang.h | 27 +- gdb/c-typeprint.c | 2 +- gdb/c-valprint.c | 8 +- gdb/cli/cli-cmds.c | 36 - gdb/cli/cli-interp.c | 8 + gdb/cli/cli-style.c | 17 +- gdb/cli/cli-style.h | 6 +- gdb/coff-pe-read.c | 2 +- gdb/coffread.c | 8 +- gdb/compile/compile-c-support.c | 16 +- gdb/compile/compile-c-symbols.c | 13 +- gdb/compile/compile-c-types.c | 12 +- gdb/compile/compile-c.h | 2 +- gdb/compile/compile-cplus-types.c | 6 +- gdb/compile/compile-internal.h | 3 +- gdb/compile/compile-loc2c.c | 30 +- gdb/compile/compile.c | 16 +- gdb/compile/compile.h | 4 +- gdb/configure | 3 +- gdb/configure.ac | 3 +- gdb/configure.tgt | 9 +- gdb/copyright.py | 2 +- gdb/corelow.c | 24 + gdb/cp-support.c | 9 +- gdb/cp-valprint.c | 2 +- gdb/cris-tdep.c | 11 +- gdb/csky-tdep.c | 4 +- gdb/ctfread.c | 173 +- gdb/d-exp.y | 307 +- gdb/d-lang.c | 48 - gdb/debuginfod-support.h | 2 + gdb/doc/ChangeLog | 80 + gdb/doc/gdb.texinfo | 547 +- gdb/doc/python.texi | 27 +- gdb/dtrace-probe.c | 18 +- gdb/dwarf2/abbrev.c | 97 +- gdb/dwarf2/abbrev.h | 44 +- gdb/dwarf2/attribute.c | 16 +- gdb/dwarf2/attribute.h | 28 +- gdb/dwarf2/die.h | 36 +- gdb/dwarf2/dwz.c | 242 + gdb/dwarf2/dwz.h | 11 + gdb/dwarf2/index-write.c | 8 + gdb/dwarf2/loc.c | 12 +- gdb/dwarf2/loc.h | 2 +- gdb/dwarf2/macro.c | 6 +- gdb/dwarf2/read.c | 1142 +- gdb/dwarf2/read.h | 8 +- gdb/dwarf2/sect-names.h | 78 + gdb/elf-none-tdep.c | 126 + gdb/elf-none-tdep.h | 30 + gdb/eval.c | 4037 +++-- gdb/event-top.c | 23 +- gdb/event-top.h | 19 +- gdb/exec.c | 62 +- gdb/exec.h | 2 +- gdb/expop.h | 2171 +++ gdb/expprint.c | 1171 +- gdb/expression.h | 193 +- gdb/f-array-walker.h | 4 +- gdb/f-exp.h | 278 + gdb/f-exp.y | 489 +- gdb/f-lang.c | 1348 +- gdb/f-lang.h | 19 - gdb/f-typeprint.c | 7 +- gdb/f-valprint.c | 7 +- gdb/fbsd-tdep.c | 137 +- gdb/findvar.c | 22 +- gdb/frame.c | 20 +- gdb/frame.h | 16 +- gdb/frv-tdep.c | 2 +- gdb/gcore-elf.c | 166 + gdb/gcore-elf.h | 47 + gdb/gcore.c | 21 + gdb/gcore.h | 9 + gdb/gdb-gdb.py.in | 6 +- gdb/gdb_bfd.c | 70 +- gdb/gdbarch.c | 10 +- gdb/gdbarch.h | 8 +- gdb/gdbarch.sh | 4 +- gdb/gdbcmd.h | 9 +- gdb/gdbtypes.c | 144 +- gdb/gdbtypes.h | 85 +- gdb/gnu-v2-abi.c | 2 +- gdb/gnu-v3-abi.c | 22 +- gdb/go-exp.y | 239 +- gdb/go-lang.c | 46 - gdb/go-lang.h | 16 - gdb/go-valprint.c | 2 +- gdb/guile/scm-pretty-print.c | 2 +- gdb/guile/scm-type.c | 4 +- gdb/guile/scm-value.c | 2 +- gdb/hppa-tdep.c | 26 +- gdb/i386-fbsd-tdep.c | 16 +- gdb/i386-gnu-tdep.c | 2 +- gdb/i386-linux-tdep.c | 10 +- gdb/i386-netbsd-tdep.c | 2 +- gdb/i386-obsd-tdep.c | 2 +- gdb/i386-tdep.c | 231 +- gdb/i386-tdep.h | 5 +- gdb/i387-tdep.c | 6 +- gdb/ia64-tdep.c | 6 +- gdb/inf-ptrace.c | 16 - gdb/infcall.c | 2 +- gdb/infcmd.c | 15 +- gdb/inferior.c | 58 +- gdb/infrun.c | 803 +- gdb/infrun.h | 4 + gdb/language.c | 35 +- gdb/language.h | 40 +- gdb/linespec.c | 2 +- gdb/linux-nat.c | 57 +- gdb/linux-nat.h | 7 +- gdb/linux-tdep.c | 154 +- gdb/linux-thread-db.c | 32 +- gdb/lm32-tdep.c | 4 +- gdb/m2-exp.h | 84 + gdb/m2-exp.y | 260 +- gdb/m2-lang.c | 188 +- gdb/m2-lang.h | 18 - gdb/m2-valprint.c | 4 +- gdb/m32r-linux-tdep.c | 10 +- gdb/m32r-tdep.c | 4 +- gdb/m68hc11-tdep.c | 4 +- gdb/m68k-linux-tdep.c | 2 +- gdb/m68k-tdep.c | 6 +- gdb/main.c | 20 +- gdb/maint-test-options.c | 2 +- gdb/maint.c | 371 +- gdb/mep-tdep.c | 2 +- gdb/mi/mi-cmds.c | 5 +- gdb/mi/mi-interp.c | 8 +- gdb/minsyms.c | 19 +- gdb/minsyms.h | 7 + gdb/mips-tdep.c | 40 +- gdb/nat/aarch64-linux-hw-point.c | 9 +- gdb/nat/aarch64-sve-linux-ptrace.h | 6 + gdb/nat/amd64-linux-siginfo.c | 15 +- gdb/nat/linux-osdata.c | 2 +- gdb/nat/windows-nat.c | 24 +- gdb/objc-lang.c | 53 +- gdb/objfiles.c | 4 +- gdb/opencl-lang.c | 415 +- gdb/osabi.c | 1 - gdb/osabi.h | 1 - gdb/p-exp.y | 324 +- gdb/p-lang.c | 34 - gdb/p-lang.h | 9 - gdb/p-valprint.c | 2 +- gdb/parse.c | 919 +- gdb/parser-defs.h | 256 +- gdb/ppc-fbsd-tdep.c | 4 +- gdb/ppc-linux-nat.c | 13 +- gdb/ppc-linux-tdep.c | 24 +- gdb/ppc-netbsd-tdep.c | 2 +- gdb/ppc-obsd-tdep.c | 4 +- gdb/ppc64-tdep.c | 2 +- gdb/printcmd.c | 48 +- gdb/procfs.c | 14 +- gdb/progspace.c | 2 +- gdb/progspace.h | 21 +- gdb/psympriv.h | 7 +- gdb/psymtab.c | 2 +- gdb/python/py-breakpoint.c | 8 +- gdb/python/py-frame.c | 7 +- gdb/python/py-param.c | 7 +- gdb/python/py-prettyprint.c | 2 +- gdb/python/py-record-btrace.c | 2 +- gdb/python/py-record.c | 2 +- gdb/python/py-tui.c | 35 +- gdb/python/py-type.c | 10 +- gdb/python/python.c | 12 +- gdb/record-btrace.c | 5 +- gdb/record-full.c | 2 + gdb/record.c | 2 +- gdb/regcache.c | 2 +- gdb/registry.h | 2 +- gdb/remote-notif.c | 4 +- gdb/remote-sim.c | 1 + gdb/remote.c | 428 +- gdb/remote.h | 20 + gdb/riscv-fbsd-tdep.c | 20 +- gdb/riscv-linux-tdep.c | 4 +- gdb/riscv-none-tdep.c | 173 + gdb/riscv-tdep.c | 125 +- gdb/riscv-tdep.h | 26 + gdb/rs6000-tdep.c | 18 +- gdb/rust-exp.h | 235 + gdb/rust-exp.y | 326 +- gdb/rust-lang.c | 810 +- gdb/rust-lang.h | 15 - gdb/s390-tdep.c | 18 +- gdb/score-tdep.c | 18 +- gdb/ser-tcp.c | 2 +- gdb/solib-dsbt.c | 3 +- gdb/solib-svr4.c | 8 +- gdb/source.c | 2 + gdb/sparc-nat.c | 19 +- gdb/sparc-nat.h | 10 +- gdb/sparc-netbsd-tdep.c | 2 +- gdb/sparc-obsd-tdep.c | 7 + gdb/sparc-sol2-tdep.c | 2 +- gdb/sparc-tdep.c | 6 + gdb/sparc64-linux-nat.c | 4 +- gdb/sparc64-netbsd-tdep.c | 2 +- gdb/sparc64-obsd-tdep.c | 7 + gdb/sparc64-sol2-tdep.c | 2 +- gdb/stabsread.c | 2 +- gdb/stap-probe.c | 220 +- gdb/std-operator.def | 71 +- gdb/symfile.h | 46 +- gdb/symmisc.c | 20 +- gdb/symtab.c | 32 +- gdb/symtab.h | 38 +- gdb/target-debug.h | 2 +- gdb/target-delegates.c | 16 +- gdb/target.c | 39 +- gdb/target.h | 40 +- gdb/testsuite/ChangeLog | 691 + gdb/testsuite/README | 5 + gdb/testsuite/gdb.ada/assign_arr.exp | 7 + gdb/testsuite/gdb.ada/assign_arr/main_p324_051.adb | 2 + .../gdb.ada/assign_arr/target_wrapper.adb | 28 + .../gdb.ada/assign_arr/target_wrapper.ads | 8 + gdb/testsuite/gdb.ada/catch_ex_std.exp | 3 +- gdb/testsuite/gdb.ada/enums_overload.exp | 37 + .../gdb.ada/enums_overload/enums_overload.adb | 38 + .../gdb.ada/enums_overload/enums_overload.ads | 24 + .../gdb.ada/enums_overload/enums_overload_main.adb | 20 + gdb/testsuite/gdb.ada/fixed_points.exp | 85 +- .../gdb.ada/fixed_points/fixed_points.adb | 3 + gdb/testsuite/gdb.ada/fixed_points/pck.ads | 4 + gdb/testsuite/gdb.ada/local-enum.exp | 88 + gdb/testsuite/gdb.ada/local-enum/local.adb | 28 + gdb/testsuite/gdb.ada/operator_call.exp | 115 + gdb/testsuite/gdb.ada/operator_call/opcall.adb | 25 + gdb/testsuite/gdb.ada/operator_call/twovecs.adb | 133 + gdb/testsuite/gdb.ada/operator_call/twovecs.ads | 55 + gdb/testsuite/gdb.ada/out_of_line_in_inlined.exp | 3 +- gdb/testsuite/gdb.ada/varsize_limit.exp | 2 +- gdb/testsuite/gdb.ada/varsize_limit/vsizelim.adb | 14 + gdb/testsuite/gdb.arch/amd64-stap-expressions.S | 43 + gdb/testsuite/gdb.arch/amd64-stap-expressions.exp | 68 + gdb/testsuite/gdb.arch/i386-biarch-core.exp | 5 + gdb/testsuite/gdb.arch/i386-gnu-cfi.exp | 26 +- gdb/testsuite/gdb.arch/i386-mpx.c | 2 +- gdb/testsuite/gdb.arch/i386-sse-stack-align.S | 40 +- gdb/testsuite/gdb.arch/i386-sse-stack-align.c | 13 +- gdb/testsuite/gdb.arch/i386-sse-stack-align.exp | 2 +- gdb/testsuite/gdb.arch/insn-reloc.c | 81 + gdb/testsuite/gdb.arch/riscv-default-tdesc.exp | 59 + gdb/testsuite/gdb.base/bitfields.exp | 137 +- gdb/testsuite/gdb.base/bitfields2.exp | 81 +- gdb/testsuite/gdb.base/break.exp | 23 +- gdb/testsuite/gdb.base/call-sc.exp | 2 +- gdb/testsuite/gdb.base/callfuncs.exp | 2 +- gdb/testsuite/gdb.base/cast-call.c | 37 + gdb/testsuite/gdb.base/cast-call.exp | 38 + gdb/testsuite/gdb.base/catch-syscall.exp | 3 + gdb/testsuite/gdb.base/complex-parts.exp | 11 + gdb/testsuite/gdb.base/ctf-ptype.exp | 19 +- gdb/testsuite/gdb.base/debug-expr.exp | 4 +- gdb/testsuite/gdb.base/dfp-test.exp | 48 +- gdb/testsuite/gdb.base/dup-sect.exp | 1 - gdb/testsuite/gdb.base/endian.exp | 36 +- gdb/testsuite/gdb.base/ending-run.exp | 4 - gdb/testsuite/gdb.base/exprs.exp | 9 +- gdb/testsuite/gdb.base/funcargs.exp | 156 +- gdb/testsuite/gdb.base/gnu-ifunc.exp | 4 + gdb/testsuite/gdb.base/hbreak2.exp | 27 +- gdb/testsuite/gdb.base/inferior-noarg.c | 22 + gdb/testsuite/gdb.base/inferior-noarg.exp | 36 + gdb/testsuite/gdb.base/line65535.exp | 2 +- gdb/testsuite/gdb.base/long_long.exp | 3 +- gdb/testsuite/gdb.base/maint-info-sections.exp | 248 + gdb/testsuite/gdb.base/maint.exp | 87 - gdb/testsuite/gdb.base/recurse.exp | 37 +- gdb/testsuite/gdb.base/scope.exp | 294 +- gdb/testsuite/gdb.base/sect-cmd.exp | 146 +- gdb/testsuite/gdb.base/sepdebug.exp | 23 +- gdb/testsuite/gdb.base/skip.exp | 60 +- gdb/testsuite/gdb.base/solib-weak.exp | 3 +- gdb/testsuite/gdb.base/source-dir.exp | 41 + gdb/testsuite/gdb.base/step-over-syscall.exp | 23 + gdb/testsuite/gdb.base/structs.exp | 2 +- gdb/testsuite/gdb.base/style.exp | 437 +- gdb/testsuite/gdb.base/ui-redirect.exp | 8 + gdb/testsuite/gdb.base/until.exp | 10 +- gdb/testsuite/gdb.btrace/delta.exp | 9 +- gdb/testsuite/gdb.btrace/exception.cc | 6 +- gdb/testsuite/gdb.btrace/exception.exp | 26 +- gdb/testsuite/gdb.btrace/function_call_history.exp | 20 +- gdb/testsuite/gdb.btrace/non-stop.exp | 4 +- gdb/testsuite/gdb.btrace/rn-dl-bind.exp | 31 +- gdb/testsuite/gdb.btrace/stepi.exp | 2 +- gdb/testsuite/gdb.btrace/unknown_functions.exp | 2 +- gdb/testsuite/gdb.cp/misc.exp | 10 +- gdb/testsuite/gdb.dwarf2/clang-debug-names.exp | 16 + .../gdb.dwarf2/dw2-out-of-range-end-of-seq.exp | 7 +- gdb/testsuite/gdb.dwarf2/dw2-ranges-psym.exp | 5 +- .../gdb.dwarf2/dw2-step-out-of-function-no-stmt.c | 44 + .../dw2-step-out-of-function-no-stmt.exp | 126 + gdb/testsuite/gdb.dwarf2/dwznolink.exp | 60 + gdb/testsuite/gdb.dwarf2/enqueued-cu-base-addr.exp | 2 +- gdb/testsuite/gdb.dwarf2/fission-base.S | 5 +- gdb/testsuite/gdb.dwarf2/fission-base.exp | 14 +- gdb/testsuite/gdb.dwarf2/fission-loclists-pie.S | 4 +- gdb/testsuite/gdb.dwarf2/fission-loclists-pie.exp | 13 +- gdb/testsuite/gdb.dwarf2/fission-loclists.S | 5 +- gdb/testsuite/gdb.dwarf2/fission-loclists.exp | 14 +- gdb/testsuite/gdb.dwarf2/fission-multi-cu.S | 6 +- gdb/testsuite/gdb.dwarf2/fission-multi-cu.exp | 14 +- gdb/testsuite/gdb.dwarf2/fission-reread.S | 7 +- gdb/testsuite/gdb.dwarf2/fission-reread.exp | 36 +- gdb/testsuite/gdb.dwarf2/loclists-multiple-cus.c | 37 + gdb/testsuite/gdb.dwarf2/loclists-multiple-cus.exp | 146 + gdb/testsuite/gdb.dwarf2/loclists-sec-offset.c | 69 + gdb/testsuite/gdb.dwarf2/loclists-sec-offset.exp | 261 + gdb/testsuite/gdb.dwarf2/main-subprogram.exp | 14 +- gdb/testsuite/gdb.dwarf2/pr13961.S | 157 +- gdb/testsuite/gdb.dwarf2/rnglists-multiple-cus.exp | 102 + gdb/testsuite/gdb.dwarf2/rnglists-sec-offset.exp | 143 + gdb/testsuite/gdb.fortran/allocated.exp | 49 + gdb/testsuite/gdb.fortran/allocated.f90 | 49 + gdb/testsuite/gdb.fortran/array-slices.exp | 5 +- gdb/testsuite/gdb.fortran/associated.exp | 87 + gdb/testsuite/gdb.fortran/associated.f90 | 97 + gdb/testsuite/gdb.fortran/call-no-debug-func.f90 | 29 + gdb/testsuite/gdb.fortran/call-no-debug-prog.f90 | 35 + gdb/testsuite/gdb.fortran/call-no-debug.exp | 102 + gdb/testsuite/gdb.fortran/debug-expr.exp | 8 +- gdb/testsuite/gdb.fortran/dot-ops.exp | 8 + gdb/testsuite/gdb.fortran/function-calls.exp | 15 + gdb/testsuite/gdb.fortran/intrinsics.exp | 5 + gdb/testsuite/gdb.fortran/lbound-ubound.F90 | 105 + gdb/testsuite/gdb.fortran/lbound-ubound.exp | 199 + gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 21 +- gdb/testsuite/gdb.fortran/pointer-to-pointer.exp | 29 +- gdb/testsuite/gdb.fortran/rank.exp | 79 + gdb/testsuite/gdb.fortran/rank.f90 | 57 + gdb/testsuite/gdb.fortran/shape.exp | 86 + gdb/testsuite/gdb.fortran/shape.f90 | 77 + gdb/testsuite/gdb.fortran/size.exp | 89 + gdb/testsuite/gdb.fortran/size.f90 | 118 + gdb/testsuite/gdb.gdb/python-helper.exp | 142 + gdb/testsuite/gdb.guile/scm-section-script.exp | 1 - gdb/testsuite/gdb.multi/multi-target.exp.tcl | 8 +- gdb/testsuite/gdb.opt/solib-intra-step.exp | 35 +- gdb/testsuite/gdb.python/lib-types.exp | 2 +- .../gdb.python/py-auto-load-chaining-f1.c | 24 + .../gdb.python/py-auto-load-chaining-f1.o-gdb.py | 37 + .../gdb.python/py-auto-load-chaining-f2.c | 24 + .../gdb.python/py-auto-load-chaining-f2.o-gdb.py | 24 + gdb/testsuite/gdb.python/py-auto-load-chaining.c | 58 + gdb/testsuite/gdb.python/py-auto-load-chaining.exp | 78 + gdb/testsuite/gdb.python/py-bad-printers.exp | 7 +- gdb/testsuite/gdb.python/py-block.exp | 18 +- gdb/testsuite/gdb.python/py-breakpoint.exp | 24 + gdb/testsuite/gdb.python/py-events.exp | 2 +- gdb/testsuite/gdb.python/py-explore-cc.exp | 8 +- gdb/testsuite/gdb.python/py-explore.exp | 58 +- gdb/testsuite/gdb.python/py-finish-breakpoint.exp | 28 +- gdb/testsuite/gdb.python/py-finish-breakpoint2.exp | 6 +- gdb/testsuite/gdb.python/py-format-string.exp | 42 +- gdb/testsuite/gdb.python/py-frame-inline.exp | 2 +- gdb/testsuite/gdb.python/py-frame.exp | 3 +- gdb/testsuite/gdb.python/py-framefilter.exp | 2 +- gdb/testsuite/gdb.python/py-infthread.exp | 3 +- gdb/testsuite/gdb.python/py-lookup-type.exp | 2 - gdb/testsuite/gdb.python/py-mi.exp | 322 +- gdb/testsuite/gdb.python/py-pp-maint.exp | 15 +- gdb/testsuite/gdb.python/py-prompt.exp | 85 +- gdb/testsuite/gdb.python/py-section-script.exp | 1 - gdb/testsuite/gdb.python/py-strfns.exp | 4 +- gdb/testsuite/gdb.python/py-symtab.exp | 6 +- gdb/testsuite/gdb.python/py-value-cc.exp | 2 - gdb/testsuite/gdb.python/python.exp | 2 +- gdb/testsuite/gdb.python/tui-window-disabled.c | 43 + gdb/testsuite/gdb.python/tui-window-disabled.exp | 189 + gdb/testsuite/gdb.python/tui-window-disabled.py | 89 + gdb/testsuite/gdb.python/tui-window.exp | 6 + gdb/testsuite/gdb.python/tui-window.py | 10 +- gdb/testsuite/gdb.server/stop-reply-no-thread.exp | 10 + gdb/testsuite/gdb.threads/attach-non-stop.c | 58 + gdb/testsuite/gdb.threads/attach-non-stop.exp | 148 + gdb/testsuite/gdb.threads/detach-step-over.c | 112 + gdb/testsuite/gdb.threads/detach-step-over.exp | 290 + gdb/testsuite/gdb.threads/killed-outside.exp | 3 + .../gdb.threads/signal-command-handle-nopass.exp | 4 +- .../signal-command-multiple-signals-pending.exp | 4 +- .../gdb.threads/signal-delivered-right-thread.exp | 4 +- gdb/testsuite/gdb.threads/signal-sigtrap.exp | 4 +- gdb/testsuite/gdb.trace/mi-tsv-changed.exp | 10 +- gdb/testsuite/gdb.tui/scroll.exp | 72 + .../gdb.tui/tui-layout-asm-short-prog.exp | 4 +- gdb/testsuite/gdb.tui/tui-layout-asm.exp | 7 +- gdb/testsuite/gdb.tui/winheight.exp | 14 + gdb/testsuite/gdb.xml/tdesc-regs.exp | 3 +- gdb/testsuite/lib/dwarf.exp | 456 +- gdb/testsuite/lib/gdb-utils.exp | 1 + gdb/testsuite/lib/gdb.exp | 231 +- gdb/testsuite/lib/gdbserver-support.exp | 3 + gdb/testsuite/lib/mi-support.exp | 41 +- gdb/testsuite/lib/prompt.exp | 2 - gdb/testsuite/lib/range-stepping-support.exp | 8 +- gdb/testsuite/lib/tuiterm.exp | 573 +- gdb/testsuite/lib/valgrind.exp | 2 +- gdb/thread.c | 11 +- gdb/tilegx-tdep.c | 18 +- gdb/top.c | 21 +- gdb/top.h | 7 +- gdb/tracepoint.c | 64 +- gdb/trad-frame.c | 98 +- gdb/trad-frame.h | 50 +- gdb/tramp-frame.c | 7 +- gdb/tui/tui-data.h | 4 +- gdb/tui/tui-disasm.c | 13 +- gdb/tui/tui-interp.c | 23 +- gdb/tui/tui-io.c | 73 +- gdb/tui/tui-io.h | 5 + gdb/tui/tui-layout.c | 44 +- gdb/tui/tui-layout.h | 16 + gdb/tui/tui-location.c | 81 + gdb/tui/tui-location.h | 93 + gdb/tui/tui-regs.c | 19 +- gdb/tui/tui-source.c | 9 +- gdb/tui/tui-stack.c | 114 +- gdb/tui/tui-stack.h | 19 - gdb/tui/tui-wingeneral.c | 4 - gdb/tui/tui-winsource.c | 3 +- gdb/tui/tui.c | 26 +- gdb/tui/tui.h | 1 + gdb/unittests/command-def-selftests.c | 6 +- gdb/unittests/gdb_tilde_expand-selftests.c | 94 + gdb/unittests/observable-selftests.c | 2 +- gdb/unittests/optional/assignment/1.cc | 2 +- gdb/unittests/optional/assignment/2.cc | 2 +- gdb/unittests/optional/assignment/3.cc | 2 +- gdb/unittests/optional/assignment/4.cc | 2 +- gdb/unittests/optional/assignment/5.cc | 2 +- gdb/unittests/optional/assignment/6.cc | 2 +- gdb/utils.c | 73 +- gdb/v850-tdep.c | 5 +- gdb/valarith.c | 11 +- gdb/valops.c | 18 +- gdb/valprint.c | 12 +- gdb/value.c | 35 +- gdb/value.h | 21 +- gdb/varobj.c | 2 +- gdb/vax-tdep.c | 2 +- gdb/windows-nat.c | 118 +- gdb/xcoffread.c | 9 +- gdbserver/ChangeLog | 55 + gdbserver/Makefile.in | 2 +- gdbserver/ax.cc | 2 +- gdbserver/debug.cc | 2 +- gdbserver/gdbreplay.cc | 60 +- gdbserver/linux-low.cc | 53 +- gdbserver/linux-low.h | 8 +- gdbserver/linux-x86-low.cc | 59 +- gdbserver/remote-utils.cc | 4 + gdbserver/server.cc | 9 + gdbserver/tracepoint.cc | 18 +- gdbsupport/ChangeLog | 20 + gdbsupport/common-debug.cc | 6 +- gdbsupport/common-debug.h | 8 + gdbsupport/common-defs.h | 4 +- gdbsupport/common-utils.h | 6 +- gdbsupport/gdb_tilde_expand.cc | 46 +- gdbsupport/gdb_tilde_expand.h | 3 +- gnulib/ChangeLog | 6 + gnulib/Makefile.in | 108 +- gnulib/aclocal.m4 | 7 +- gnulib/config.in | 180 +- gnulib/configure | 2721 ++-- gnulib/import/Makefile.am | 183 +- gnulib/import/Makefile.in | 312 +- gnulib/import/_Noreturn.h | 2 +- gnulib/import/alloca.c | 286 +- gnulib/import/alloca.in.h | 4 +- gnulib/import/arg-nonnull.h | 4 +- gnulib/import/arpa_inet.in.h | 2 +- gnulib/import/assure.h | 2 +- gnulib/import/at-func.c | 2 +- gnulib/import/attribute.h | 25 +- gnulib/import/basename-lgpl.c | 22 +- gnulib/import/basename-lgpl.h | 78 + gnulib/import/btowc.c | 2 +- gnulib/import/c++defs.h | 26 +- gnulib/import/canonicalize-lgpl.c | 495 +- gnulib/import/cdefs.h | 207 +- gnulib/import/chdir-long.c | 2 +- gnulib/import/chdir-long.h | 2 +- gnulib/import/cloexec.c | 2 +- gnulib/import/cloexec.h | 2 +- gnulib/import/close.c | 10 +- gnulib/import/closedir.c | 2 +- gnulib/import/count-one-bits.h | 5 +- gnulib/import/ctype.in.h | 2 +- gnulib/import/dirent-private.h | 2 +- gnulib/import/dirent.in.h | 4 +- gnulib/import/dirfd.c | 2 +- gnulib/import/dirname-lgpl.c | 2 +- gnulib/import/dirname.h | 9 +- gnulib/import/dup-safer-flag.c | 2 +- gnulib/import/dup-safer.c | 2 +- gnulib/import/dup.c | 10 +- gnulib/import/dup2.c | 104 +- gnulib/import/eloop-threshold.h | 83 + gnulib/import/errno.in.h | 2 +- gnulib/import/error.c | 6 +- gnulib/import/error.h | 27 +- gnulib/import/exitfail.c | 2 +- gnulib/import/exitfail.h | 2 +- gnulib/import/extra/update-copyright | 2 +- gnulib/import/fchdir.c | 2 +- gnulib/import/fcntl.c | 10 +- gnulib/import/fcntl.in.h | 45 +- gnulib/import/fd-hook.c | 2 +- gnulib/import/fd-hook.h | 2 +- gnulib/import/fd-safer-flag.c | 2 +- gnulib/import/fd-safer.c | 2 +- gnulib/import/fdopendir.c | 2 +- gnulib/import/filename.h | 22 +- gnulib/import/filenamecat-lgpl.c | 5 +- gnulib/import/filenamecat.h | 2 +- gnulib/import/flexmember.h | 2 +- gnulib/import/float+.h | 2 +- gnulib/import/float.c | 2 +- gnulib/import/float.in.h | 8 +- gnulib/import/fnmatch.c | 14 +- gnulib/import/fnmatch.in.h | 2 +- gnulib/import/fnmatch_loop.c | 19 +- gnulib/import/fpucw.h | 6 +- gnulib/import/free.c | 47 + gnulib/import/frexp.c | 2 +- gnulib/import/frexpl.c | 2 +- gnulib/import/fstat.c | 2 +- gnulib/import/fstatat.c | 2 +- gnulib/import/getcwd-lgpl.c | 6 +- gnulib/import/getcwd.c | 86 +- gnulib/import/getdtablesize.c | 2 +- gnulib/import/getlogin_r.c | 2 +- gnulib/import/getprogname.c | 42 +- gnulib/import/getprogname.h | 2 +- gnulib/import/getrandom.c | 4 +- gnulib/import/gettext.h | 2 +- gnulib/import/gettimeofday.c | 13 +- gnulib/import/glob-libc.h | 2 +- gnulib/import/glob.c | 14 +- gnulib/import/glob.in.h | 6 +- gnulib/import/glob_internal.h | 2 +- gnulib/import/glob_pattern_p.c | 2 +- gnulib/import/globfree.c | 2 +- gnulib/import/glthread/lock.c | 2 +- gnulib/import/glthread/lock.h | 2 +- gnulib/import/glthread/threadlib.c | 37 +- gnulib/import/hard-locale.c | 2 +- gnulib/import/hard-locale.h | 2 +- gnulib/import/idx.h | 114 + gnulib/import/inet_ntop.c | 2 +- gnulib/import/intprops.h | 72 +- gnulib/import/inttypes.in.h | 464 +- gnulib/import/isblank.c | 2 +- gnulib/import/isnan.c | 2 +- gnulib/import/isnand-nolibm.h | 6 +- gnulib/import/isnand.c | 2 +- gnulib/import/isnanl-nolibm.h | 12 +- gnulib/import/isnanl.c | 2 +- gnulib/import/itold.c | 2 +- gnulib/import/lc-charset-dispatch.c | 2 +- gnulib/import/lc-charset-dispatch.h | 2 +- gnulib/import/libc-config.h | 175 +- gnulib/import/limits.in.h | 2 +- gnulib/import/localcharset.c | 2 +- gnulib/import/localcharset.h | 2 +- gnulib/import/locale.in.h | 2 +- gnulib/import/localtime-buffer.c | 60 - gnulib/import/localtime-buffer.h | 27 - gnulib/import/lstat.c | 2 +- gnulib/import/m4/00gnulib.m4 | 40 +- gnulib/import/m4/__inline.m4 | 2 +- gnulib/import/m4/absolute-header.m4 | 12 +- gnulib/import/m4/alloca.m4 | 38 +- gnulib/import/m4/arpa_inet_h.m4 | 2 +- gnulib/import/m4/btowc.m4 | 19 +- gnulib/import/m4/builtin-expect.m4 | 2 +- gnulib/import/m4/canonicalize.m4 | 20 +- gnulib/import/m4/chdir-long.m4 | 12 +- gnulib/import/m4/clock_time.m4 | 31 + gnulib/import/m4/close.m4 | 2 +- gnulib/import/m4/closedir.m4 | 2 +- gnulib/import/m4/codeset.m4 | 2 +- gnulib/import/m4/ctype.m4 | 2 +- gnulib/import/m4/d-ino.m4 | 2 +- gnulib/import/m4/d-type.m4 | 2 +- gnulib/import/m4/dirent_h.m4 | 2 +- gnulib/import/m4/dirfd.m4 | 2 +- gnulib/import/m4/dirname.m4 | 19 - gnulib/import/m4/double-slash-root.m4 | 2 +- gnulib/import/m4/dup.m4 | 7 +- gnulib/import/m4/dup2.m4 | 184 +- gnulib/import/m4/eealloc.m4 | 2 +- gnulib/import/m4/environ.m4 | 2 +- gnulib/import/m4/errno_h.m4 | 2 +- gnulib/import/m4/error.m4 | 2 +- gnulib/import/m4/exponentd.m4 | 2 +- gnulib/import/m4/exponentl.m4 | 2 +- gnulib/import/m4/extensions.m4 | 174 +- gnulib/import/m4/extern-inline.m4 | 2 +- gnulib/import/m4/fchdir.m4 | 37 +- gnulib/import/m4/fcntl-o.m4 | 5 +- gnulib/import/m4/fcntl.m4 | 55 +- gnulib/import/m4/fcntl_h.m4 | 7 +- gnulib/import/m4/fdopendir.m4 | 22 +- gnulib/import/m4/filenamecat.m4 | 2 +- gnulib/import/m4/flexmember.m4 | 2 +- gnulib/import/m4/float_h.m4 | 2 +- gnulib/import/m4/fnmatch.m4 | 2 +- gnulib/import/m4/fnmatch_h.m4 | 2 +- gnulib/import/m4/fpieee.m4 | 2 +- gnulib/import/m4/free.m4 | 49 + gnulib/import/m4/frexp.m4 | 2 +- gnulib/import/m4/frexpl.m4 | 8 +- gnulib/import/m4/fstat.m4 | 5 +- gnulib/import/m4/fstatat.m4 | 2 +- gnulib/import/m4/getcwd-abort-bug.m4 | 34 +- gnulib/import/m4/getcwd-path-max.m4 | 7 +- gnulib/import/m4/getcwd.m4 | 10 +- gnulib/import/m4/getdtablesize.m4 | 21 +- gnulib/import/m4/getlogin.m4 | 2 +- gnulib/import/m4/getlogin_r.m4 | 6 +- gnulib/import/m4/getpagesize.m4 | 2 +- gnulib/import/m4/getprogname.m4 | 2 +- gnulib/import/m4/getrandom.m4 | 11 +- gnulib/import/m4/gettimeofday.m4 | 63 +- gnulib/import/m4/glob.m4 | 2 +- gnulib/import/m4/glob_h.m4 | 2 +- gnulib/import/m4/gnulib-cache.m4 | 2 +- gnulib/import/m4/gnulib-common.m4 | 182 +- gnulib/import/m4/gnulib-comp.m4 | 49 +- gnulib/import/m4/gnulib-tool.m4 | 2 +- gnulib/import/m4/include_next.m4 | 36 +- gnulib/import/m4/inet_ntop.m4 | 2 +- gnulib/import/m4/inttypes-pri.m4 | 42 - gnulib/import/m4/inttypes.m4 | 20 +- gnulib/import/m4/isblank.m4 | 2 +- gnulib/import/m4/isnand.m4 | 8 +- gnulib/import/m4/isnanl.m4 | 25 +- gnulib/import/m4/largefile.m4 | 10 +- gnulib/import/m4/limits-h.m4 | 2 +- gnulib/import/m4/localcharset.m4 | 2 +- gnulib/import/m4/locale-fr.m4 | 16 +- gnulib/import/m4/locale-ja.m4 | 10 +- gnulib/import/m4/locale-zh.m4 | 10 +- gnulib/import/m4/locale_h.m4 | 2 +- gnulib/import/m4/localtime-buffer.m4 | 21 - gnulib/import/m4/lock.m4 | 2 +- gnulib/import/m4/lstat.m4 | 2 +- gnulib/import/m4/malloc.m4 | 12 +- gnulib/import/m4/malloca.m4 | 2 +- gnulib/import/m4/math_h.m4 | 365 +- gnulib/import/m4/mbrtowc.m4 | 87 +- gnulib/import/m4/mbsinit.m4 | 15 +- gnulib/import/m4/mbsrtowcs.m4 | 22 +- gnulib/import/m4/mbstate_t.m4 | 13 +- gnulib/import/m4/mbtowc.m4 | 2 +- gnulib/import/m4/memchr.m4 | 74 +- gnulib/import/m4/memmem.m4 | 2 +- gnulib/import/m4/mempcpy.m4 | 2 +- gnulib/import/m4/memrchr.m4 | 2 +- gnulib/import/m4/minmax.m4 | 2 +- gnulib/import/m4/mkdir.m4 | 91 +- gnulib/import/m4/mkdtemp.m4 | 2 +- gnulib/import/m4/mkostemp.m4 | 2 +- gnulib/import/m4/mmap-anon.m4 | 6 +- gnulib/import/m4/mode_t.m4 | 2 +- gnulib/import/m4/msvc-inval.m4 | 2 +- gnulib/import/m4/msvc-nothrow.m4 | 2 +- gnulib/import/m4/multiarch.m4 | 69 +- gnulib/import/m4/netinet_in_h.m4 | 2 +- gnulib/import/m4/nocrash.m4 | 2 +- gnulib/import/m4/off_t.m4 | 2 +- gnulib/import/m4/open-cloexec.m4 | 2 +- gnulib/import/m4/open-slash.m4 | 5 +- gnulib/import/m4/open.m4 | 2 +- gnulib/import/m4/openat.m4 | 2 +- gnulib/import/m4/opendir.m4 | 2 +- gnulib/import/m4/pathmax.m4 | 2 +- gnulib/import/m4/pid_t.m4 | 38 + gnulib/import/m4/pipe.m4 | 15 + gnulib/import/m4/pthread_rwlock_rdlock.m4 | 2 +- gnulib/import/m4/rawmemchr.m4 | 2 +- gnulib/import/m4/readdir.m4 | 2 +- gnulib/import/m4/readlink.m4 | 63 +- gnulib/import/m4/realloc.m4 | 12 +- gnulib/import/m4/rename.m4 | 6 +- gnulib/import/m4/rewinddir.m4 | 2 +- gnulib/import/m4/rmdir.m4 | 23 +- gnulib/import/m4/save-cwd.m4 | 2 +- gnulib/import/m4/setenv.m4 | 66 +- gnulib/import/m4/setlocale_null.m4 | 4 +- gnulib/import/m4/signal_h.m4 | 2 +- gnulib/import/m4/socklen.m4 | 2 +- gnulib/import/m4/sockpfaf.m4 | 2 +- gnulib/import/m4/ssize_t.m4 | 2 +- gnulib/import/m4/stat-time.m4 | 2 +- gnulib/import/m4/stat.m4 | 15 +- gnulib/import/m4/std-gnu11.m4 | 11 +- gnulib/import/m4/stdalign.m4 | 2 +- gnulib/import/m4/stdbool.m4 | 2 +- gnulib/import/m4/stddef_h.m4 | 20 +- gnulib/import/m4/stdint.m4 | 30 +- gnulib/import/m4/stdio_h.m4 | 17 +- gnulib/import/m4/stdlib_h.m4 | 44 +- gnulib/import/m4/strchrnul.m4 | 2 +- gnulib/import/m4/strdup.m4 | 12 +- gnulib/import/m4/strerror.m4 | 2 +- gnulib/import/m4/strerror_r.m4 | 2 +- gnulib/import/m4/string_h.m4 | 96 +- gnulib/import/m4/strnlen.m4 | 2 +- gnulib/import/m4/strstr.m4 | 6 +- gnulib/import/m4/strtok_r.m4 | 2 +- gnulib/import/m4/sys_random_h.m4 | 7 +- gnulib/import/m4/sys_socket_h.m4 | 2 +- gnulib/import/m4/sys_stat_h.m4 | 17 +- gnulib/import/m4/sys_time_h.m4 | 2 +- gnulib/import/m4/sys_types_h.m4 | 24 +- gnulib/import/m4/sys_uio_h.m4 | 2 +- gnulib/import/m4/tempname.m4 | 2 +- gnulib/import/m4/threadlib.m4 | 19 +- gnulib/import/m4/time_h.m4 | 25 +- gnulib/import/m4/time_r.m4 | 2 +- gnulib/import/m4/unistd-safer.m4 | 2 +- gnulib/import/m4/unistd_h.m4 | 52 +- gnulib/import/m4/visibility.m4 | 2 +- gnulib/import/m4/warn-on-use.m4 | 16 +- gnulib/import/m4/wchar_h.m4 | 110 +- gnulib/import/m4/wchar_t.m4 | 2 +- gnulib/import/m4/wctype_h.m4 | 47 +- gnulib/import/m4/wint_t.m4 | 39 +- gnulib/import/m4/wmemchr.m4 | 17 +- gnulib/import/m4/wmempcpy.m4 | 2 +- gnulib/import/m4/zzgnulib.m4 | 2 +- gnulib/import/malloc.c | 2 +- gnulib/import/malloc/scratch_buffer.h | 18 +- gnulib/import/malloc/scratch_buffer_dupfree.c | 41 + gnulib/import/malloc/scratch_buffer_grow.c | 2 +- .../import/malloc/scratch_buffer_grow_preserve.c | 2 +- .../import/malloc/scratch_buffer_set_array_size.c | 2 +- gnulib/import/malloca.c | 2 +- gnulib/import/malloca.h | 4 +- gnulib/import/math.in.h | 254 +- gnulib/import/mbrtowc-impl-utf8.h | 2 +- gnulib/import/mbrtowc-impl.h | 2 +- gnulib/import/mbrtowc.c | 2 +- gnulib/import/mbsinit.c | 2 +- gnulib/import/mbsrtowcs-impl.h | 2 +- gnulib/import/mbsrtowcs-state.c | 2 +- gnulib/import/mbsrtowcs.c | 2 +- gnulib/import/mbtowc-impl.h | 2 +- gnulib/import/mbtowc-lock.c | 2 +- gnulib/import/mbtowc-lock.h | 2 +- gnulib/import/mbtowc.c | 2 +- gnulib/import/memchr.c | 2 +- gnulib/import/memchr.valgrind | 2 +- gnulib/import/memmem.c | 2 +- gnulib/import/mempcpy.c | 2 +- gnulib/import/memrchr.c | 2 +- gnulib/import/minmax.h | 2 +- gnulib/import/mkdir.c | 4 +- gnulib/import/mkdtemp.c | 2 +- gnulib/import/mkostemp.c | 2 +- gnulib/import/msvc-inval.c | 2 +- gnulib/import/msvc-inval.h | 2 +- gnulib/import/msvc-nothrow.c | 2 +- gnulib/import/msvc-nothrow.h | 2 +- gnulib/import/netinet_in.in.h | 2 +- gnulib/import/open.c | 6 +- gnulib/import/openat-die.c | 2 +- gnulib/import/openat-priv.h | 2 +- gnulib/import/openat-proc.c | 2 +- gnulib/import/openat.c | 2 +- gnulib/import/openat.h | 2 +- gnulib/import/opendir.c | 2 +- gnulib/import/pathmax.h | 2 +- gnulib/import/pipe-safer.c | 10 +- gnulib/import/pipe.c | 50 + gnulib/import/rawmemchr.c | 2 +- gnulib/import/rawmemchr.valgrind | 2 +- gnulib/import/readdir.c | 2 +- gnulib/import/readlink.c | 50 +- gnulib/import/realloc.c | 2 +- gnulib/import/rename.c | 2 +- gnulib/import/rewinddir.c | 2 +- gnulib/import/rmdir.c | 5 +- gnulib/import/same-inode.h | 2 +- gnulib/import/save-cwd.c | 2 +- gnulib/import/save-cwd.h | 2 +- gnulib/import/scratch_buffer.h | 18 + gnulib/import/setenv.c | 4 +- gnulib/import/setlocale-lock.c | 2 +- gnulib/import/setlocale_null.c | 2 +- gnulib/import/setlocale_null.h | 2 +- gnulib/import/signal.in.h | 8 +- gnulib/import/stat-time.h | 2 +- gnulib/import/stat-w32.c | 31 +- gnulib/import/stat-w32.h | 2 +- gnulib/import/stat.c | 2 +- gnulib/import/stdalign.in.h | 25 +- gnulib/import/stdbool.in.h | 2 +- gnulib/import/stddef.in.h | 21 +- gnulib/import/stdint.in.h | 12 +- gnulib/import/stdio.in.h | 217 +- gnulib/import/stdlib.in.h | 188 +- gnulib/import/str-two-way.h | 2 +- gnulib/import/strchrnul.c | 2 +- gnulib/import/strchrnul.valgrind | 2 +- gnulib/import/strdup.c | 2 +- gnulib/import/streq.h | 4 +- gnulib/import/strerror-override.c | 2 +- gnulib/import/strerror-override.h | 2 +- gnulib/import/strerror.c | 2 +- gnulib/import/strerror_r.c | 3 +- gnulib/import/string.in.h | 138 +- gnulib/import/stripslash.c | 2 +- gnulib/import/strnlen.c | 2 +- gnulib/import/strnlen1.c | 2 +- gnulib/import/strnlen1.h | 2 +- gnulib/import/strstr.c | 2 +- gnulib/import/strtok_r.c | 2 +- gnulib/import/sys_random.in.h | 6 +- gnulib/import/sys_socket.in.h | 4 +- gnulib/import/sys_stat.in.h | 140 +- gnulib/import/sys_time.in.h | 4 +- gnulib/import/sys_types.in.h | 2 +- gnulib/import/sys_uio.in.h | 2 +- gnulib/import/tempname.c | 51 +- gnulib/import/tempname.h | 2 +- gnulib/import/time.in.h | 48 +- gnulib/import/time_r.c | 2 +- gnulib/import/unistd--.h | 2 +- gnulib/import/unistd-safer.h | 2 +- gnulib/import/unistd.in.h | 613 +- gnulib/import/unsetenv.c | 2 +- gnulib/import/verify.h | 32 +- gnulib/import/warn-on-use.h | 33 +- gnulib/import/wchar.in.h | 45 +- gnulib/import/wctype.in.h | 11 +- gnulib/import/windows-initguard.h | 2 +- gnulib/import/windows-mutex.c | 2 +- gnulib/import/windows-mutex.h | 2 +- gnulib/import/windows-once.c | 2 +- gnulib/import/windows-once.h | 2 +- gnulib/import/windows-recmutex.c | 2 +- gnulib/import/windows-recmutex.h | 2 +- gnulib/import/windows-rwlock.c | 2 +- gnulib/import/windows-rwlock.h | 2 +- gnulib/import/wmemchr-impl.h | 2 +- gnulib/import/wmemchr.c | 2 +- gnulib/import/wmempcpy.c | 2 +- gnulib/import/xalloc-oversized.h | 4 +- gnulib/update-gnulib.sh | 2 +- gold/ChangeLog | 18 + gold/dwarf_reader.cc | 4 + gold/powerpc.cc | 1 - gold/testsuite/ifuncmain6pie.c | 14 +- gold/testsuite/ifuncmod6.c | 10 +- include/ChangeLog | 128 + include/bfdlink.h | 12 +- include/coff/i386.h | 11 + include/coff/internal.h | 151 +- include/coff/rs6000.h | 50 +- include/coff/rs6k64.h | 54 +- include/coff/ti.h | 22 +- include/coff/x86_64.h | 29 + include/coff/xcoff.h | 72 +- include/coff/z80.h | 16 + include/coff/z8k.h | 11 + include/ctf-api.h | 21 +- include/elf/common.h | 15 + include/elf/riscv.h | 3 +- include/gdb/ChangeLog | 4 + include/gdb/sim-riscv.h | 99 + include/opcode/riscv-opc.h | 196 +- include/opcode/riscv.h | 323 +- include/opcode/s390.h | 1 + include/opcode/tic54x.h | 8 +- intl/ChangeLog | 49 + intl/Makefile.in | 16 +- intl/aclocal.m4 | 1 + intl/configure | 113 +- intl/configure.ac | 30 +- intl/plural-config.h | 1 + intl/plural-exp.h | 8 +- intl/plural.c | 62 +- intl/plural.y | 27 +- ld/ChangeLog | 527 + ld/Makefile.am | 15 +- ld/Makefile.in | 16 +- ld/NEWS | 8 + ld/configure.tgt | 9 +- ld/emulparams/alphavms.sh | 3 +- ld/emulparams/armsymbian.sh | 25 - ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf64_ia64_vms.sh | 1 - ld/emulparams/elf64mmix.sh | 1 - ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_iamcu.sh | 1 - ld/emulparams/elf_k1om.sh | 1 - ld/emulparams/elf_l1om.sh | 1 - ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/mmo.sh | 1 - ld/emulparams/pdp11.sh | 5 + ld/emulparams/x86-report-relative.sh | 11 + ld/emultempl/aix.em | 38 + ld/emultempl/beos.em | 25 + ld/emultempl/elf.em | 6 +- ld/emultempl/pdp11.em | 30 +- ld/emultempl/pe.em | 34 + ld/emultempl/pep.em | 34 + ld/emultempl/riscvelf.em | 6 +- ld/ld.texi | 30 +- ld/ldelf.c | 29 +- ld/ldelf.h | 1 + ld/ldelfgen.c | 15 +- ld/ldexp.c | 37 +- ld/ldexp.h | 1 + ld/ldgram.y | 25 +- ld/ldlang.c | 38 +- ld/ldlex.h | 2 +- ld/ldlex.l | 31 +- ld/ldmain.c | 5 +- ld/lexsup.c | 13 +- ld/pe-dll.c | 15 +- ld/po/BLD-POTFILES.in | 1 - ld/scripttempl/DWARF.sc | 22 +- ld/scripttempl/aix.sc | 31 +- ld/scripttempl/armbpabi.sc | 417 - ld/scripttempl/mcorepe.sc | 2 +- ld/scripttempl/pdp11.sc | 2 +- ld/scripttempl/pe.sc | 81 +- ld/scripttempl/pep.sc | 87 +- ld/testplug.c | 5 +- ld/testsuite/ld-arm/arm-elf.exp | 4 - ld/testsuite/ld-arm/symbian-seg1.d | 8 - ld/testsuite/ld-arm/symbian-seg1.s | 13 - ld/testsuite/ld-bootstrap/bootstrap.exp | 1 + ld/testsuite/ld-cdtest/cdtest.exp | 4 +- ld/testsuite/ld-checks/checks.exp | 2 +- ld/testsuite/ld-ctf/data-func-2.c | 4 + ld/testsuite/ld-ctf/data-func-conflicted.d | 4 +- ld/testsuite/ld-elf/binutils.exp | 10 +- ld/testsuite/ld-elf/compress.exp | 20 +- ld/testsuite/ld-elf/compressed1d.d | 5 +- ld/testsuite/ld-elf/dwarf.exp | 6 +- ld/testsuite/ld-elf/elf.exp | 13 + ld/testsuite/ld-elf/exclude.exp | 4 +- ld/testsuite/ld-elf/frame.exp | 4 +- ld/testsuite/ld-elf/indirect.exp | 2 +- ld/testsuite/ld-elf/linux-x86.exp | 4 +- ld/testsuite/ld-elf/pr25708.d | 2 +- ld/testsuite/ld-elf/pr26936.d | 8 +- ld/testsuite/ld-elf/pr27128a.d | 2 +- ld/testsuite/ld-elf/pr27128b.d | 2 +- ld/testsuite/ld-elf/pr27128c.d | 2 +- ld/testsuite/ld-elf/pr27128d.d | 2 +- ld/testsuite/ld-elf/pr27128e.d | 2 +- ld/testsuite/ld-elf/pr27259.d | 7 + ld/testsuite/ld-elf/pr27259.s | 14 + ld/testsuite/ld-elf/sec-to-seg.exp | 2 +- ld/testsuite/ld-elf/sec64k.exp | 4 +- ld/testsuite/ld-elf/size-2.d | 2 +- ld/testsuite/ld-elf/tls_common.exp | 10 +- ld/testsuite/ld-elfcomm/elfcomm.exp | 11 +- ld/testsuite/ld-elfvers/vers.exp | 16 +- ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- ld/testsuite/ld-elfvsb/elfvsb.exp | 22 +- ld/testsuite/ld-elfweak/elfweak.exp | 6 +- ld/testsuite/ld-gc/abi-note.d | 1 - ld/testsuite/ld-gc/gc.exp | 48 +- ld/testsuite/ld-gc/pr13683.d | 1 + ld/testsuite/ld-gc/pr14265.d | 15 +- ld/testsuite/ld-gc/pr19167.d | 3 +- ld/testsuite/ld-gc/pr19167a.s | 4 + ld/testsuite/ld-gc/start.d | 5 +- ld/testsuite/ld-gc/start.s | 6 +- ld/testsuite/ld-gc/start2.d | 10 + ld/testsuite/ld-gc/start2.s | 12 + ld/testsuite/ld-gc/start3.d | 9 + ld/testsuite/ld-gc/start3.s | 29 + ld/testsuite/ld-gc/start4.d | 9 + ld/testsuite/ld-gc/start4.s | 19 + ld/testsuite/ld-gc/stop.d | 3 +- ld/testsuite/ld-i386/i386.exp | 69 +- ld/testsuite/ld-i386/pr27193.dd | 5 + ld/testsuite/ld-i386/pr27193a.o.bz2 | Bin 0 -> 468 bytes ld/testsuite/ld-i386/pr27193b.s | 8 + ld/testsuite/ld-i386/property-x86-isa1.d | 2 +- ld/testsuite/ld-i386/report-reloc-1.d | 10 + ld/testsuite/ld-i386/report-reloc-1.l | 2 + ld/testsuite/ld-i386/report-reloc-1.s | 12 + ld/testsuite/ld-ifunc/binutils.exp | 8 +- ld/testsuite/ld-ifunc/ifunc.exp | 26 +- ld/testsuite/ld-ifunc/pr23169a.c | 2 +- ld/testsuite/ld-mips-elf/mips-elf-flags.exp | 2 +- ld/testsuite/ld-misc/defsym.exp | 6 +- ld/testsuite/ld-mn10300/mn10300.exp | 16 +- ld/testsuite/ld-pe/pe.exp | 2 + ld/testsuite/ld-pe/reloc.d | 15 + ld/testsuite/ld-pe/reloc.s | 20 + ld/testsuite/ld-plugin/lto.exp | 66 +- ld/testsuite/ld-plugin/plugin.exp | 12 +- ld/testsuite/ld-plugin/pr15146.d | 4 + ld/testsuite/ld-plugin/pr15146a.c | 13 + ld/testsuite/ld-plugin/pr15146b.c | 1 + .../empty => ld/testsuite/ld-plugin/pr15146c.c | 0 ld/testsuite/ld-plugin/pr15146d.c | 7 + ld/testsuite/ld-plugin/pr27311.d | 4 + ld/testsuite/ld-plugin/pr27311.ver | 3 + ld/testsuite/ld-plugin/pr27311a.c | 1 + ld/testsuite/ld-plugin/pr27311b.c | 1 + ld/testsuite/ld-plugin/pr27311c.c | 5 + ld/testsuite/ld-plugin/pr27311d.c | 5 + ld/testsuite/ld-plugin/pr27441a.c | 2 + ld/testsuite/ld-plugin/pr27441b.c | 1 + ld/testsuite/ld-plugin/pr27441c.c | 8 + ld/testsuite/ld-plugin/pr27441c.d | 4 + ld/testsuite/ld-powerpc/aix-largetoc-1-32.d | 20 + ld/testsuite/ld-powerpc/aix-largetoc-1-64.d | 20 + .../{aix-abs-branch-1.ex => aix-largetoc-1.ex} | 0 ld/testsuite/ld-powerpc/aix-largetoc-1.s | 25 + ld/testsuite/ld-powerpc/aix-tls-reloc-32.d | 35 + ld/testsuite/ld-powerpc/aix-tls-reloc-64.d | 31 + .../{aix-abs-branch-1.ex => aix-tls-reloc.ex} | 0 ld/testsuite/ld-powerpc/aix-tls-reloc.s | 65 + ld/testsuite/ld-powerpc/aix-tls-section-32.d | 15 + ld/testsuite/ld-powerpc/aix-tls-section-64.d | 15 + .../aix-tls-section.ex} | 0 ld/testsuite/ld-powerpc/aix-tls-section.s | 8 + ld/testsuite/ld-powerpc/aix52.exp | 27 + ld/testsuite/ld-powerpc/powerpc.exp | 9 + ld/testsuite/ld-powerpc/relbrlt.d | 46 +- ld/testsuite/ld-powerpc/relbrlt.s | 5 +- ld/testsuite/ld-powerpc/startstop.d | 10 + ld/testsuite/ld-powerpc/startstop.r | 2 + ld/testsuite/ld-powerpc/startstop.s | 16 + ld/testsuite/ld-powerpc/tlsexe.r | 13 - ld/testsuite/ld-powerpc/tlsexe32.r | 12 - ld/testsuite/ld-powerpc/tlsexe32no.r | 12 - ld/testsuite/ld-powerpc/tlsexeno.r | 13 - ld/testsuite/ld-powerpc/tlsexenors.r | 13 - ld/testsuite/ld-powerpc/tlsexers.r | 13 - ld/testsuite/ld-powerpc/tlsexetoc.r | 13 - ld/testsuite/ld-powerpc/tlsexetocrs.r | 13 - ld/testsuite/ld-powerpc/tlsget.d | 23 +- ld/testsuite/ld-powerpc/tlsget.wf | 4 +- ld/testsuite/ld-powerpc/tlsget2.d | 16 +- ld/testsuite/ld-powerpc/tlsget2.wf | 2 +- ld/testsuite/ld-powerpc/tlsso.r | 12 - ld/testsuite/ld-powerpc/tlsso32.r | 11 - ld/testsuite/ld-powerpc/tlstocso.r | 12 - ld/testsuite/ld-powerpc/weak1.d | 26 + ld/testsuite/ld-powerpc/weak1.r | 5 + ld/testsuite/ld-powerpc/weak1.s | 22 + ld/testsuite/ld-powerpc/weak1so.d | 26 + ld/testsuite/ld-powerpc/weak1so.r | 7 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 1 + ld/testsuite/ld-riscv-elf/restart-relax.d | 14 + ld/testsuite/ld-riscv-elf/restart-relax.s | 17 + ld/testsuite/ld-scripts/align.exp | 2 +- ld/testsuite/ld-scripts/alignof.exp | 9 +- ld/testsuite/ld-scripts/assert.exp | 2 +- ld/testsuite/ld-scripts/crossref.exp | 16 +- ld/testsuite/ld-scripts/data.exp | 4 +- ld/testsuite/ld-scripts/default-script.exp | 2 + ld/testsuite/ld-scripts/default-script1.d | 2 - ld/testsuite/ld-scripts/default-script2.d | 2 - ld/testsuite/ld-scripts/default-script3.d | 2 - ld/testsuite/ld-scripts/default-script4.d | 2 - ld/testsuite/ld-scripts/defined.exp | 2 +- ld/testsuite/ld-scripts/defined5.d | 5 +- ld/testsuite/ld-scripts/extern.exp | 2 +- ld/testsuite/ld-scripts/log2.exp | 11 +- ld/testsuite/ld-scripts/map-address.exp | 16 +- ld/testsuite/ld-scripts/map-address.t | 3 + ld/testsuite/ld-scripts/phdrs.exp | 6 +- ld/testsuite/ld-scripts/phdrs2.exp | 7 +- ld/testsuite/ld-scripts/pr22267.d | 3 +- ld/testsuite/ld-scripts/pr22267.t | 2 +- ld/testsuite/ld-scripts/print-memory-usage.exp | 6 + ld/testsuite/ld-scripts/script.exp | 2 +- ld/testsuite/ld-scripts/section-flags.exp | 2 +- ld/testsuite/ld-scripts/sizeof.exp | 11 +- ld/testsuite/ld-scripts/weak.exp | 8 +- ld/testsuite/ld-selective/selective.exp | 2 +- ld/testsuite/ld-sh/sh.exp | 20 +- ld/testsuite/ld-shared/shared.exp | 16 +- ld/testsuite/ld-srec/srec.exp | 17 +- ld/testsuite/ld-tic6x/tic6x.exp | 9 +- ld/testsuite/ld-undefined/undefined.exp | 92 +- ld/testsuite/ld-undefined/weak-undef.exp | 18 +- ld/testsuite/ld-x86-64/bnd-plt-1.d | 4 +- ld/testsuite/ld-x86-64/pe-x86-64-1.od | 1 + ld/testsuite/ld-x86-64/pe-x86-64-2.od | 1 + ld/testsuite/ld-x86-64/pe-x86-64-3.od | 1 + ld/testsuite/ld-x86-64/pe-x86-64-4.od | 1 + ld/testsuite/ld-x86-64/pe-x86-64-5.od | 1 + ld/testsuite/ld-x86-64/pe-x86-64-5.rd | 3 +- ld/testsuite/ld-x86-64/pe-x86-64-6.obj.bz2 | Bin 0 -> 1366 bytes ld/testsuite/ld-x86-64/pe-x86-64-6.od | 91 + ld/testsuite/ld-x86-64/pe-x86-64.exp | 9 + ld/testsuite/ld-x86-64/pr19609-2a.d | 2 +- ld/testsuite/ld-x86-64/pr19609-2b.d | 2 +- ld/testsuite/ld-x86-64/pr19609-4a.d | 2 +- ld/testsuite/ld-x86-64/pr19609-4c.d | 2 +- ld/testsuite/ld-x86-64/pr19609-5d.d | 2 +- ld/testsuite/ld-x86-64/pr19609-7a.d | 2 +- ld/testsuite/ld-x86-64/pr19609-7c.d | 2 +- ld/testsuite/ld-x86-64/property-x86-isa1-x32.d | 2 +- ld/testsuite/ld-x86-64/property-x86-isa1.d | 2 +- ld/testsuite/ld-x86-64/report-reloc-1-x32.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.l | 2 + ld/testsuite/ld-x86-64/report-reloc-1.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 65 +- ld/testsuite/lib/ld-lib.exp | 161 +- libctf/ChangeLog | 273 + libctf/Makefile.am | 6 +- libctf/Makefile.in | 100 +- libctf/NEWS | 26 + libctf/configure | 293 +- libctf/configure.ac | 30 +- libctf/ctf-archive.c | 250 +- libctf/ctf-create.c | 304 +- libctf/ctf-dedup.c | 222 +- libctf/ctf-dump.c | 4 +- libctf/ctf-impl.h | 31 +- libctf/ctf-link.c | 609 +- libctf/ctf-lookup.c | 290 +- libctf/ctf-open.c | 22 +- libctf/ctf-string.c | 9 +- libctf/ctf-types.c | 123 +- libctf/libctf.ver | 6 + libctf/testsuite/config/default.exp | 1 + libctf/testsuite/lib/ctf-lib.exp | 183 +- .../libctf-lookup/conflicting-type-syms-a.c | 5 + .../libctf-lookup/conflicting-type-syms-b.c | 5 + .../libctf-lookup/conflicting-type-syms.c | 99 + .../libctf-lookup/conflicting-type-syms.lk | 7 + libctf/testsuite/libctf-lookup/enum-symbol-obj.lk | 5 + libctf/testsuite/libctf-lookup/enum-symbol.c | 115 +- .../nonstatic-var-section-ld-executable.lk | 9 + .../nonstatic-var-section-ld-r-ctf.c | 9 + .../libctf-regression/nonstatic-var-section-ld-r.c | 73 + .../nonstatic-var-section-ld-r.lk | 7 + .../libctf-regression/nonstatic-var-section-ld.c | 76 + .../libctf-regression/nonstatic-var-section-ld.lk | 6 + libctf/testsuite/libctf-regression/pptrtab-a.c | 2 + libctf/testsuite/libctf-regression/pptrtab-b.c | 3 +- libctf/testsuite/libctf-regression/pptrtab.c | 10 +- .../type-add-unnamed-struct-ctf.c | 19 + .../libctf-regression/type-add-unnamed-struct.c | 72 + .../libctf-regression/type-add-unnamed-struct.lk | 3 + .../symtypetab-nonlinker-writeout.c | 252 + .../symtypetab-nonlinker-writeout.lk | 12 + opcodes/ChangeLog | 456 + opcodes/aarch64-opc.c | 10 + opcodes/configure | 8 +- opcodes/configure.ac | 8 +- opcodes/i386-dis-evex-len.h | 338 +- opcodes/i386-dis-evex-mod.h | 64 +- opcodes/i386-dis-evex-prefix.h | 4 +- opcodes/i386-dis-evex-reg.h | 20 +- opcodes/i386-dis-evex-w.h | 148 +- opcodes/i386-dis-evex.h | 66 +- opcodes/i386-dis.c | 1814 +-- opcodes/i386-gen.c | 73 +- opcodes/i386-opc.h | 31 +- opcodes/i386-opc.tbl | 6848 ++++----- opcodes/i386-tbl.h | 14902 ++++++++++--------- opcodes/riscv-dis.c | 88 +- opcodes/riscv-opc.c | 1528 +- opcodes/s390-mkopc.c | 2 + opcodes/s390-opc.txt | 28 + opcodes/tic54x-dis.c | 2 +- opcodes/tic54x-opc.c | 14 +- opcodes/wasm32-dis.c | 26 +- readline/ChangeLog | 9 + readline/readline/CHANGELOG | 61 +- readline/readline/CHANGES | 123 + readline/readline/ChangeLog.gdb | 4 + readline/readline/INSTALL | 7 +- readline/readline/Makefile.in | 4 +- readline/readline/NEWS | 62 + readline/readline/README | 2 +- readline/readline/aclocal.m4 | 2130 +-- readline/readline/bind.c | 256 +- readline/readline/colors.c | 9 +- readline/readline/complete.c | 104 +- readline/readline/configure | 66 +- readline/readline/configure.ac | 33 +- readline/readline/display.c | 824 +- readline/readline/doc/history.3 | 55 +- readline/readline/doc/history.texi | 2 +- readline/readline/doc/hstech.texi | 6 +- readline/readline/doc/hsuser.texi | 39 +- readline/readline/doc/readline.3 | 53 +- readline/readline/doc/rlman.texi | 2 +- readline/readline/doc/rltech.texi | 42 +- readline/readline/doc/rluser.texi | 79 +- readline/readline/doc/rluserman.texi | 2 +- readline/readline/doc/texi2dvi | 1680 ++- readline/readline/doc/version.texi | 12 +- readline/readline/emacs_keymap.c | 4 +- .../examples/autoconf/BASH_CHECK_LIB_TERMCAP | 3 +- .../examples/autoconf/RL_LIB_READLINE_VERSION | 1 + readline/readline/examples/fileman.c | 4 +- readline/readline/funmap.c | 10 +- readline/readline/histexpand.c | 26 +- readline/readline/histfile.c | 52 +- readline/readline/input.c | 43 +- readline/readline/isearch.c | 75 +- readline/readline/kill.c | 110 +- readline/readline/mbutil.c | 106 +- readline/readline/misc.c | 63 +- readline/readline/patchlevel | 2 +- readline/readline/posixdir.h | 2 +- readline/readline/posixstat.h | 8 +- readline/readline/readline.c | 98 +- readline/readline/readline.h | 16 +- readline/readline/readline.pc.in | 2 +- readline/readline/rlmbutil.h | 2 +- readline/readline/rlprivate.h | 42 +- readline/readline/search.c | 47 +- readline/readline/shlib/Makefile.in | 2 +- readline/readline/signals.c | 89 +- readline/readline/support/config.guess | 366 +- readline/readline/support/config.sub | 648 +- readline/readline/support/shlib-install | 36 +- readline/readline/support/shobj-conf | 59 +- readline/readline/terminal.c | 76 +- readline/readline/text.c | 105 +- readline/readline/tilde.c | 18 +- readline/readline/undo.c | 2 + readline/readline/util.c | 18 +- readline/readline/vi_mode.c | 182 +- sim/ChangeLog | 124 +- sim/MAINTAINERS | 4 +- sim/Makefile.am | 38 + sim/Makefile.in | 827 +- sim/README-HACKING | 18 +- sim/aarch64/ChangeLog | 18 + sim/aarch64/aclocal.m4 | 39 +- sim/aarch64/configure | 2678 +--- sim/aarch64/configure.ac | 2 +- sim/aclocal.m4 | 1172 ++ sim/arm/ChangeLog | 20 +- sim/arm/aclocal.m4 | 39 +- sim/arm/configure | 2678 +--- sim/arm/configure.ac | 2 +- sim/avr/ChangeLog | 26 + sim/avr/aclocal.m4 | 39 +- sim/avr/configure | 2678 +--- sim/avr/configure.ac | 2 +- sim/avr/interp.c | 7 - sim/bfin/ChangeLog | 26 + sim/bfin/aclocal.m4 | 42 +- sim/bfin/configure | 2698 +--- sim/bfin/configure.ac | 3 +- sim/bfin/interp.c | 7 - sim/bpf/ChangeLog | 28 + sim/bpf/aclocal.m4 | 43 +- sim/bpf/configure | 2678 +--- sim/bpf/configure.ac | 2 +- sim/bpf/decode-be.c | 70 +- sim/bpf/decode-le.c | 70 +- sim/bpf/mloop.in | 2 +- sim/common/ChangeLog | 111 + sim/common/Make-common.in | 31 +- sim/common/Makefile.in | 135 - sim/common/acinclude.m4 | 893 -- sim/common/aclocal.m4 | 15 - sim/common/cgen-accfp.c | 6 +- sim/common/cgen-trace.c | 2 +- sim/common/configure | 3718 ----- sim/common/configure.ac | 34 - sim/common/create-version.sh | 17 +- sim/common/gennltvals.py | 232 + sim/common/gennltvals.sh | 101 - sim/common/gentvals.sh | 74 - sim/common/nltvals.def | 232 +- sim/common/sim-events.c | 58 + sim/common/sim-events.h | 11 + sim/common/sim-hw.c | 67 +- sim/common/sim-profile.c | 4 +- sim/common/sim-watch.c | 20 +- sim/common/sim-watch.h | 2 - sim/configure | 2464 ++- sim/configure.ac | 137 +- sim/configure.tgt | 111 - sim/cr16/ChangeLog | 28 +- sim/cr16/Makefile.in | 6 +- sim/cr16/aclocal.m4 | 39 +- sim/cr16/configure | 2678 +--- sim/cr16/configure.ac | 2 +- sim/cris/ChangeLog | 18 + sim/cris/aclocal.m4 | 43 +- sim/cris/configure | 2678 +--- sim/cris/configure.ac | 2 +- sim/d10v/ChangeLog | 28 +- sim/d10v/Makefile.in | 6 +- sim/d10v/aclocal.m4 | 39 +- sim/d10v/configure | 2678 +--- sim/d10v/configure.ac | 2 +- sim/erc32/ChangeLog | 27 + sim/erc32/Makefile.in | 2 +- sim/erc32/aclocal.m4 | 37 +- sim/erc32/configure | 2678 +--- sim/erc32/configure.ac | 2 +- sim/erc32/interf.c | 6 + sim/frv/ChangeLog | 26 + sim/frv/aclocal.m4 | 43 +- sim/frv/configure | 2678 +--- sim/frv/configure.ac | 2 +- sim/frv/sim-if.c | 9 - sim/ft32/ChangeLog | 18 + sim/ft32/aclocal.m4 | 39 +- sim/ft32/configure | 2678 +--- sim/ft32/configure.ac | 2 +- sim/h8300/ChangeLog | 18 + sim/h8300/aclocal.m4 | 39 +- sim/h8300/configure | 2678 +--- sim/h8300/configure.ac | 2 +- sim/igen/ChangeLog | 80 + sim/igen/Makefile.in | 41 +- sim/igen/config.in | 64 - sim/igen/configure | 4923 ++---- sim/igen/configure.ac | 34 +- sim/igen/filter.c | 3 - sim/igen/filter_host.c | 1 - sim/igen/gen.c | 2 +- sim/igen/igen.c | 1 - sim/igen/ld-decode.c | 2 +- sim/igen/ld-insn.c | 2 +- sim/igen/lf.c | 1 - sim/igen/misc.c | 1 - sim/igen/misc.h | 3 - sim/igen/table.c | 3 - sim/iq2000/ChangeLog | 26 + sim/iq2000/aclocal.m4 | 43 +- sim/iq2000/configure | 2678 +--- sim/iq2000/configure.ac | 2 +- sim/iq2000/sim-if.c | 9 - sim/lm32/ChangeLog | 18 + sim/lm32/aclocal.m4 | 43 +- sim/lm32/configure | 2678 +--- sim/lm32/configure.ac | 2 +- sim/m32c/ChangeLog | 31 + sim/m32c/Makefile.in | 6 +- sim/m32c/aclocal.m4 | 37 +- sim/m32c/configure | 2678 +--- sim/m32c/configure.ac | 2 +- sim/m32c/gdb-if.c | 6 + sim/m32r/ChangeLog | 26 + sim/m32r/aclocal.m4 | 43 +- sim/m32r/configure | 2678 +--- sim/m32r/configure.ac | 2 +- sim/m32r/sim-if.c | 9 - sim/m4/sim_ac_common.m4 | 261 + sim/m4/sim_ac_option_alignment.m4 | 66 + sim/m4/sim_ac_option_assert.m4 | 31 + sim/m4/sim_ac_option_bitsize.m4 | 81 + sim/m4/sim_ac_option_cgen_maint.m4 | 56 + sim/m4/sim_ac_option_default_model.m4 | 31 + sim/m4/sim_ac_option_endian.m4 | 65 + sim/m4/sim_ac_option_environment.m4 | 45 + sim/m4/sim_ac_option_float.m4 | 47 + sim/m4/sim_ac_option_hardware.m4 | 81 + sim/m4/sim_ac_option_inline.m4 | 50 + sim/m4/sim_ac_option_reserved_bits.m4 | 30 + sim/m4/sim_ac_option_scache.m4 | 34 + sim/m4/sim_ac_option_smp.m4 | 31 + sim/m4/sim_ac_option_warnings.m4 | 103 + sim/m4/sim_ac_option_xor_endian.m4 | 30 + sim/m4/sim_ac_output.m4 | 62 + sim/m68hc11/ChangeLog | 46 + sim/m68hc11/Makefile.in | 7 +- sim/m68hc11/aclocal.m4 | 40 +- sim/m68hc11/configure | 2698 +--- sim/m68hc11/configure.ac | 17 +- sim/m68hc11/dv-m68hc11.c | 1 + sim/m68hc11/dv-m68hc11tim.c | 2 +- sim/m68hc11/interp.c | 4 +- sim/m68hc11/m68hc11_sim.c | 14 +- sim/mcore/ChangeLog | 19 +- sim/mcore/aclocal.m4 | 39 +- sim/mcore/configure | 2678 +--- sim/mcore/configure.ac | 2 +- sim/microblaze/ChangeLog | 18 + sim/microblaze/aclocal.m4 | 39 +- sim/microblaze/configure | 2678 +--- sim/microblaze/configure.ac | 2 +- sim/mips/ChangeLog | 31 + sim/mips/Makefile.in | 2 +- sim/mips/aclocal.m4 | 43 +- sim/mips/configure | 2678 +--- sim/mips/configure.ac | 2 +- sim/mips/interp.c | 2 - sim/mn10300/ChangeLog | 27 +- sim/mn10300/aclocal.m4 | 42 +- sim/mn10300/configure | 2678 +--- sim/mn10300/configure.ac | 2 +- sim/mn10300/interp.c | 2 - sim/moxie/ChangeLog | 32 + sim/moxie/aclocal.m4 | 39 +- sim/moxie/configure | 2683 +--- sim/moxie/configure.ac | 3 +- sim/moxie/interp.c | 5 +- sim/msp430/ChangeLog | 26 + sim/msp430/Makefile.in | 4 - sim/msp430/aclocal.m4 | 39 +- sim/msp430/configure | 2678 +--- sim/msp430/configure.ac | 2 +- sim/or1k/ChangeLog | 23 + sim/or1k/aclocal.m4 | 43 +- sim/or1k/configure | 2668 +--- sim/or1k/configure.ac | 2 +- sim/or1k/decode.c | 114 +- sim/ppc/ChangeLog | 41 +- sim/ppc/Makefile.in | 66 +- sim/ppc/aclocal.m4 | 18 + sim/ppc/configure | 2332 +-- sim/ppc/configure.ac | 5 +- sim/pru/ChangeLog | 18 + sim/pru/aclocal.m4 | 39 +- sim/pru/configure | 2678 +--- sim/pru/configure.ac | 2 +- sim/riscv/ChangeLog | 29 + sim/riscv/Makefile.in | 30 + sim/riscv/aclocal.m4 | 122 + sim/{aarch64 => riscv}/config.in | 0 sim/riscv/configure | 14445 ++++++++++++++++++ sim/riscv/configure.ac | 28 + sim/riscv/interp.c | 153 + sim/riscv/machs.c | 125 + sim/riscv/machs.h | 45 + sim/riscv/model_list.def | 9 + sim/riscv/sim-main.c | 1220 ++ sim/riscv/sim-main.h | 86 + sim/rl78/ChangeLog | 22 + sim/rl78/aclocal.m4 | 37 +- sim/rl78/configure | 2678 +--- sim/rl78/configure.ac | 2 +- sim/rl78/gdb-if.c | 6 + sim/rx/ChangeLog | 88 + sim/rx/aclocal.m4 | 37 +- sim/rx/configure | 2795 +--- sim/rx/configure.ac | 3 +- sim/rx/cpu.h | 2 +- sim/rx/err.c | 11 +- sim/rx/fpu.c | 2 +- sim/rx/gdb-if.c | 14 +- sim/rx/load.c | 3 +- sim/rx/mem.c | 18 +- sim/rx/mem.h | 4 +- sim/rx/reg.c | 14 +- sim/rx/rx.c | 6 +- sim/rx/syscalls.c | 7 +- sim/rx/trace.c | 9 +- sim/sh/ChangeLog | 24 +- sim/sh/Makefile.in | 8 +- sim/sh/aclocal.m4 | 39 +- sim/sh/configure | 2678 +--- sim/sh/configure.ac | 2 +- sim/testsuite/ChangeLog | 56 + sim/testsuite/Makefile.in | 182 - sim/testsuite/aarch64/ChangeLog | 87 + sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/aarch64/allinsn.exp | 19 + sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => }/aarch64/pass.s | 0 sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/stn_single.s | 0 sim/testsuite/{sim => }/aarch64/sumov.s | 0 sim/testsuite/{sim => }/aarch64/sumulh.s | 0 sim/testsuite/{sim => }/aarch64/tbnz.s | 0 sim/testsuite/{sim => }/aarch64/testutils.inc | 0 sim/testsuite/{sim => }/aarch64/uzp.s | 0 sim/testsuite/{sim => }/aarch64/xtl.s | 0 sim/testsuite/{sim => }/aarch64/xtn.s | 0 sim/testsuite/arm/ChangeLog | 127 + sim/testsuite/{sim => }/arm/adc.cgs | 0 sim/testsuite/{sim => }/arm/add.cgs | 0 sim/testsuite/arm/allinsn.exp | 29 + sim/testsuite/{sim => }/arm/and.cgs | 0 sim/testsuite/{sim => }/arm/b.cgs | 0 sim/testsuite/{sim => }/arm/bic.cgs | 0 sim/testsuite/{sim => }/arm/bl.cgs | 0 sim/testsuite/{sim => }/arm/bx.cgs | 0 sim/testsuite/{sim => }/arm/cmn.cgs | 0 sim/testsuite/{sim => }/arm/cmp.cgs | 0 sim/testsuite/{sim => }/arm/eor.cgs | 0 sim/testsuite/{sim => }/arm/hello.ms | 0 sim/testsuite/arm/iwmmxt/iwmmxt.exp | 29 + sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/arm/misc.exp | 21 + sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 0 sim/testsuite/{sim => }/arm/sub.cgs | 0 sim/testsuite/{sim => }/arm/swi.cgs | 0 sim/testsuite/{sim => }/arm/swp.cgs | 0 sim/testsuite/{sim => }/arm/swpb.cgs | 0 sim/testsuite/{sim => }/arm/teq.cgs | 0 sim/testsuite/{sim => }/arm/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0 sim/testsuite/arm/thumb/allthumb.exp | 21 + sim/testsuite/{sim => }/arm/thumb/and.cgs | 0 sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/b.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0 sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/arm/xscale/xscale.exp | 29 + sim/testsuite/avr/ChangeLog | 11 + sim/testsuite/avr/allinsn.exp | 19 + sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 sim/testsuite/{sim => }/bfin/10799.s | 0 sim/testsuite/{sim => }/bfin/11080.s | 0 sim/testsuite/{sim => }/bfin/7641.s | 0 sim/testsuite/bfin/ChangeLog | 378 + sim/testsuite/{sim => }/bfin/PN_generator.s | 0 sim/testsuite/{sim => }/bfin/a0.s | 0 sim/testsuite/{sim => }/bfin/a0shift.S | 0 sim/testsuite/{sim => }/bfin/a1.s | 0 sim/testsuite/{sim => }/bfin/a10.s | 0 sim/testsuite/{sim => }/bfin/a11.S | 0 sim/testsuite/{sim => }/bfin/a12.s | 0 sim/testsuite/{sim => }/bfin/a2.s | 0 sim/testsuite/{sim => }/bfin/a20.S | 0 sim/testsuite/{sim => }/bfin/a21.s | 0 sim/testsuite/{sim => }/bfin/a22.s | 0 sim/testsuite/{sim => }/bfin/a23.s | 0 sim/testsuite/{sim => }/bfin/a24.s | 0 sim/testsuite/{sim => }/bfin/a25.s | 0 sim/testsuite/{sim => }/bfin/a26.s | 0 sim/testsuite/{sim => }/bfin/a3.s | 0 sim/testsuite/{sim => }/bfin/a30.s | 0 sim/testsuite/{sim => }/bfin/a4.s | 0 sim/testsuite/{sim => }/bfin/a5.s | 0 sim/testsuite/{sim => }/bfin/a6.s | 0 sim/testsuite/{sim => }/bfin/a7.s | 0 sim/testsuite/{sim => }/bfin/a8.s | 0 sim/testsuite/{sim => }/bfin/a9.s | 0 sim/testsuite/{sim => }/bfin/abs-2.S | 0 sim/testsuite/{sim => }/bfin/abs-3.S | 0 sim/testsuite/{sim => }/bfin/abs-4.S | 0 sim/testsuite/{sim => }/bfin/abs.S | 0 sim/testsuite/{sim => }/bfin/abs_acc.s | 0 sim/testsuite/{sim => }/bfin/acc-rot.s | 0 sim/testsuite/{sim => }/bfin/acp5_19.s | 0 sim/testsuite/{sim => }/bfin/acp5_4.s | 0 sim/testsuite/{sim => }/bfin/add_imm7.s | 0 sim/testsuite/{sim => }/bfin/add_shift.S | 0 sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0 sim/testsuite/{sim => }/bfin/addsub_flags.S | 0 sim/testsuite/{sim => }/bfin/algnbug1.s | 0 sim/testsuite/{sim => }/bfin/algnbug2.s | 0 sim/testsuite/bfin/allinsn.exp | 47 + sim/testsuite/{sim => }/bfin/argc.c | 0 sim/testsuite/{sim => }/bfin/ashift.s | 0 sim/testsuite/{sim => }/bfin/ashift_flags.s | 0 sim/testsuite/{sim => }/bfin/ashift_left.s | 0 sim/testsuite/{sim => }/bfin/b0.S | 0 sim/testsuite/{sim => }/bfin/b1.s | 0 sim/testsuite/{sim => }/bfin/b2.S | 0 sim/testsuite/{sim => }/bfin/brcc.s | 0 sim/testsuite/{sim => }/bfin/brevadd.s | 0 sim/testsuite/{sim => }/bfin/byteop16m.s | 0 sim/testsuite/{sim => }/bfin/byteop16p.s | 0 sim/testsuite/{sim => }/bfin/byteop1p.s | 0 sim/testsuite/{sim => }/bfin/byteop2p.s | 0 sim/testsuite/{sim => }/bfin/byteop3p.s | 0 sim/testsuite/{sim => }/bfin/byteunpack.s | 0 .../{sim => }/bfin/c_alu2op_arith_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0 .../{sim => }/bfin/c_alu2op_conv_toggle.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0 .../{sim => }/bfin/c_br_preg_killed_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0 .../{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0 sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0 sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0 sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0 .../{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_minus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_plus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodik_lz_inc_dec.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodim_lz_inc_dec.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_absabs.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s | 0 .../{sim => }/bfin/c_dsp32alu_byteop1ew.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s | 0 .../{sim => }/bfin/c_dsp32alu_byteunpack.s | 0 .../{sim => }/bfin/c_dsp32alu_disalnexcpt.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s | 0 .../{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s | 0 .../{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_u.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_is.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_s.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s | 0 .../{sim => }/bfin/c_dsp32shift_align16.s | 0 .../{sim => }/bfin/c_dsp32shift_align24.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_h.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_l.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_r.s | 0 .../{sim => }/bfin/c_dsp32shift_expexp_r.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s | 0 .../{sim => }/bfin/c_dsp32shift_rot_mix.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_r.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rh.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rl.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s | 0 .../{sim => }/bfin/c_dsp32shift_vmaxvmax.s | 0 .../{sim => }/bfin/c_dsp32shiftim_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahh_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_ld_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_st_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_except_illopcode.S | 0 sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S | 0 sim/testsuite/{sim => }/bfin/c_except_user_mode.S | 0 sim/testsuite/{sim => }/bfin/c_interr_disable.S | 0 .../{sim => }/bfin/c_interr_disable_enable.S | 0 sim/testsuite/{sim => }/bfin/c_interr_excpt.S | 0 .../{sim => }/bfin/c_interr_loopsetup_stld.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nested.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nmi.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending_2.S | 0 sim/testsuite/{sim => }/bfin/c_interr_timer.S | 0 .../{sim => }/bfin/c_interr_timer_reload.S | 0 .../{sim => }/bfin/c_interr_timer_tcount.S | 0 .../{sim => }/bfin/c_interr_timer_tscale.S | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s | 0 .../{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s | 0 .../{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_linkage.s | 0 .../{sim => }/bfin/c_logi2op_alshft_mix.s | 0 .../{sim => }/bfin/c_logi2op_arith_shft.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft_astat.S | 0 .../{sim => }/bfin/c_logi2op_log_r_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_r_shft_astat.S | 0 sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s | 0 .../{sim => }/bfin/c_loopsetup_nested_bot.s | 0 .../{sim => }/bfin/c_loopsetup_nested_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_nested_top.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_stld.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_topbotcntr.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_loop.S | 0 .../{sim => }/bfin/c_mmr_loop_user_except.S | 0 .../{sim => }/bfin/c_mmr_ppop_illegal_adr.S | 0 .../{sim => }/bfin/c_mmr_ppopm_illegal_adr.S | 0 sim/testsuite/{sim => }/bfin/c_mmr_timer.S | 0 sim/testsuite/{sim => }/bfin/c_mode_supervisor.S | 0 sim/testsuite/{sim => }/bfin/c_mode_user.S | 0 .../{sim => }/bfin/c_mode_user_superivsor.S | 0 .../{sim => }/bfin/c_multi_issue_dsp_ld_ld.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_1.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_2.s | 0 .../{sim => }/bfin/c_progctrl_call_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s | 0 .../{sim => }/bfin/c_progctrl_clisti_interr.S | 0 .../{sim => }/bfin/c_progctrl_csync_mmr.S | 0 .../{sim => }/bfin/c_progctrl_except_rtx.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S | 0 .../{sim => }/bfin/c_progctrl_jump_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_nop.s | 0 .../{sim => }/bfin/c_progctrl_raise_rt_i_n.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_rts.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s | 0 .../{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp_pair.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dreg.s | 0 .../{sim => }/bfin/c_pushpopmultiple_preg.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s | 0 .../{sim => }/bfin/c_regmv_dr_dep_nostall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S | 0 .../{sim => }/bfin/c_seq_ac_raise_mv_ppop.S | 0 .../{sim => }/bfin/c_seq_ac_regmv_pushpop.S | 0 .../{sim => }/bfin/c_seq_dec_raise_pushpop.S | 0 .../{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_call_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0 sim/testsuite/{sim => }/bfin/c_ujump.s | 0 sim/testsuite/{sim => }/bfin/cc-alu.S | 0 sim/testsuite/{sim => }/bfin/cc-astat-bits.s | 0 sim/testsuite/{sim => }/bfin/cc0.s | 0 sim/testsuite/{sim => }/bfin/cc1.s | 0 sim/testsuite/{sim => }/bfin/cc5.S | 0 sim/testsuite/{sim => }/bfin/cec-exact-exception.S | 0 sim/testsuite/{sim => }/bfin/cec-ifetch.S | 0 sim/testsuite/{sim => }/bfin/cec-multi-pending.S | 0 sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S | 0 .../{sim => }/bfin/cec-non-operating-env.s | 0 sim/testsuite/{sim => }/bfin/cec-raise-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-snen-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S | 0 sim/testsuite/{sim => }/bfin/cec-system-call.S | 0 sim/testsuite/{sim => }/bfin/cir.s | 0 sim/testsuite/{sim => }/bfin/cir1.s | 0 sim/testsuite/{sim => }/bfin/cli-sti.s | 0 sim/testsuite/{sim => }/bfin/cmpacc.s | 0 sim/testsuite/{sim => }/bfin/cmpdreg.S | 0 sim/testsuite/{sim => }/bfin/compare.s | 0 sim/testsuite/{sim => }/bfin/conv_enc_gen.s | 0 sim/testsuite/{sim => }/bfin/cycles.s | 0 sim/testsuite/{sim => }/bfin/d0.s | 0 sim/testsuite/{sim => }/bfin/d1.s | 0 sim/testsuite/{sim => }/bfin/d2.s | 0 .../{sim => }/bfin/dbg_brprd_ntkn_src_kill.S | 0 .../{sim => }/bfin/dbg_brtkn_nprd_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_basic.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_umode.S | 0 .../{sim => }/bfin/disalnexcpt_implicit.S | 0 sim/testsuite/{sim => }/bfin/div0.s | 0 sim/testsuite/{sim => }/bfin/divq.s | 0 sim/testsuite/{sim => }/bfin/dotproduct.s | 0 sim/testsuite/{sim => }/bfin/dotproduct2.s | 0 sim/testsuite/{sim => }/bfin/double_prec_mult.s | 0 sim/testsuite/{sim => }/bfin/dsp_a4.s | 0 sim/testsuite/{sim => }/bfin/dsp_a7.s | 0 sim/testsuite/{sim => }/bfin/dsp_a8.s | 0 sim/testsuite/{sim => }/bfin/dsp_d0.s | 0 sim/testsuite/{sim => }/bfin/dsp_d1.s | 0 sim/testsuite/{sim => }/bfin/dsp_neg.S | 0 sim/testsuite/{sim => }/bfin/dsp_s1.s | 0 sim/testsuite/{sim => }/bfin/e0.s | 0 sim/testsuite/{sim => }/bfin/edn_snafu.s | 0 sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s | 0 sim/testsuite/{sim => }/bfin/events.s | 0 sim/testsuite/{sim => }/bfin/f221.s | 0 sim/testsuite/{sim => }/bfin/fact.s | 0 sim/testsuite/{sim => }/bfin/fir.s | 0 sim/testsuite/{sim => }/bfin/fsm.s | 0 sim/testsuite/{sim => }/bfin/greg2.s | 0 sim/testsuite/{sim => }/bfin/hwloop-bits.S | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-in.s | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-out.s | 0 sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s | 0 sim/testsuite/{sim => }/bfin/hwloop-nested.s | 0 sim/testsuite/{sim => }/bfin/i0.s | 0 sim/testsuite/{sim => }/bfin/iir.s | 0 sim/testsuite/{sim => }/bfin/issue103.s | 0 sim/testsuite/{sim => }/bfin/issue109.s | 0 sim/testsuite/{sim => }/bfin/issue112.s | 0 sim/testsuite/{sim => }/bfin/issue113.s | 0 sim/testsuite/{sim => }/bfin/issue117.s | 0 sim/testsuite/{sim => }/bfin/issue118.s | 0 sim/testsuite/{sim => }/bfin/issue119.s | 0 sim/testsuite/{sim => }/bfin/issue121.s | 0 sim/testsuite/{sim => }/bfin/issue123.s | 0 sim/testsuite/{sim => }/bfin/issue124.s | 0 sim/testsuite/{sim => }/bfin/issue125.s | 0 sim/testsuite/{sim => }/bfin/issue126.s | 0 sim/testsuite/{sim => }/bfin/issue127.s | 0 sim/testsuite/{sim => }/bfin/issue129.s | 0 sim/testsuite/{sim => }/bfin/issue139.S | 0 sim/testsuite/{sim => }/bfin/issue140.S | 0 sim/testsuite/{sim => }/bfin/issue142.s | 0 sim/testsuite/{sim => }/bfin/issue144.s | 0 sim/testsuite/{sim => }/bfin/issue146.S | 0 sim/testsuite/{sim => }/bfin/issue175.s | 0 sim/testsuite/{sim => }/bfin/issue205.s | 0 sim/testsuite/{sim => }/bfin/issue257.s | 0 sim/testsuite/{sim => }/bfin/issue272.S | 0 sim/testsuite/{sim => }/bfin/issue83.s | 0 sim/testsuite/{sim => }/bfin/issue89.s | 0 sim/testsuite/{sim => }/bfin/l0.s | 0 sim/testsuite/{sim => }/bfin/l0shift.s | 0 sim/testsuite/{sim => }/bfin/l2_loop.s | 0 sim/testsuite/{sim => }/bfin/link-2.s | 0 sim/testsuite/{sim => }/bfin/link.s | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_align.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_default.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S | 0 sim/testsuite/{sim => }/bfin/load.s | 0 sim/testsuite/{sim => }/bfin/logic.s | 0 sim/testsuite/{sim => }/bfin/loop_snafu.s | 0 sim/testsuite/{sim => }/bfin/loop_strncpy.s | 0 sim/testsuite/{sim => }/bfin/lp0.s | 0 sim/testsuite/{sim => }/bfin/lp1.s | 0 sim/testsuite/{sim => }/bfin/lsetup.s | 0 sim/testsuite/{sim => }/bfin/m0boundary.s | 0 sim/testsuite/{sim => }/bfin/m1.S | 0 sim/testsuite/{sim => }/bfin/m10.s | 0 sim/testsuite/{sim => }/bfin/m11.s | 0 sim/testsuite/{sim => }/bfin/m12.s | 0 sim/testsuite/{sim => }/bfin/m13.s | 0 sim/testsuite/{sim => }/bfin/m14.s | 0 sim/testsuite/{sim => }/bfin/m15.s | 0 sim/testsuite/{sim => }/bfin/m16.s | 0 sim/testsuite/{sim => }/bfin/m17.s | 0 sim/testsuite/{sim => }/bfin/m2.s | 0 sim/testsuite/{sim => }/bfin/m3.s | 0 sim/testsuite/{sim => }/bfin/m4.s | 0 sim/testsuite/{sim => }/bfin/m5.s | 0 sim/testsuite/{sim => }/bfin/m6.s | 0 sim/testsuite/{sim => }/bfin/m7.s | 0 sim/testsuite/{sim => }/bfin/m8.s | 0 sim/testsuite/{sim => }/bfin/m9.s | 0 sim/testsuite/{sim => }/bfin/mac2halfreg.S | 0 sim/testsuite/{sim => }/bfin/math.s | 0 sim/testsuite/{sim => }/bfin/max_min_flags.s | 0 sim/testsuite/{sim => }/bfin/mc_s2.s | 0 .../{sim => }/bfin/mdma-32bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c | 0 .../{sim => }/bfin/mdma-8bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c | 0 sim/testsuite/{sim => }/bfin/mdma-skel.h | 0 sim/testsuite/{sim => }/bfin/mem3.s | 0 sim/testsuite/{sim => }/bfin/mmr-exception.s | 0 sim/testsuite/{sim => }/bfin/move.s | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.10.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5_10.s | 0 sim/testsuite/{sim => }/bfin/mult.s | 0 sim/testsuite/{sim => }/bfin/neg-2.S | 0 sim/testsuite/{sim => }/bfin/neg-3.S | 0 sim/testsuite/{sim => }/bfin/neg.S | 0 sim/testsuite/{sim => }/bfin/nshift.s | 0 sim/testsuite/{sim => }/bfin/pr.s | 0 sim/testsuite/{sim => }/bfin/push-pop-multiple.s | 0 sim/testsuite/{sim => }/bfin/push-pop.s | 0 sim/testsuite/{sim => }/bfin/pushpopreg_1.s | 0 sim/testsuite/{sim => }/bfin/quadaddsub.s | 0 sim/testsuite/{sim => }/bfin/random_0001.s | 0 sim/testsuite/{sim => }/bfin/random_0002.S | 0 sim/testsuite/{sim => }/bfin/random_0003.S | 0 sim/testsuite/{sim => }/bfin/random_0004.S | 0 sim/testsuite/{sim => }/bfin/random_0005.S | 0 sim/testsuite/{sim => }/bfin/random_0006.S | 0 sim/testsuite/{sim => }/bfin/random_0007.S | 0 sim/testsuite/{sim => }/bfin/random_0008.S | 0 sim/testsuite/{sim => }/bfin/random_0009.S | 0 sim/testsuite/{sim => }/bfin/random_0010.S | 0 sim/testsuite/{sim => }/bfin/random_0011.S | 0 sim/testsuite/{sim => }/bfin/random_0012.S | 0 sim/testsuite/{sim => }/bfin/random_0013.S | 0 sim/testsuite/{sim => }/bfin/random_0014.S | 0 sim/testsuite/{sim => }/bfin/random_0015.S | 0 sim/testsuite/{sim => }/bfin/random_0016.S | 0 sim/testsuite/{sim => }/bfin/random_0017.S | 0 sim/testsuite/{sim => }/bfin/random_0018.S | 0 sim/testsuite/{sim => }/bfin/random_0019.S | 0 sim/testsuite/{sim => }/bfin/random_0020.S | 0 sim/testsuite/{sim => }/bfin/random_0021.S | 0 sim/testsuite/{sim => }/bfin/random_0022.S | 0 sim/testsuite/{sim => }/bfin/random_0023.S | 0 sim/testsuite/{sim => }/bfin/random_0024.S | 0 sim/testsuite/{sim => }/bfin/random_0025.S | 0 sim/testsuite/{sim => }/bfin/random_0026.S | 0 sim/testsuite/{sim => }/bfin/random_0027.S | 0 sim/testsuite/{sim => }/bfin/random_0028.S | 0 sim/testsuite/{sim => }/bfin/random_0029.S | 0 sim/testsuite/{sim => }/bfin/random_0030.S | 0 sim/testsuite/{sim => }/bfin/random_0031.S | 0 sim/testsuite/{sim => }/bfin/random_0032.S | 0 sim/testsuite/{sim => }/bfin/random_0033.S | 0 sim/testsuite/{sim => }/bfin/random_0034.S | 0 sim/testsuite/{sim => }/bfin/random_0035.S | 0 sim/testsuite/{sim => }/bfin/random_0036.S | 0 sim/testsuite/{sim => }/bfin/random_0037.S | 0 sim/testsuite/{sim => }/bfin/run-tests.sh | 0 sim/testsuite/{sim => }/bfin/s0.s | 0 sim/testsuite/{sim => }/bfin/s1.s | 0 sim/testsuite/{sim => }/bfin/s10.s | 0 sim/testsuite/{sim => }/bfin/s11.s | 0 sim/testsuite/{sim => }/bfin/s12.s | 0 sim/testsuite/{sim => }/bfin/s13.s | 0 sim/testsuite/{sim => }/bfin/s14.s | 0 sim/testsuite/{sim => }/bfin/s15.s | 0 sim/testsuite/{sim => }/bfin/s16.s | 0 sim/testsuite/{sim => }/bfin/s17.s | 0 sim/testsuite/{sim => }/bfin/s18.s | 0 sim/testsuite/{sim => }/bfin/s19.s | 0 sim/testsuite/{sim => }/bfin/s2.s | 0 sim/testsuite/{sim => }/bfin/s20.s | 0 sim/testsuite/bfin/s21.s | 297 + sim/testsuite/{sim => }/bfin/s3.s | 0 sim/testsuite/{sim => }/bfin/s30.s | 0 sim/testsuite/{sim => }/bfin/s4.s | 0 sim/testsuite/{sim => }/bfin/s5.s | 0 sim/testsuite/{sim => }/bfin/s6.s | 0 sim/testsuite/{sim => }/bfin/s7.s | 0 sim/testsuite/{sim => }/bfin/s8.s | 0 sim/testsuite/{sim => }/bfin/s9.s | 0 sim/testsuite/{sim => }/bfin/saatest.s | 0 sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S | 0 sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S | 0 .../{sim => }/bfin/se_all32bitopcodes.lds | 0 .../{sim => }/bfin/se_all64bitg0opcodes.S | 0 .../{sim => }/bfin/se_all64bitg1opcodes.S | 0 .../{sim => }/bfin/se_all64bitg2opcodes.S | 0 sim/testsuite/{sim => }/bfin/se_allopcodes.h | 0 sim/testsuite/{sim => }/bfin/se_brtarget_stall.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui2.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui3.S | 0 sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S | 0 sim/testsuite/{sim => }/bfin/se_cc_kill.S | 0 sim/testsuite/{sim => }/bfin/se_cof.S | 0 sim/testsuite/{sim => }/bfin/se_event_quad.S | 0 .../{sim => }/bfin/se_excpt_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S | 0 .../{sim => }/bfin/se_illegalcombination.S | 0 sim/testsuite/{sim => }/bfin/se_kill_wbbr.S | 0 sim/testsuite/{sim => }/bfin/se_kills2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_disable.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_lr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S | 0 sim/testsuite/{sim => }/bfin/se_lsetup_kill.S | 0 sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S | 0 sim/testsuite/{sim => }/bfin/se_more_ret_haz.S | 0 sim/testsuite/{sim => }/bfin/se_mv2lp.S | 0 sim/testsuite/{sim => }/bfin/se_oneins_zoff.S | 0 sim/testsuite/{sim => }/bfin/se_popkill.S | 0 sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S | 0 sim/testsuite/{sim => }/bfin/se_rets_hazard.s | 0 sim/testsuite/{sim => }/bfin/se_rts_rti.S | 0 .../{sim => }/bfin/se_ssstep_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_ssync.S | 0 sim/testsuite/{sim => }/bfin/se_stall_if2.S | 0 .../{sim => }/bfin/se_undefinedinstruction1.S | 0 .../{sim => }/bfin/se_undefinedinstruction2.S | 0 .../{sim => }/bfin/se_undefinedinstruction3.S | 0 .../{sim => }/bfin/se_undefinedinstruction4.S | 0 .../{sim => }/bfin/se_usermode_protviol.S | 0 sim/testsuite/{sim => }/bfin/seqstat.s | 0 sim/testsuite/{sim => }/bfin/sign.s | 0 sim/testsuite/{sim => }/bfin/simple0.s | 0 sim/testsuite/{sim => }/bfin/sri.s | 0 sim/testsuite/{sim => }/bfin/stk.s | 0 sim/testsuite/{sim => }/bfin/stk2.s | 0 sim/testsuite/{sim => }/bfin/stk3.s | 0 sim/testsuite/{sim => }/bfin/stk4.s | 0 sim/testsuite/{sim => }/bfin/stk5.s | 0 sim/testsuite/{sim => }/bfin/stk6.s | 0 sim/testsuite/{sim => }/bfin/syscfg.s | 0 sim/testsuite/{sim => }/bfin/tar10622.s | 0 sim/testsuite/{sim => }/bfin/test-dma.h | 0 sim/testsuite/{sim => }/bfin/test.h | 0 sim/testsuite/{sim => }/bfin/testset.s | 0 sim/testsuite/{sim => }/bfin/testset2.s | 0 sim/testsuite/{sim => }/bfin/testutils.inc | 0 sim/testsuite/{sim => }/bfin/unlink.S | 0 sim/testsuite/{sim => }/bfin/up0.s | 0 sim/testsuite/{sim => }/bfin/usp.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-2.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-3.S | 0 sim/testsuite/{sim => }/bfin/vec-abs.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-2.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-3.S | 0 sim/testsuite/{sim => }/bfin/vec-neg.S | 0 sim/testsuite/{sim => }/bfin/vecadd.s | 0 sim/testsuite/{sim => }/bfin/vit_max.s | 0 sim/testsuite/{sim => }/bfin/vit_max2.s | 0 sim/testsuite/{sim => }/bfin/viterbi2.s | 0 sim/testsuite/{sim => }/bfin/wtf.s | 0 sim/testsuite/{sim => }/bfin/x1.s | 0 sim/testsuite/{sim => }/bfin/zcall.s | 0 sim/testsuite/{sim => }/bfin/zeroflagrnd.s | 0 sim/testsuite/bpf/ChangeLog | 24 + sim/testsuite/bpf/allinsn.exp | 30 + sim/testsuite/{sim => }/bpf/alu.s | 0 sim/testsuite/{sim => }/bpf/alu32.s | 0 sim/testsuite/{sim => }/bpf/endbe.s | 0 sim/testsuite/{sim => }/bpf/endle.s | 0 sim/testsuite/{sim => }/bpf/jmp.s | 0 sim/testsuite/{sim => }/bpf/jmp32.s | 0 sim/testsuite/{sim => }/bpf/ldabs.s | 0 sim/testsuite/{sim => }/bpf/mem.s | 0 sim/testsuite/{sim => }/bpf/mov.s | 0 sim/testsuite/{sim => }/bpf/testutils.inc | 0 sim/testsuite/{sim => }/bpf/xadd.s | 0 sim/testsuite/configure | 3264 ---- sim/testsuite/configure.ac | 32 - sim/testsuite/cr16/ChangeLog | 55 + sim/testsuite/{sim => }/cr16/addb.cgs | 0 sim/testsuite/{sim => }/cr16/addd.cgs | 0 sim/testsuite/{sim => }/cr16/addi.cgs | 0 sim/testsuite/{sim => }/cr16/addw.cgs | 0 sim/testsuite/cr16/allinsn.exp | 32 + sim/testsuite/{sim => }/cr16/andb.cgs | 0 sim/testsuite/{sim => }/cr16/andd.cgs | 0 sim/testsuite/{sim => }/cr16/andw.cgs | 0 sim/testsuite/{sim => }/cr16/ashub.cgs | 0 sim/testsuite/{sim => }/cr16/ashub_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashud.cgs | 0 sim/testsuite/{sim => }/cr16/ashud_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw_i.cgs | 0 sim/testsuite/{sim => }/cr16/bal1_24.cgs | 0 sim/testsuite/{sim => }/cr16/bal2_24.cgs | 0 sim/testsuite/{sim => }/cr16/bcc.cgs | 0 sim/testsuite/{sim => }/cr16/bcs.cgs | 0 sim/testsuite/{sim => }/cr16/beq.cgs | 0 sim/testsuite/{sim => }/cr16/beq0b.cgs | 0 sim/testsuite/{sim => }/cr16/beq0w.cgs | 0 sim/testsuite/{sim => }/cr16/bge.cgs | 0 sim/testsuite/{sim => }/cr16/bgt.cgs | 0 sim/testsuite/{sim => }/cr16/bhi.cgs | 0 sim/testsuite/{sim => }/cr16/bhs.cgs | 0 sim/testsuite/{sim => }/cr16/bht.cgs | 0 sim/testsuite/{sim => }/cr16/blo.cgs | 0 sim/testsuite/{sim => }/cr16/bls.cgs | 0 sim/testsuite/{sim => }/cr16/blt.cgs | 0 sim/testsuite/{sim => }/cr16/bne.cgs | 0 sim/testsuite/{sim => }/cr16/bne0b.cgs | 0 sim/testsuite/{sim => }/cr16/bne0w.cgs | 0 sim/testsuite/{sim => }/cr16/br.cgs | 0 sim/testsuite/{sim => }/cr16/cbitb.cgs | 0 sim/testsuite/{sim => }/cr16/cbitw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpi.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw_i.cgs | 0 sim/testsuite/{sim => }/cr16/excp.cgs | 0 sim/testsuite/{sim => }/cr16/hello.ms | 0 sim/testsuite/{sim => }/cr16/hw-trap.ms | 0 sim/testsuite/{sim => }/cr16/jal.cgs | 0 sim/testsuite/{sim => }/cr16/jcc.cgs | 0 sim/testsuite/{sim => }/cr16/jcs.cgs | 0 sim/testsuite/{sim => }/cr16/jeq.cgs | 0 sim/testsuite/{sim => }/cr16/jfc.cgs | 0 sim/testsuite/{sim => }/cr16/jfs.cgs | 0 sim/testsuite/{sim => }/cr16/jge.cgs | 0 sim/testsuite/{sim => }/cr16/jgt.cgs | 0 sim/testsuite/{sim => }/cr16/jhi.cgs | 0 sim/testsuite/{sim => }/cr16/jhs.cgs | 0 sim/testsuite/{sim => }/cr16/jlo.cgs | 0 sim/testsuite/{sim => }/cr16/jls.cgs | 0 sim/testsuite/{sim => }/cr16/jlt.cgs | 0 sim/testsuite/{sim => }/cr16/jne.cgs | 0 sim/testsuite/{sim => }/cr16/jump.cgs | 0 sim/testsuite/{sim => }/cr16/loadb.cgs | 0 sim/testsuite/{sim => }/cr16/loadd.cgs | 0 sim/testsuite/{sim => }/cr16/loadm.cgs | 0 sim/testsuite/{sim => }/cr16/loadmp.cgs | 0 sim/testsuite/{sim => }/cr16/loadw.cgs | 0 sim/testsuite/{sim => }/cr16/lpr-spr.cgs | 0 sim/testsuite/{sim => }/cr16/lprd-sprd.cgs | 0 sim/testsuite/{sim => }/cr16/lshb.cgs | 0 sim/testsuite/{sim => }/cr16/lshb_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshd.cgs | 0 sim/testsuite/{sim => }/cr16/lshd_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshw.cgs | 0 sim/testsuite/{sim => }/cr16/lshw_i.cgs | 0 sim/testsuite/{sim => }/cr16/macqw.cgs | 0 sim/testsuite/{sim => }/cr16/macsw.cgs | 0 sim/testsuite/{sim => }/cr16/macuw.cgs | 0 sim/testsuite/cr16/misc.exp | 32 + sim/testsuite/{sim => }/cr16/movb.cgs | 0 sim/testsuite/{sim => }/cr16/movd.cgs | 0 sim/testsuite/{sim => }/cr16/movw.cgs | 0 sim/testsuite/{sim => }/cr16/movxb.cgs | 0 sim/testsuite/{sim => }/cr16/movxw.cgs | 0 sim/testsuite/{sim => }/cr16/movzb.cgs | 0 sim/testsuite/{sim => }/cr16/movzw.cgs | 0 sim/testsuite/{sim => }/cr16/mulb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsw.cgs | 0 sim/testsuite/{sim => }/cr16/muluw.cgs | 0 sim/testsuite/{sim => }/cr16/mulw.cgs | 0 sim/testsuite/{sim => }/cr16/nop.cgs | 0 sim/testsuite/{sim => }/cr16/orb.cgs | 0 sim/testsuite/{sim => }/cr16/ord.cgs | 0 sim/testsuite/{sim => }/cr16/orw.cgs | 0 sim/testsuite/{sim => }/cr16/pop1.cgs | 0 sim/testsuite/{sim => }/cr16/pop2.cgs | 0 sim/testsuite/{sim => }/cr16/pop3.cgs | 0 sim/testsuite/{sim => }/cr16/popret1.cgs | 0 sim/testsuite/{sim => }/cr16/popret2.cgs | 0 sim/testsuite/{sim => }/cr16/popret3.cgs | 0 sim/testsuite/{sim => }/cr16/push1.cgs | 0 sim/testsuite/{sim => }/cr16/push2.cgs | 0 sim/testsuite/{sim => }/cr16/push3.cgs | 0 sim/testsuite/{sim => }/cr16/sbitb.cgs | 0 sim/testsuite/{sim => }/cr16/sbitw.cgs | 0 sim/testsuite/{sim => }/cr16/scc.cgs | 0 sim/testsuite/{sim => }/cr16/scs.cgs | 0 sim/testsuite/{sim => }/cr16/seq.cgs | 0 sim/testsuite/{sim => }/cr16/sfc.cgs | 0 sim/testsuite/{sim => }/cr16/sfs.cgs | 0 sim/testsuite/{sim => }/cr16/sge.cgs | 0 sim/testsuite/{sim => }/cr16/sgt.cgs | 0 sim/testsuite/{sim => }/cr16/shi.cgs | 0 sim/testsuite/{sim => }/cr16/shs.cgs | 0 sim/testsuite/{sim => }/cr16/slo.cgs | 0 sim/testsuite/{sim => }/cr16/sls.cgs | 0 sim/testsuite/{sim => }/cr16/slt.cgs | 0 sim/testsuite/{sim => }/cr16/sne.cgs | 0 sim/testsuite/{sim => }/cr16/storb.cgs | 0 sim/testsuite/{sim => }/cr16/stord.cgs | 0 sim/testsuite/{sim => }/cr16/storw.cgs | 0 sim/testsuite/{sim => }/cr16/subb.cgs | 0 sim/testsuite/{sim => }/cr16/subd.cgs | 0 sim/testsuite/{sim => }/cr16/subi.cgs | 0 sim/testsuite/{sim => }/cr16/subw.cgs | 0 sim/testsuite/{sim => }/cr16/tbit.cgs | 0 sim/testsuite/{sim => }/cr16/tbitb.cgs | 0 sim/testsuite/{sim => }/cr16/tbitw.cgs | 0 sim/testsuite/{sim => }/cr16/testutils.inc | 0 sim/testsuite/{sim => }/cr16/uread16.ms | 0 sim/testsuite/{sim => }/cr16/uread32.ms | 0 sim/testsuite/{sim => }/cr16/xorb.cgs | 0 sim/testsuite/{sim => }/cr16/xord.cgs | 0 sim/testsuite/{sim => }/cr16/xorw.cgs | 0 sim/testsuite/cris/ChangeLog | 208 + sim/testsuite/{sim => }/cris/asm/abs.ms | 0 sim/testsuite/{sim => }/cris/asm/addc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32c.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32m.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32r.ms | 0 sim/testsuite/{sim => }/cris/asm/addi.ms | 0 sim/testsuite/{sim => }/cris/asm/addiv32.ms | 0 sim/testsuite/{sim => }/cris/asm/addm.ms | 0 sim/testsuite/{sim => }/cris/asm/addoc.ms | 0 sim/testsuite/{sim => }/cris/asm/addom.ms | 0 sim/testsuite/{sim => }/cris/asm/addoq.ms | 0 sim/testsuite/{sim => }/cris/asm/addq.ms | 0 sim/testsuite/{sim => }/cris/asm/addqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addr.ms | 0 sim/testsuite/{sim => }/cris/asm/addswpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxm.ms | 0 sim/testsuite/{sim => }/cris/asm/addxr.ms | 0 sim/testsuite/{sim => }/cris/asm/andc.ms | 0 sim/testsuite/{sim => }/cris/asm/andm.ms | 0 sim/testsuite/{sim => }/cris/asm/andq.ms | 0 sim/testsuite/{sim => }/cris/asm/andr.ms | 0 sim/testsuite/cris/asm/asm.exp | 49 + sim/testsuite/{sim => }/cris/asm/asr.ms | 0 sim/testsuite/{sim => }/cris/asm/ba.ms | 0 sim/testsuite/{sim => }/cris/asm/badarch1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare2.ms | 0 sim/testsuite/{sim => }/cris/asm/bare3.ms | 0 sim/testsuite/{sim => }/cris/asm/bas.ms | 0 sim/testsuite/{sim => }/cris/asm/bccb.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapc.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapm.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapq.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/biap.ms | 0 sim/testsuite/{sim => }/cris/asm/boundc.ms | 0 sim/testsuite/{sim => }/cris/asm/boundm.ms | 0 sim/testsuite/{sim => }/cris/asm/boundmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/boundr.ms | 0 sim/testsuite/{sim => }/cris/asm/break.ms | 0 sim/testsuite/{sim => }/cris/asm/btst.ms | 0 sim/testsuite/{sim => }/cris/asm/ccr-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/ccs-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv10.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv32.ms | 0 sim/testsuite/{sim => }/cris/asm/clrjmp1.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpm.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpq.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpr.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxm.ms | 0 sim/testsuite/{sim => }/cris/asm/dflags.ms | 0 sim/testsuite/{sim => }/cris/asm/dip.ms | 0 sim/testsuite/{sim => }/cris/asm/dstep.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxd.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxi.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagd.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagi.ms | 0 sim/testsuite/{sim => }/cris/asm/halt.ms | 0 sim/testsuite/{sim => }/cris/asm/io1.ms | 0 sim/testsuite/{sim => }/cris/asm/io2.ms | 0 sim/testsuite/{sim => }/cris/asm/io3.ms | 0 sim/testsuite/{sim => }/cris/asm/io4.ms | 0 sim/testsuite/{sim => }/cris/asm/io5.ms | 0 sim/testsuite/{sim => }/cris/asm/io6.ms | 0 sim/testsuite/{sim => }/cris/asm/io7.ms | 0 sim/testsuite/{sim => }/cris/asm/io8.ms | 0 sim/testsuite/{sim => }/cris/asm/io9.ms | 0 sim/testsuite/{sim => }/cris/asm/jsr.ms | 0 sim/testsuite/{sim => }/cris/asm/jsrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/jumpmp.ms | 0 sim/testsuite/{sim => }/cris/asm/jumppv32.ms | 0 sim/testsuite/{sim => }/cris/asm/lapc.ms | 0 sim/testsuite/{sim => }/cris/asm/lsl.ms | 0 sim/testsuite/{sim => }/cris/asm/lsr.ms | 0 sim/testsuite/{sim => }/cris/asm/lz.ms | 0 sim/testsuite/{sim => }/cris/asm/mcp.ms | 0 sim/testsuite/{sim => }/cris/asm/movdelsr1.ms | 0 sim/testsuite/{sim => }/cris/asm/movecpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movecr.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt10.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt32.ms | 0 sim/testsuite/{sim => }/cris/asm/movect10.ms | 0 sim/testsuite/{sim => }/cris/asm/movei.ms | 0 sim/testsuite/{sim => }/cris/asm/movempc.ms | 0 sim/testsuite/{sim => }/cris/asm/movemr.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcb.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcd.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moveq.ms | 0 sim/testsuite/{sim => }/cris/asm/moveqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mover.ms | 0 sim/testsuite/{sim => }/cris/asm/moverbpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverdpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverm.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcb.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcd.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moverwpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movesmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp8.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movppc.ms | 0 sim/testsuite/{sim => }/cris/asm/movpr.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movrss.ms | 0 sim/testsuite/{sim => }/cris/asm/movscpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movscr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsm.ms | 0 sim/testsuite/{sim => }/cris/asm/movsmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movsr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsrpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movssr.ms | 0 sim/testsuite/{sim => }/cris/asm/movucpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movucr.ms | 0 sim/testsuite/{sim => }/cris/asm/movum.ms | 0 sim/testsuite/{sim => }/cris/asm/movumpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movur.ms | 0 sim/testsuite/{sim => }/cris/asm/movurpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mstep.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc1.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc2.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc3.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/mulx.ms | 0 sim/testsuite/{sim => }/cris/asm/neg.ms | 0 sim/testsuite/{sim => }/cris/asm/nonvcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv10t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t2.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t3.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t4.ms | 0 sim/testsuite/{sim => }/cris/asm/not.ms | 0 sim/testsuite/{sim => }/cris/asm/op3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr1.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr2.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr4.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr5.ms | 0 sim/testsuite/{sim => }/cris/asm/option1.ms | 0 sim/testsuite/{sim => }/cris/asm/option2.ms | 0 sim/testsuite/{sim => }/cris/asm/option3.ms | 0 sim/testsuite/{sim => }/cris/asm/option4.ms | 0 sim/testsuite/{sim => }/cris/asm/orc.ms | 0 sim/testsuite/{sim => }/cris/asm/orm.ms | 0 sim/testsuite/{sim => }/cris/asm/orq.ms | 0 sim/testsuite/{sim => }/cris/asm/orr.ms | 0 sim/testsuite/{sim => }/cris/asm/pcplus.ms | 0 sim/testsuite/{sim => }/cris/asm/pid1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw10.ms | 0 sim/testsuite/{sim => }/cris/asm/raw11.ms | 0 sim/testsuite/{sim => }/cris/asm/raw12.ms | 0 sim/testsuite/{sim => }/cris/asm/raw13.ms | 0 sim/testsuite/{sim => }/cris/asm/raw14.ms | 0 sim/testsuite/{sim => }/cris/asm/raw15.ms | 0 sim/testsuite/{sim => }/cris/asm/raw16.ms | 0 sim/testsuite/{sim => }/cris/asm/raw17.ms | 0 sim/testsuite/{sim => }/cris/asm/raw2.ms | 0 sim/testsuite/{sim => }/cris/asm/raw3.ms | 0 sim/testsuite/{sim => }/cris/asm/raw4.ms | 0 sim/testsuite/{sim => }/cris/asm/raw5.ms | 0 sim/testsuite/{sim => }/cris/asm/raw6.ms | 0 sim/testsuite/{sim => }/cris/asm/raw7.ms | 0 sim/testsuite/{sim => }/cris/asm/raw8.ms | 0 sim/testsuite/{sim => }/cris/asm/raw9.ms | 0 sim/testsuite/{sim => }/cris/asm/ret.ms | 0 sim/testsuite/{sim => }/cris/asm/rfe.ms | 0 sim/testsuite/{sim => }/cris/asm/rfg.ms | 0 sim/testsuite/{sim => }/cris/asm/rfn.ms | 0 sim/testsuite/{sim => }/cris/asm/sbfs.ms | 0 sim/testsuite/{sim => }/cris/asm/scc.ms | 0 sim/testsuite/{sim => }/cris/asm/sfe.ms | 0 sim/testsuite/{sim => }/cris/asm/subc.ms | 0 sim/testsuite/{sim => }/cris/asm/subm.ms | 0 sim/testsuite/{sim => }/cris/asm/subq.ms | 0 sim/testsuite/{sim => }/cris/asm/subqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/subr.ms | 0 sim/testsuite/{sim => }/cris/asm/subxc.ms | 0 sim/testsuite/{sim => }/cris/asm/subxm.ms | 0 sim/testsuite/{sim => }/cris/asm/subxr.ms | 0 sim/testsuite/{sim => }/cris/asm/swap.ms | 0 sim/testsuite/{sim => }/cris/asm/tb.ms | 0 sim/testsuite/{sim => }/cris/asm/test.ms | 0 sim/testsuite/{sim => }/cris/asm/testutils.inc | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm1.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm2.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/user.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x10-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x4-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x8-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x9-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/xor.ms | 0 sim/testsuite/{sim => }/cris/c/access1.c | 0 sim/testsuite/{sim => }/cris/c/append1.c | 0 sim/testsuite/{sim => }/cris/c/badldso1.c | 0 sim/testsuite/{sim => }/cris/c/badldso2.c | 0 sim/testsuite/{sim => }/cris/c/badldso3.c | 0 sim/testsuite/cris/c/c.exp | 257 + sim/testsuite/{sim => }/cris/c/clone1.c | 0 sim/testsuite/{sim => }/cris/c/clone2.c | 0 sim/testsuite/{sim => }/cris/c/clone3.c | 0 sim/testsuite/{sim => }/cris/c/clone4.c | 0 sim/testsuite/{sim => }/cris/c/clone5.c | 0 sim/testsuite/{sim => }/cris/c/clone6.c | 0 sim/testsuite/{sim => }/cris/c/ex1.c | 0 sim/testsuite/{sim => }/cris/c/exitg1.c | 0 sim/testsuite/{sim => }/cris/c/exitg2.c | 0 sim/testsuite/{sim => }/cris/c/fcntl1.c | 0 sim/testsuite/{sim => }/cris/c/fcntl2.c | 0 sim/testsuite/{sim => }/cris/c/fdopen1.c | 0 sim/testsuite/{sim => }/cris/c/fdopen2.c | 0 sim/testsuite/{sim => }/cris/c/freopen1.c | 0 sim/testsuite/{sim => }/cris/c/freopen2.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate1.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate2.c | 0 sim/testsuite/{sim => }/cris/c/getcwd1.c | 0 sim/testsuite/{sim => }/cris/c/gettod.c | 0 sim/testsuite/{sim => }/cris/c/hello.c | 0 sim/testsuite/{sim => }/cris/c/helloaout.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn2.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn3.c | 0 sim/testsuite/{sim => }/cris/c/kill1.c | 0 sim/testsuite/{sim => }/cris/c/kill2.c | 0 sim/testsuite/{sim => }/cris/c/kill3.c | 0 sim/testsuite/{sim => }/cris/c/mapbrk.c | 0 sim/testsuite/{sim => }/cris/c/mmap1.c | 0 sim/testsuite/{sim => }/cris/c/mmap2.c | 0 sim/testsuite/{sim => }/cris/c/mmap3.c | 0 sim/testsuite/{sim => }/cris/c/mmap4.c | 0 sim/testsuite/{sim => }/cris/c/mmap5.c | 0 sim/testsuite/{sim => }/cris/c/mmap6.c | 0 sim/testsuite/{sim => }/cris/c/mmap7.c | 0 sim/testsuite/{sim => }/cris/c/mmap8.c | 0 sim/testsuite/{sim => }/cris/c/mprotect1.c | 0 sim/testsuite/{sim => }/cris/c/mprotect2.c | 0 sim/testsuite/{sim => }/cris/c/mremap.c | 0 sim/testsuite/{sim => }/cris/c/openpf1.c | 0 sim/testsuite/{sim => }/cris/c/openpf2.c | 0 sim/testsuite/{sim => }/cris/c/openpf3.c | 0 sim/testsuite/{sim => }/cris/c/openpf4.c | 0 sim/testsuite/{sim => }/cris/c/openpf5.c | 0 sim/testsuite/{sim => }/cris/c/pipe1.c | 0 sim/testsuite/{sim => }/cris/c/pipe2.c | 0 sim/testsuite/{sim => }/cris/c/pipe3.c | 0 sim/testsuite/{sim => }/cris/c/pipe4.c | 0 sim/testsuite/{sim => }/cris/c/pipe5.c | 0 sim/testsuite/{sim => }/cris/c/pipe6.c | 0 sim/testsuite/{sim => }/cris/c/pipe7.c | 0 sim/testsuite/{sim => }/cris/c/readlink1.c | 0 sim/testsuite/{sim => }/cris/c/readlink10.c | 0 sim/testsuite/{sim => }/cris/c/readlink11.c | 0 sim/testsuite/{sim => }/cris/c/readlink2.c | 0 sim/testsuite/{sim => }/cris/c/readlink3.c | 0 sim/testsuite/{sim => }/cris/c/readlink4.c | 0 sim/testsuite/{sim => }/cris/c/readlink5.c | 0 sim/testsuite/{sim => }/cris/c/readlink6.c | 0 sim/testsuite/{sim => }/cris/c/readlink7.c | 0 sim/testsuite/{sim => }/cris/c/readlink8.c | 0 sim/testsuite/{sim => }/cris/c/readlink9.c | 0 sim/testsuite/{sim => }/cris/c/rename2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c | 0 sim/testsuite/{sim => }/cris/c/sched1.c | 0 sim/testsuite/{sim => }/cris/c/sched2.c | 0 sim/testsuite/{sim => }/cris/c/sched3.c | 0 sim/testsuite/{sim => }/cris/c/sched4.c | 0 sim/testsuite/{sim => }/cris/c/sched5.c | 0 sim/testsuite/{sim => }/cris/c/sched6.c | 0 sim/testsuite/{sim => }/cris/c/sched7.c | 0 sim/testsuite/{sim => }/cris/c/sched8.c | 0 sim/testsuite/{sim => }/cris/c/sched9.c | 0 sim/testsuite/{sim => }/cris/c/seek1.c | 0 sim/testsuite/{sim => }/cris/c/seek2.c | 0 sim/testsuite/{sim => }/cris/c/seek3.c | 0 sim/testsuite/{sim => }/cris/c/seek4.c | 0 sim/testsuite/{sim => }/cris/c/setrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/settls1.c | 0 sim/testsuite/{sim => }/cris/c/sig1.c | 0 sim/testsuite/{sim => }/cris/c/sig10.c | 0 sim/testsuite/{sim => }/cris/c/sig11.c | 0 sim/testsuite/{sim => }/cris/c/sig12.c | 0 sim/testsuite/{sim => }/cris/c/sig13.c | 0 sim/testsuite/{sim => }/cris/c/sig2.c | 0 sim/testsuite/{sim => }/cris/c/sig3.c | 0 sim/testsuite/{sim => }/cris/c/sig4.c | 0 sim/testsuite/{sim => }/cris/c/sig5.c | 0 sim/testsuite/{sim => }/cris/c/sig6.c | 0 sim/testsuite/{sim => }/cris/c/sig7.c | 0 sim/testsuite/{sim => }/cris/c/sig8.c | 0 sim/testsuite/{sim => }/cris/c/sig9.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn1.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn2.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn3.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn4.c | 0 sim/testsuite/{sim => }/cris/c/sjlj.c | 0 sim/testsuite/{sim => }/cris/c/sock1.c | 0 sim/testsuite/{sim => }/cris/c/stat1.c | 0 sim/testsuite/{sim => }/cris/c/stat2.c | 0 sim/testsuite/{sim => }/cris/c/stat3.c | 0 sim/testsuite/{sim => }/cris/c/stat4.c | 0 sim/testsuite/{sim => }/cris/c/stat5.c | 0 sim/testsuite/{sim => }/cris/c/stat7.c | 0 sim/testsuite/{sim => }/cris/c/stat8.c | 0 sim/testsuite/{sim => }/cris/c/syscall1.c | 0 sim/testsuite/{sim => }/cris/c/syscall2.c | 0 sim/testsuite/{sim => }/cris/c/syscall3.c | 0 sim/testsuite/{sim => }/cris/c/syscall4.c | 0 sim/testsuite/{sim => }/cris/c/syscall5.c | 0 sim/testsuite/{sim => }/cris/c/syscall6.c | 0 sim/testsuite/{sim => }/cris/c/syscall7.c | 0 sim/testsuite/{sim => }/cris/c/syscall8.c | 0 sim/testsuite/{sim => }/cris/c/sysctl1.c | 0 sim/testsuite/{sim => }/cris/c/sysctl2.c | 0 sim/testsuite/{sim => }/cris/c/sysctl3.c | 0 sim/testsuite/{sim => }/cris/c/thread2.c | 0 sim/testsuite/{sim => }/cris/c/thread3.c | 0 sim/testsuite/{sim => }/cris/c/thread4.c | 0 sim/testsuite/{sim => }/cris/c/thread5.c | 0 sim/testsuite/{sim => }/cris/c/time1.c | 0 sim/testsuite/{sim => }/cris/c/time2.c | 0 sim/testsuite/{sim => }/cris/c/truncate1.c | 0 sim/testsuite/{sim => }/cris/c/truncate2.c | 0 sim/testsuite/{sim => }/cris/c/ugetrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/uname1.c | 0 sim/testsuite/{sim => }/cris/c/writev1.c | 0 sim/testsuite/{sim => }/cris/c/writev2.c | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s | 0 sim/testsuite/cris/hw/rv-n-cris/rvc.exp | 253 + sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev | 0 .../{sim => }/cris/hw/rv-n-cris/testutils.inc | 0 .../{sim => }/cris/hw/rv-n-cris/trivial1.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial2.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial3.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.r | 0 .../{sim => }/cris/hw/rv-n-cris/trivial5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms | 0 sim/testsuite/d10v-elf/ChangeLog | 139 - sim/testsuite/d10v-elf/Makefile.in | 180 - sim/testsuite/d10v-elf/configure | 2984 ---- sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/hello.s | 5 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/d10v-elf/t-ae-ld-d.s | 13 - sim/testsuite/d10v-elf/t-ae-ld-i.s | 16 - sim/testsuite/d10v-elf/t-ae-ld-id.s | 15 - sim/testsuite/d10v-elf/t-ae-ld-im.s | 16 - sim/testsuite/d10v-elf/t-ae-ld-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-ld2w-d.s | 13 - sim/testsuite/d10v-elf/t-ae-ld2w-i.s | 16 - sim/testsuite/d10v-elf/t-ae-ld2w-id.s | 14 - sim/testsuite/d10v-elf/t-ae-ld2w-im.s | 16 - sim/testsuite/d10v-elf/t-ae-ld2w-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-st-d.s | 13 - sim/testsuite/d10v-elf/t-ae-st-i.s | 16 - sim/testsuite/d10v-elf/t-ae-st-id.s | 14 - sim/testsuite/d10v-elf/t-ae-st-im.s | 16 - sim/testsuite/d10v-elf/t-ae-st-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-st-is.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-d.s | 13 - sim/testsuite/d10v-elf/t-ae-st2w-i.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-id.s | 14 - sim/testsuite/d10v-elf/t-ae-st2w-im.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-is.s | 16 - sim/testsuite/d10v-elf/t-dbt.s | 33 - sim/testsuite/d10v-elf/t-ld-st.s | 32 - sim/testsuite/d10v-elf/t-mac.s | 71 - sim/testsuite/d10v-elf/t-macros.i | 233 - sim/testsuite/d10v-elf/t-mod-ld-pre.s | 126 - sim/testsuite/d10v-elf/t-msbu.s | 28 - sim/testsuite/d10v-elf/t-mulxu.s | 28 - sim/testsuite/d10v-elf/t-mvtac.s | 19 - sim/testsuite/d10v-elf/t-mvtc.s | 129 - sim/testsuite/d10v-elf/t-rac.s | 16 - sim/testsuite/d10v-elf/t-rachi.s | 28 - sim/testsuite/d10v-elf/t-rdt.s | 18 - sim/testsuite/d10v-elf/t-rep.s | 45 - sim/testsuite/d10v-elf/t-rie-xx.s | 12 - sim/testsuite/d10v-elf/t-rte.s | 18 - sim/testsuite/d10v-elf/t-sac.s | 23 - sim/testsuite/d10v-elf/t-sachi.s | 22 - sim/testsuite/d10v-elf/t-sadd.s | 38 - sim/testsuite/d10v-elf/t-slae.s | 39 - sim/testsuite/d10v-elf/t-sp.s | 17 - sim/testsuite/d10v-elf/t-sub.s | 42 - sim/testsuite/d10v-elf/t-sub2w.s | 57 - sim/testsuite/d10v-elf/t-subi.s | 39 - sim/testsuite/d10v-elf/t-trap.s | 5 - sim/testsuite/d10v/ChangeLog | 147 + sim/testsuite/d10v/allinsn.exp | 19 + sim/testsuite/d10v/exit47.s | 8 + sim/testsuite/d10v/hello.s | 8 + sim/testsuite/d10v/t-ae-ld-d.s | 17 + sim/testsuite/d10v/t-ae-ld-i.s | 20 + sim/testsuite/d10v/t-ae-ld-id.s | 19 + sim/testsuite/d10v/t-ae-ld-im.s | 20 + sim/testsuite/d10v/t-ae-ld-ip.s | 20 + sim/testsuite/d10v/t-ae-ld2w-d.s | 17 + sim/testsuite/d10v/t-ae-ld2w-i.s | 20 + sim/testsuite/d10v/t-ae-ld2w-id.s | 18 + sim/testsuite/d10v/t-ae-ld2w-im.s | 20 + sim/testsuite/d10v/t-ae-ld2w-ip.s | 20 + sim/testsuite/d10v/t-ae-st-d.s | 17 + sim/testsuite/d10v/t-ae-st-i.s | 20 + sim/testsuite/d10v/t-ae-st-id.s | 18 + sim/testsuite/d10v/t-ae-st-im.s | 20 + sim/testsuite/d10v/t-ae-st-ip.s | 20 + sim/testsuite/d10v/t-ae-st-is.s | 20 + sim/testsuite/d10v/t-ae-st2w-d.s | 17 + sim/testsuite/d10v/t-ae-st2w-i.s | 20 + sim/testsuite/d10v/t-ae-st2w-id.s | 18 + sim/testsuite/d10v/t-ae-st2w-im.s | 20 + sim/testsuite/d10v/t-ae-st2w-ip.s | 20 + sim/testsuite/d10v/t-ae-st2w-is.s | 20 + sim/testsuite/d10v/t-dbt.s | 38 + sim/testsuite/d10v/t-ld-st.s | 36 + sim/testsuite/d10v/t-mac.s | 75 + sim/testsuite/d10v/t-macros.i | 235 + sim/testsuite/d10v/t-mod-ld-pre.s | 126 + sim/testsuite/d10v/t-msbu.s | 32 + sim/testsuite/d10v/t-mulxu.s | 32 + sim/testsuite/d10v/t-mvtac.s | 23 + sim/testsuite/d10v/t-mvtc.s | 134 + sim/testsuite/d10v/t-rac.s | 20 + sim/testsuite/d10v/t-rachi.s | 32 + sim/testsuite/d10v/t-rdt.s | 23 + sim/testsuite/d10v/t-rep.s | 49 + sim/testsuite/d10v/t-rie-xx.s | 16 + sim/testsuite/d10v/t-rte.s | 22 + sim/testsuite/d10v/t-sac.s | 27 + sim/testsuite/d10v/t-sachi.s | 26 + sim/testsuite/d10v/t-sadd.s | 42 + sim/testsuite/d10v/t-slae.s | 43 + sim/testsuite/d10v/t-sp.s | 21 + sim/testsuite/d10v/t-sub.s | 46 + sim/testsuite/d10v/t-sub2w.s | 61 + sim/testsuite/d10v/t-subi.s | 43 + sim/testsuite/d10v/t-trap.s | 10 + sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/cache.s | 164 - sim/testsuite/frv-elf/configure | 2984 ---- sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/exit47.s | 5 - sim/testsuite/frv-elf/grloop.s | 10 - sim/testsuite/frv-elf/hello.s | 16 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/frv/ChangeLog | 88 + sim/testsuite/{sim => }/frv/add.cgs | 0 sim/testsuite/{sim => }/frv/add.pcgs | 0 sim/testsuite/{sim => }/frv/addcc.cgs | 0 sim/testsuite/{sim => }/frv/addi.cgs | 0 sim/testsuite/{sim => }/frv/addicc.cgs | 0 sim/testsuite/{sim => }/frv/addx.cgs | 0 sim/testsuite/{sim => }/frv/addxcc.cgs | 0 sim/testsuite/{sim => }/frv/addxi.cgs | 0 sim/testsuite/{sim => }/frv/addxicc.cgs | 0 sim/testsuite/frv/allinsn.exp | 21 + sim/testsuite/{sim => }/frv/and.cgs | 0 sim/testsuite/{sim => }/frv/andcc.cgs | 0 sim/testsuite/{sim => }/frv/andcr.cgs | 0 sim/testsuite/{sim => }/frv/andi.cgs | 0 sim/testsuite/{sim => }/frv/andicc.cgs | 0 sim/testsuite/{sim => }/frv/andncr.cgs | 0 sim/testsuite/{sim => }/frv/bar.cgs | 0 sim/testsuite/{sim => }/frv/bc.cgs | 0 sim/testsuite/{sim => }/frv/bcclr.cgs | 0 sim/testsuite/{sim => }/frv/bceqlr.cgs | 0 sim/testsuite/{sim => }/frv/bcgelr.cgs | 0 sim/testsuite/{sim => }/frv/bcgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bchilr.cgs | 0 sim/testsuite/{sim => }/frv/bclelr.cgs | 0 sim/testsuite/{sim => }/frv/bclr.cgs | 0 sim/testsuite/{sim => }/frv/bclslr.cgs | 0 sim/testsuite/{sim => }/frv/bcltlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnclr.cgs | 0 sim/testsuite/{sim => }/frv/bcnelr.cgs | 0 sim/testsuite/{sim => }/frv/bcnlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnolr.cgs | 0 sim/testsuite/{sim => }/frv/bcnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bcplr.cgs | 0 sim/testsuite/{sim => }/frv/bcralr.cgs | 0 sim/testsuite/{sim => }/frv/bctrlr.cgs | 0 sim/testsuite/{sim => }/frv/bcvlr.cgs | 0 sim/testsuite/{sim => }/frv/beq.cgs | 0 sim/testsuite/{sim => }/frv/beqlr.cgs | 0 sim/testsuite/{sim => }/frv/bge.cgs | 0 sim/testsuite/{sim => }/frv/bgelr.cgs | 0 sim/testsuite/{sim => }/frv/bgt.cgs | 0 sim/testsuite/{sim => }/frv/bgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bhi.cgs | 0 sim/testsuite/{sim => }/frv/bhilr.cgs | 0 sim/testsuite/{sim => }/frv/ble.cgs | 0 sim/testsuite/{sim => }/frv/blelr.cgs | 0 sim/testsuite/{sim => }/frv/bls.cgs | 0 sim/testsuite/{sim => }/frv/blslr.cgs | 0 sim/testsuite/{sim => }/frv/blt.cgs | 0 sim/testsuite/{sim => }/frv/bltlr.cgs | 0 sim/testsuite/{sim => }/frv/bn.cgs | 0 sim/testsuite/{sim => }/frv/bnc.cgs | 0 sim/testsuite/{sim => }/frv/bnclr.cgs | 0 sim/testsuite/{sim => }/frv/bne.cgs | 0 sim/testsuite/{sim => }/frv/bnelr.cgs | 0 sim/testsuite/{sim => }/frv/bnlr.cgs | 0 sim/testsuite/{sim => }/frv/bno.cgs | 0 sim/testsuite/{sim => }/frv/bnolr.cgs | 0 sim/testsuite/{sim => }/frv/bnv.cgs | 0 sim/testsuite/{sim => }/frv/bnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bp.cgs | 0 sim/testsuite/{sim => }/frv/bplr.cgs | 0 sim/testsuite/{sim => }/frv/bra.cgs | 0 sim/testsuite/{sim => }/frv/bralr.cgs | 0 sim/testsuite/{sim => }/frv/branch.pcgs | 0 sim/testsuite/{sim => }/frv/break.cgs | 0 sim/testsuite/{sim => }/frv/bv.cgs | 0 sim/testsuite/{sim => }/frv/bvlr.cgs | 0 sim/testsuite/frv/cache.ms | 168 + sim/testsuite/{sim => }/frv/cadd.cgs | 0 sim/testsuite/{sim => }/frv/caddcc.cgs | 0 sim/testsuite/{sim => }/frv/call.cgs | 0 sim/testsuite/{sim => }/frv/call.pcgs | 0 sim/testsuite/{sim => }/frv/callil.cgs | 0 sim/testsuite/{sim => }/frv/calll.cgs | 0 sim/testsuite/{sim => }/frv/cand.cgs | 0 sim/testsuite/{sim => }/frv/candcc.cgs | 0 sim/testsuite/{sim => }/frv/ccalll.cgs | 0 sim/testsuite/{sim => }/frv/cckc.cgs | 0 sim/testsuite/{sim => }/frv/cckeq.cgs | 0 sim/testsuite/{sim => }/frv/cckge.cgs | 0 sim/testsuite/{sim => }/frv/cckgt.cgs | 0 sim/testsuite/{sim => }/frv/cckhi.cgs | 0 sim/testsuite/{sim => }/frv/cckle.cgs | 0 sim/testsuite/{sim => }/frv/cckls.cgs | 0 sim/testsuite/{sim => }/frv/ccklt.cgs | 0 sim/testsuite/{sim => }/frv/cckn.cgs | 0 sim/testsuite/{sim => }/frv/ccknc.cgs | 0 sim/testsuite/{sim => }/frv/cckne.cgs | 0 sim/testsuite/{sim => }/frv/cckno.cgs | 0 sim/testsuite/{sim => }/frv/ccknv.cgs | 0 sim/testsuite/{sim => }/frv/cckp.cgs | 0 sim/testsuite/{sim => }/frv/cckra.cgs | 0 sim/testsuite/{sim => }/frv/cckv.cgs | 0 sim/testsuite/{sim => }/frv/ccmp.cgs | 0 sim/testsuite/{sim => }/frv/cfabss.cgs | 0 sim/testsuite/{sim => }/frv/cfadds.cgs | 0 sim/testsuite/{sim => }/frv/cfckeq.cgs | 0 sim/testsuite/{sim => }/frv/cfckge.cgs | 0 sim/testsuite/{sim => }/frv/cfckgt.cgs | 0 sim/testsuite/{sim => }/frv/cfckle.cgs | 0 sim/testsuite/{sim => }/frv/cfcklg.cgs | 0 sim/testsuite/{sim => }/frv/cfcklt.cgs | 0 sim/testsuite/{sim => }/frv/cfckne.cgs | 0 sim/testsuite/{sim => }/frv/cfckno.cgs | 0 sim/testsuite/{sim => }/frv/cfcko.cgs | 0 sim/testsuite/{sim => }/frv/cfckra.cgs | 0 sim/testsuite/{sim => }/frv/cfcku.cgs | 0 sim/testsuite/{sim => }/frv/cfckue.cgs | 0 sim/testsuite/{sim => }/frv/cfckug.cgs | 0 sim/testsuite/{sim => }/frv/cfckuge.cgs | 0 sim/testsuite/{sim => }/frv/cfckul.cgs | 0 sim/testsuite/{sim => }/frv/cfckule.cgs | 0 sim/testsuite/{sim => }/frv/cfcmps.cgs | 0 sim/testsuite/{sim => }/frv/cfdivs.cgs | 0 sim/testsuite/{sim => }/frv/cfitos.cgs | 0 sim/testsuite/{sim => }/frv/cfmadds.cgs | 0 sim/testsuite/{sim => }/frv/cfmas.cgs | 0 sim/testsuite/{sim => }/frv/cfmovs.cgs | 0 sim/testsuite/{sim => }/frv/cfmss.cgs | 0 sim/testsuite/{sim => }/frv/cfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/cfmuls.cgs | 0 sim/testsuite/{sim => }/frv/cfnegs.cgs | 0 sim/testsuite/{sim => }/frv/cfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/cfstoi.cgs | 0 sim/testsuite/{sim => }/frv/cfsubs.cgs | 0 sim/testsuite/{sim => }/frv/cjmpl.cgs | 0 sim/testsuite/{sim => }/frv/ckc.cgs | 0 sim/testsuite/{sim => }/frv/ckeq.cgs | 0 sim/testsuite/{sim => }/frv/ckge.cgs | 0 sim/testsuite/{sim => }/frv/ckgt.cgs | 0 sim/testsuite/{sim => }/frv/ckhi.cgs | 0 sim/testsuite/{sim => }/frv/ckle.cgs | 0 sim/testsuite/{sim => }/frv/ckls.cgs | 0 sim/testsuite/{sim => }/frv/cklt.cgs | 0 sim/testsuite/{sim => }/frv/ckn.cgs | 0 sim/testsuite/{sim => }/frv/cknc.cgs | 0 sim/testsuite/{sim => }/frv/ckne.cgs | 0 sim/testsuite/{sim => }/frv/ckno.cgs | 0 sim/testsuite/{sim => }/frv/cknv.cgs | 0 sim/testsuite/{sim => }/frv/ckp.cgs | 0 sim/testsuite/{sim => }/frv/ckra.cgs | 0 sim/testsuite/{sim => }/frv/ckv.cgs | 0 sim/testsuite/{sim => }/frv/cld.cgs | 0 sim/testsuite/{sim => }/frv/cldbf.cgs | 0 sim/testsuite/{sim => }/frv/cldbfu.cgs | 0 sim/testsuite/{sim => }/frv/cldd.cgs | 0 sim/testsuite/{sim => }/frv/clddf.cgs | 0 sim/testsuite/{sim => }/frv/clddfu.cgs | 0 sim/testsuite/{sim => }/frv/clddu.cgs | 0 sim/testsuite/{sim => }/frv/cldf.cgs | 0 sim/testsuite/{sim => }/frv/cldfu.cgs | 0 sim/testsuite/{sim => }/frv/cldhf.cgs | 0 sim/testsuite/{sim => }/frv/cldhfu.cgs | 0 sim/testsuite/{sim => }/frv/cldq.cgs | 0 sim/testsuite/{sim => }/frv/cldqu.cgs | 0 sim/testsuite/{sim => }/frv/cldsb.cgs | 0 sim/testsuite/{sim => }/frv/cldsbu.cgs | 0 sim/testsuite/{sim => }/frv/cldsh.cgs | 0 sim/testsuite/{sim => }/frv/cldshu.cgs | 0 sim/testsuite/{sim => }/frv/cldu.cgs | 0 sim/testsuite/{sim => }/frv/cldub.cgs | 0 sim/testsuite/{sim => }/frv/cldubu.cgs | 0 sim/testsuite/{sim => }/frv/clduh.cgs | 0 sim/testsuite/{sim => }/frv/clduhu.cgs | 0 sim/testsuite/{sim => }/frv/clrfa.cgs | 0 sim/testsuite/{sim => }/frv/clrfr.cgs | 0 sim/testsuite/{sim => }/frv/clrga.cgs | 0 sim/testsuite/{sim => }/frv/clrgr.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/cmand.cgs | 0 sim/testsuite/{sim => }/frv/cmbtoh.cgs | 0 sim/testsuite/{sim => }/frv/cmbtohe.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxis.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/cmhtob.cgs | 0 sim/testsuite/{sim => }/frv/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmnot.cgs | 0 sim/testsuite/{sim => }/frv/cmor.cgs | 0 sim/testsuite/{sim => }/frv/cmov.cgs | 0 sim/testsuite/{sim => }/frv/cmovfg.cgs | 0 sim/testsuite/{sim => }/frv/cmovfgd.cgs | 0 sim/testsuite/{sim => }/frv/cmovgf.cgs | 0 sim/testsuite/{sim => }/frv/cmovgfd.cgs | 0 sim/testsuite/{sim => }/frv/cmp.cgs | 0 sim/testsuite/{sim => }/frv/cmpb.cgs | 0 sim/testsuite/{sim => }/frv/cmpba.cgs | 0 sim/testsuite/{sim => }/frv/cmpi.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/cmxor.cgs | 0 sim/testsuite/{sim => }/frv/cnot.cgs | 0 sim/testsuite/{sim => }/frv/commitfa.cgs | 0 sim/testsuite/{sim => }/frv/commitfr.cgs | 0 sim/testsuite/{sim => }/frv/commitga.cgs | 0 sim/testsuite/{sim => }/frv/commitgr.cgs | 0 sim/testsuite/{sim => }/frv/cop1.cgs | 0 sim/testsuite/{sim => }/frv/cop2.cgs | 0 sim/testsuite/{sim => }/frv/cor.cgs | 0 sim/testsuite/{sim => }/frv/corcc.cgs | 0 sim/testsuite/{sim => }/frv/cscan.cgs | 0 sim/testsuite/{sim => }/frv/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/csll.cgs | 0 sim/testsuite/{sim => }/frv/csllcc.cgs | 0 sim/testsuite/{sim => }/frv/csmul.cgs | 0 sim/testsuite/{sim => }/frv/csmulcc.cgs | 0 sim/testsuite/{sim => }/frv/csra.cgs | 0 sim/testsuite/{sim => }/frv/csracc.cgs | 0 sim/testsuite/{sim => }/frv/csrl.cgs | 0 sim/testsuite/{sim => }/frv/csrlcc.cgs | 0 sim/testsuite/{sim => }/frv/cst.cgs | 0 sim/testsuite/{sim => }/frv/cstb.cgs | 0 sim/testsuite/{sim => }/frv/cstbf.cgs | 0 sim/testsuite/{sim => }/frv/cstbfu.cgs | 0 sim/testsuite/{sim => }/frv/cstbu.cgs | 0 sim/testsuite/{sim => }/frv/cstd.cgs | 0 sim/testsuite/{sim => }/frv/cstdf.cgs | 0 sim/testsuite/{sim => }/frv/cstdfu.cgs | 0 sim/testsuite/{sim => }/frv/cstdu.cgs | 0 sim/testsuite/{sim => }/frv/cstf.cgs | 0 sim/testsuite/{sim => }/frv/cstfu.cgs | 0 sim/testsuite/{sim => }/frv/csth.cgs | 0 sim/testsuite/{sim => }/frv/csthf.cgs | 0 sim/testsuite/{sim => }/frv/csthfu.cgs | 0 sim/testsuite/{sim => }/frv/csthu.cgs | 0 sim/testsuite/{sim => }/frv/cstq.cgs | 0 sim/testsuite/{sim => }/frv/cstu.cgs | 0 sim/testsuite/{sim => }/frv/csub.cgs | 0 sim/testsuite/{sim => }/frv/csubcc.cgs | 0 sim/testsuite/{sim => }/frv/cswap.cgs | 0 sim/testsuite/{sim => }/frv/cudiv.cgs | 0 sim/testsuite/{sim => }/frv/cxor.cgs | 0 sim/testsuite/{sim => }/frv/cxorcc.cgs | 0 sim/testsuite/{sim => }/frv/dcef.cgs | 0 sim/testsuite/{sim => }/frv/dcei.cgs | 0 sim/testsuite/{sim => }/frv/dcf.cgs | 0 sim/testsuite/{sim => }/frv/dci.cgs | 0 sim/testsuite/frv/exit47.ms | 11 + sim/testsuite/{sim => }/frv/fabsd.cgs | 0 sim/testsuite/{sim => }/frv/fabss.cgs | 0 sim/testsuite/{sim => }/frv/faddd.cgs | 0 sim/testsuite/{sim => }/frv/fadds.cgs | 0 sim/testsuite/{sim => }/frv/fbeq.cgs | 0 sim/testsuite/{sim => }/frv/fbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fbge.cgs | 0 sim/testsuite/{sim => }/frv/fbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fbgt.cgs | 0 sim/testsuite/{sim => }/frv/fbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fble.cgs | 0 sim/testsuite/{sim => }/frv/fblelr.cgs | 0 sim/testsuite/{sim => }/frv/fblg.cgs | 0 sim/testsuite/{sim => }/frv/fblglr.cgs | 0 sim/testsuite/{sim => }/frv/fblt.cgs | 0 sim/testsuite/{sim => }/frv/fbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fbne.cgs | 0 sim/testsuite/{sim => }/frv/fbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fbno.cgs | 0 sim/testsuite/{sim => }/frv/fbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fbo.cgs | 0 sim/testsuite/{sim => }/frv/fbolr.cgs | 0 sim/testsuite/{sim => }/frv/fbra.cgs | 0 sim/testsuite/{sim => }/frv/fbralr.cgs | 0 sim/testsuite/{sim => }/frv/fbu.cgs | 0 sim/testsuite/{sim => }/frv/fbue.cgs | 0 sim/testsuite/{sim => }/frv/fbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fbug.cgs | 0 sim/testsuite/{sim => }/frv/fbuge.cgs | 0 sim/testsuite/{sim => }/frv/fbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fbul.cgs | 0 sim/testsuite/{sim => }/frv/fbule.cgs | 0 sim/testsuite/{sim => }/frv/fbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fbullr.cgs | 0 sim/testsuite/{sim => }/frv/fbulr.cgs | 0 sim/testsuite/{sim => }/frv/fcbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fcblelr.cgs | 0 sim/testsuite/{sim => }/frv/fcblglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbralr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbullr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulr.cgs | 0 sim/testsuite/{sim => }/frv/fckeq.cgs | 0 sim/testsuite/{sim => }/frv/fckge.cgs | 0 sim/testsuite/{sim => }/frv/fckgt.cgs | 0 sim/testsuite/{sim => }/frv/fckle.cgs | 0 sim/testsuite/{sim => }/frv/fcklg.cgs | 0 sim/testsuite/{sim => }/frv/fcklt.cgs | 0 sim/testsuite/{sim => }/frv/fckne.cgs | 0 sim/testsuite/{sim => }/frv/fckno.cgs | 0 sim/testsuite/{sim => }/frv/fcko.cgs | 0 sim/testsuite/{sim => }/frv/fckra.cgs | 0 sim/testsuite/{sim => }/frv/fcku.cgs | 0 sim/testsuite/{sim => }/frv/fckue.cgs | 0 sim/testsuite/{sim => }/frv/fckug.cgs | 0 sim/testsuite/{sim => }/frv/fckuge.cgs | 0 sim/testsuite/{sim => }/frv/fckul.cgs | 0 sim/testsuite/{sim => }/frv/fckule.cgs | 0 sim/testsuite/{sim => }/frv/fcmpd.cgs | 0 sim/testsuite/{sim => }/frv/fcmps.cgs | 0 sim/testsuite/{sim => }/frv/fdabss.cgs | 0 sim/testsuite/{sim => }/frv/fdadds.cgs | 0 sim/testsuite/{sim => }/frv/fdcmps.cgs | 0 sim/testsuite/{sim => }/frv/fddivs.cgs | 0 sim/testsuite/{sim => }/frv/fditos.cgs | 0 sim/testsuite/{sim => }/frv/fdivd.cgs | 0 sim/testsuite/{sim => }/frv/fdivs.cgs | 0 sim/testsuite/{sim => }/frv/fdmadds.cgs | 0 sim/testsuite/{sim => }/frv/fdmas.cgs | 0 sim/testsuite/{sim => }/frv/fdmovs.cgs | 0 sim/testsuite/{sim => }/frv/fdmss.cgs | 0 sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/fdmuls.cgs | 0 sim/testsuite/{sim => }/frv/fdnegs.cgs | 0 sim/testsuite/{sim => }/frv/fdsads.cgs | 0 sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fdstoi.cgs | 0 sim/testsuite/{sim => }/frv/fdsubs.cgs | 0 sim/testsuite/{sim => }/frv/fdtoi.cgs | 0 sim/testsuite/{sim => }/frv/fitod.cgs | 0 sim/testsuite/{sim => }/frv/fitos.cgs | 0 sim/testsuite/{sim => }/frv/fmad.cgs | 0 sim/testsuite/{sim => }/frv/fmaddd.cgs | 0 sim/testsuite/{sim => }/frv/fmadds.cgs | 0 sim/testsuite/{sim => }/frv/fmas.cgs | 0 sim/testsuite/{sim => }/frv/fmovd.cgs | 0 sim/testsuite/{sim => }/frv/fmovs.cgs | 0 sim/testsuite/{sim => }/frv/fmsd.cgs | 0 sim/testsuite/{sim => }/frv/fmss.cgs | 0 sim/testsuite/{sim => }/frv/fmsubd.cgs | 0 sim/testsuite/{sim => }/frv/fmsubs.cgs | 0 sim/testsuite/{sim => }/frv/fmuld.cgs | 0 sim/testsuite/{sim => }/frv/fmuls.cgs | 0 sim/testsuite/{sim => }/frv/fnegd.cgs | 0 sim/testsuite/{sim => }/frv/fnegs.cgs | 0 sim/testsuite/{sim => }/frv/fnop.cgs | 0 sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0 sim/testsuite/frv/fr400/allinsn.exp | 21 + sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0 sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0 sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0 sim/testsuite/frv/fr500/allinsn.exp | 21 + sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0 sim/testsuite/frv/fr550/allinsn.exp | 21 + sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0 sim/testsuite/{sim => }/frv/fsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fstoi.cgs | 0 sim/testsuite/{sim => }/frv/fsubd.cgs | 0 sim/testsuite/{sim => }/frv/fsubs.cgs | 0 sim/testsuite/{sim => }/frv/fteq.cgs | 0 sim/testsuite/{sim => }/frv/ftge.cgs | 0 sim/testsuite/{sim => }/frv/ftgt.cgs | 0 sim/testsuite/{sim => }/frv/ftieq.cgs | 0 sim/testsuite/{sim => }/frv/ftige.cgs | 0 sim/testsuite/{sim => }/frv/ftigt.cgs | 0 sim/testsuite/{sim => }/frv/ftile.cgs | 0 sim/testsuite/{sim => }/frv/ftilg.cgs | 0 sim/testsuite/{sim => }/frv/ftilt.cgs | 0 sim/testsuite/{sim => }/frv/ftine.cgs | 0 sim/testsuite/{sim => }/frv/ftino.cgs | 0 sim/testsuite/{sim => }/frv/ftio.cgs | 0 sim/testsuite/{sim => }/frv/ftira.cgs | 0 sim/testsuite/{sim => }/frv/ftiu.cgs | 0 sim/testsuite/{sim => }/frv/ftiue.cgs | 0 sim/testsuite/{sim => }/frv/ftiug.cgs | 0 sim/testsuite/{sim => }/frv/ftiuge.cgs | 0 sim/testsuite/{sim => }/frv/ftiul.cgs | 0 sim/testsuite/{sim => }/frv/ftle.cgs | 0 sim/testsuite/{sim => }/frv/ftlg.cgs | 0 sim/testsuite/{sim => }/frv/ftlt.cgs | 0 sim/testsuite/{sim => }/frv/ftne.cgs | 0 sim/testsuite/{sim => }/frv/ftno.cgs | 0 sim/testsuite/{sim => }/frv/fto.cgs | 0 sim/testsuite/{sim => }/frv/ftra.cgs | 0 sim/testsuite/{sim => }/frv/ftu.cgs | 0 sim/testsuite/{sim => }/frv/ftue.cgs | 0 sim/testsuite/{sim => }/frv/ftug.cgs | 0 sim/testsuite/{sim => }/frv/ftuge.cgs | 0 sim/testsuite/{sim => }/frv/ftul.cgs | 0 sim/testsuite/{sim => }/frv/ftule.cgs | 0 sim/testsuite/frv/grloop.ms | 13 + sim/testsuite/frv/hello.ms | 19 + sim/testsuite/{sim => }/frv/icei.cgs | 0 sim/testsuite/{sim => }/frv/ici.cgs | 0 sim/testsuite/{sim => }/frv/icpl.cgs | 0 sim/testsuite/{sim => }/frv/icul.cgs | 0 sim/testsuite/frv/interrupts.exp | 21 + .../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0 .../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0 .../{sim => }/frv/interrupts/badalign-fr550.cgs | 0 .../{sim => }/frv/interrupts/badalign.cgs | 0 .../{sim => }/frv/interrupts/compound-fr550.cgs | 0 .../{sim => }/frv/interrupts/compound.cgs | 0 .../frv/interrupts/data_store_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/data_store_error.cgs | 0 .../frv/interrupts/fp_exception-fr550.cgs | 0 .../{sim => }/frv/interrupts/fp_exception.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0 .../frv/interrupts/insn_access_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/insn_access_error.cgs | 0 .../{sim => }/frv/interrupts/mp_exception.cgs | 0 .../frv/interrupts/privileged_instruction.cgs | 0 .../{sim => }/frv/interrupts/regalign.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0 .../{sim => }/frv/interrupts/shadow_regs.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0 sim/testsuite/{sim => }/frv/jmpil.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.pcgs | 0 sim/testsuite/{sim => }/frv/ld.cgs | 0 sim/testsuite/{sim => }/frv/ldbf.cgs | 0 sim/testsuite/{sim => }/frv/ldbfi.cgs | 0 sim/testsuite/{sim => }/frv/ldbfu.cgs | 0 sim/testsuite/{sim => }/frv/ldc.cgs | 0 sim/testsuite/{sim => }/frv/ldcu.cgs | 0 sim/testsuite/{sim => }/frv/ldd.cgs | 0 sim/testsuite/{sim => }/frv/lddc.cgs | 0 sim/testsuite/{sim => }/frv/lddcu.cgs | 0 sim/testsuite/{sim => }/frv/lddf.cgs | 0 sim/testsuite/{sim => }/frv/lddfi.cgs | 0 sim/testsuite/{sim => }/frv/lddfu.cgs | 0 sim/testsuite/{sim => }/frv/lddi.cgs | 0 sim/testsuite/{sim => }/frv/lddu.cgs | 0 sim/testsuite/{sim => }/frv/ldf.cgs | 0 sim/testsuite/{sim => }/frv/ldfi.cgs | 0 sim/testsuite/{sim => }/frv/ldfu.cgs | 0 sim/testsuite/{sim => }/frv/ldhf.cgs | 0 sim/testsuite/{sim => }/frv/ldhfi.cgs | 0 sim/testsuite/{sim => }/frv/ldhfu.cgs | 0 sim/testsuite/{sim => }/frv/ldi.cgs | 0 sim/testsuite/{sim => }/frv/ldq.cgs | 0 sim/testsuite/{sim => }/frv/ldqc.cgs | 0 sim/testsuite/{sim => }/frv/ldqcu.cgs | 0 sim/testsuite/{sim => }/frv/ldqf.cgs | 0 sim/testsuite/{sim => }/frv/ldqfi.cgs | 0 sim/testsuite/{sim => }/frv/ldqfu.cgs | 0 sim/testsuite/{sim => }/frv/ldqi.cgs | 0 sim/testsuite/{sim => }/frv/ldqu.cgs | 0 sim/testsuite/{sim => }/frv/ldsb.cgs | 0 sim/testsuite/{sim => }/frv/ldsbi.cgs | 0 sim/testsuite/{sim => }/frv/ldsbu.cgs | 0 sim/testsuite/{sim => }/frv/ldsh.cgs | 0 sim/testsuite/{sim => }/frv/ldshi.cgs | 0 sim/testsuite/{sim => }/frv/ldshu.cgs | 0 sim/testsuite/{sim => }/frv/ldu.cgs | 0 sim/testsuite/{sim => }/frv/ldub.cgs | 0 sim/testsuite/{sim => }/frv/ldubi.cgs | 0 sim/testsuite/{sim => }/frv/ldubu.cgs | 0 sim/testsuite/{sim => }/frv/lduh.cgs | 0 sim/testsuite/{sim => }/frv/lduhi.cgs | 0 sim/testsuite/{sim => }/frv/lduhu.cgs | 0 sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0 sim/testsuite/{sim => }/frv/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/mand.cgs | 0 sim/testsuite/{sim => }/frv/maveh.cgs | 0 sim/testsuite/{sim => }/frv/mbtoh.cgs | 0 sim/testsuite/{sim => }/frv/mbtohe.cgs | 0 sim/testsuite/{sim => }/frv/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0 sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0 sim/testsuite/{sim => }/frv/mcop1.cgs | 0 sim/testsuite/{sim => }/frv/mcop2.cgs | 0 sim/testsuite/{sim => }/frv/mcplhi.cgs | 0 sim/testsuite/{sim => }/frv/mcpli.cgs | 0 sim/testsuite/{sim => }/frv/mcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mcut.cgs | 0 sim/testsuite/{sim => }/frv/mcuti.cgs | 0 sim/testsuite/{sim => }/frv/mcutss.cgs | 0 sim/testsuite/{sim => }/frv/mcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdpackh.cgs | 0 sim/testsuite/{sim => }/frv/mdrotli.cgs | 0 sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0 sim/testsuite/{sim => }/frv/membar.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/mhtob.cgs | 0 sim/testsuite/frv/misc.exp | 21 + sim/testsuite/{sim => }/frv/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mnop.cgs | 0 sim/testsuite/{sim => }/frv/mnot.cgs | 0 sim/testsuite/{sim => }/frv/mor.cgs | 0 sim/testsuite/{sim => }/frv/mov.cgs | 0 sim/testsuite/{sim => }/frv/movfg.cgs | 0 sim/testsuite/{sim => }/frv/movfgd.cgs | 0 sim/testsuite/{sim => }/frv/movfgq.cgs | 0 sim/testsuite/{sim => }/frv/movgf.cgs | 0 sim/testsuite/{sim => }/frv/movgfd.cgs | 0 sim/testsuite/{sim => }/frv/movgfq.cgs | 0 sim/testsuite/{sim => }/frv/movgs.cgs | 0 sim/testsuite/{sim => }/frv/movsg.cgs | 0 sim/testsuite/{sim => }/frv/mpackh.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0 sim/testsuite/{sim => }/frv/mqlmths.cgs | 0 sim/testsuite/{sim => }/frv/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mqsaths.cgs | 0 sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0 sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0 sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mrdacc.cgs | 0 sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0 sim/testsuite/{sim => }/frv/mrotli.cgs | 0 sim/testsuite/{sim => }/frv/mrotri.cgs | 0 sim/testsuite/{sim => }/frv/msaths.cgs | 0 sim/testsuite/{sim => }/frv/msathu.cgs | 0 sim/testsuite/{sim => }/frv/msllhi.cgs | 0 sim/testsuite/{sim => }/frv/msrahi.cgs | 0 sim/testsuite/{sim => }/frv/msrlhi.cgs | 0 sim/testsuite/{sim => }/frv/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/munpackh.cgs | 0 sim/testsuite/{sim => }/frv/mwcut.cgs | 0 sim/testsuite/{sim => }/frv/mwcuti.cgs | 0 sim/testsuite/{sim => }/frv/mwtacc.cgs | 0 sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0 sim/testsuite/{sim => }/frv/mxor.cgs | 0 sim/testsuite/{sim => }/frv/nandcr.cgs | 0 sim/testsuite/{sim => }/frv/nandncr.cgs | 0 sim/testsuite/{sim => }/frv/nfadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0 sim/testsuite/{sim => }/frv/nfddivs.cgs | 0 sim/testsuite/{sim => }/frv/nfditos.cgs | 0 sim/testsuite/{sim => }/frv/nfdivs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdmas.cgs | 0 sim/testsuite/{sim => }/frv/nfdmss.cgs | 0 sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfdsads.cgs | 0 sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfitos.cgs | 0 sim/testsuite/{sim => }/frv/nfmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfmas.cgs | 0 sim/testsuite/{sim => }/frv/nfmss.cgs | 0 sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfsubs.cgs | 0 sim/testsuite/{sim => }/frv/nld.cgs | 0 sim/testsuite/{sim => }/frv/nldbf.cgs | 0 sim/testsuite/{sim => }/frv/nldbfi.cgs | 0 sim/testsuite/{sim => }/frv/nldbfu.cgs | 0 sim/testsuite/{sim => }/frv/nldd.cgs | 0 sim/testsuite/{sim => }/frv/nlddf.cgs | 0 sim/testsuite/{sim => }/frv/nlddfi.cgs | 0 sim/testsuite/{sim => }/frv/nlddfu.cgs | 0 sim/testsuite/{sim => }/frv/nlddi.cgs | 0 sim/testsuite/{sim => }/frv/nlddu.cgs | 0 sim/testsuite/{sim => }/frv/nldf.cgs | 0 sim/testsuite/{sim => }/frv/nldfi.cgs | 0 sim/testsuite/{sim => }/frv/nldfu.cgs | 0 sim/testsuite/{sim => }/frv/nldhf.cgs | 0 sim/testsuite/{sim => }/frv/nldhfi.cgs | 0 sim/testsuite/{sim => }/frv/nldhfu.cgs | 0 sim/testsuite/{sim => }/frv/nldi.cgs | 0 sim/testsuite/{sim => }/frv/nldq.cgs | 0 sim/testsuite/{sim => }/frv/nldqf.cgs | 0 sim/testsuite/{sim => }/frv/nldqfi.cgs | 0 sim/testsuite/{sim => }/frv/nldqfu.cgs | 0 sim/testsuite/{sim => }/frv/nldqu.cgs | 0 sim/testsuite/{sim => }/frv/nldsb.cgs | 0 sim/testsuite/{sim => }/frv/nldsbi.cgs | 0 sim/testsuite/{sim => }/frv/nldsbu.cgs | 0 sim/testsuite/{sim => }/frv/nldsh.cgs | 0 sim/testsuite/{sim => }/frv/nldshi.cgs | 0 sim/testsuite/{sim => }/frv/nldshu.cgs | 0 sim/testsuite/{sim => }/frv/nldu.cgs | 0 sim/testsuite/{sim => }/frv/nldub.cgs | 0 sim/testsuite/{sim => }/frv/nldubi.cgs | 0 sim/testsuite/{sim => }/frv/nldubu.cgs | 0 sim/testsuite/{sim => }/frv/nlduh.cgs | 0 sim/testsuite/{sim => }/frv/nlduhi.cgs | 0 sim/testsuite/{sim => }/frv/nlduhu.cgs | 0 sim/testsuite/{sim => }/frv/nop.cgs | 0 sim/testsuite/{sim => }/frv/norcr.cgs | 0 sim/testsuite/{sim => }/frv/norncr.cgs | 0 sim/testsuite/{sim => }/frv/not.cgs | 0 sim/testsuite/{sim => }/frv/notcr.cgs | 0 sim/testsuite/{sim => }/frv/nsdiv.cgs | 0 sim/testsuite/{sim => }/frv/nsdivi.cgs | 0 sim/testsuite/{sim => }/frv/nudiv.cgs | 0 sim/testsuite/{sim => }/frv/nudivi.cgs | 0 sim/testsuite/{sim => }/frv/or.cgs | 0 sim/testsuite/{sim => }/frv/orcc.cgs | 0 sim/testsuite/{sim => }/frv/orcr.cgs | 0 sim/testsuite/{sim => }/frv/ori.cgs | 0 sim/testsuite/{sim => }/frv/oricc.cgs | 0 sim/testsuite/{sim => }/frv/orncr.cgs | 0 sim/testsuite/frv/parallel.exp | 21 + sim/testsuite/{sim => }/frv/ret.cgs | 0 sim/testsuite/{sim => }/frv/rett.cgs | 0 sim/testsuite/{sim => }/frv/scan.cgs | 0 sim/testsuite/{sim => }/frv/scani.cgs | 0 sim/testsuite/{sim => }/frv/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/sethi.cgs | 0 sim/testsuite/{sim => }/frv/sethilo.pcgs | 0 sim/testsuite/{sim => }/frv/setlo.cgs | 0 sim/testsuite/{sim => }/frv/setlos.cgs | 0 sim/testsuite/{sim => }/frv/sll.cgs | 0 sim/testsuite/{sim => }/frv/sllcc.cgs | 0 sim/testsuite/{sim => }/frv/slli.cgs | 0 sim/testsuite/{sim => }/frv/sllicc.cgs | 0 sim/testsuite/{sim => }/frv/smul.cgs | 0 sim/testsuite/{sim => }/frv/smulcc.cgs | 0 sim/testsuite/{sim => }/frv/smuli.cgs | 0 sim/testsuite/{sim => }/frv/smulicc.cgs | 0 sim/testsuite/{sim => }/frv/sra.cgs | 0 sim/testsuite/{sim => }/frv/sracc.cgs | 0 sim/testsuite/{sim => }/frv/srai.cgs | 0 sim/testsuite/{sim => }/frv/sraicc.cgs | 0 sim/testsuite/{sim => }/frv/srl.cgs | 0 sim/testsuite/{sim => }/frv/srlcc.cgs | 0 sim/testsuite/{sim => }/frv/srli.cgs | 0 sim/testsuite/{sim => }/frv/srlicc.cgs | 0 sim/testsuite/{sim => }/frv/st.cgs | 0 sim/testsuite/{sim => }/frv/stb.cgs | 0 sim/testsuite/{sim => }/frv/stbf.cgs | 0 sim/testsuite/{sim => }/frv/stbfi.cgs | 0 sim/testsuite/{sim => }/frv/stbfu.cgs | 0 sim/testsuite/{sim => }/frv/stbi.cgs | 0 sim/testsuite/{sim => }/frv/stbu.cgs | 0 sim/testsuite/{sim => }/frv/stc.cgs | 0 sim/testsuite/{sim => }/frv/stcu.cgs | 0 sim/testsuite/{sim => }/frv/std.cgs | 0 sim/testsuite/{sim => }/frv/std.pcgs | 0 sim/testsuite/{sim => }/frv/stdc.cgs | 0 sim/testsuite/{sim => }/frv/stdc.pcgs | 0 sim/testsuite/{sim => }/frv/stdcu.cgs | 0 sim/testsuite/{sim => }/frv/stdf.cgs | 0 sim/testsuite/{sim => }/frv/stdf.pcgs | 0 sim/testsuite/{sim => }/frv/stdfi.cgs | 0 sim/testsuite/{sim => }/frv/stdfu.cgs | 0 sim/testsuite/{sim => }/frv/stdi.cgs | 0 sim/testsuite/{sim => }/frv/stdu.cgs | 0 sim/testsuite/{sim => }/frv/stf.cgs | 0 sim/testsuite/{sim => }/frv/stfi.cgs | 0 sim/testsuite/{sim => }/frv/stfu.cgs | 0 sim/testsuite/{sim => }/frv/sth.cgs | 0 sim/testsuite/{sim => }/frv/sthf.cgs | 0 sim/testsuite/{sim => }/frv/sthfi.cgs | 0 sim/testsuite/{sim => }/frv/sthfu.cgs | 0 sim/testsuite/{sim => }/frv/sthi.cgs | 0 sim/testsuite/{sim => }/frv/sthu.cgs | 0 sim/testsuite/{sim => }/frv/sti.cgs | 0 sim/testsuite/{sim => }/frv/stq.cgs | 0 sim/testsuite/{sim => }/frv/stq.pcgs | 0 sim/testsuite/{sim => }/frv/stqc.cgs | 0 sim/testsuite/{sim => }/frv/stqc.pcgs | 0 sim/testsuite/{sim => }/frv/stqcu.cgs | 0 sim/testsuite/{sim => }/frv/stqf.cgs | 0 sim/testsuite/{sim => }/frv/stqf.pcgs | 0 sim/testsuite/{sim => }/frv/stqfi.cgs | 0 sim/testsuite/{sim => }/frv/stqfu.cgs | 0 sim/testsuite/{sim => }/frv/stqi.cgs | 0 sim/testsuite/{sim => }/frv/stqu.cgs | 0 sim/testsuite/{sim => }/frv/stu.cgs | 0 sim/testsuite/{sim => }/frv/sub.cgs | 0 sim/testsuite/{sim => }/frv/subcc.cgs | 0 sim/testsuite/{sim => }/frv/subi.cgs | 0 sim/testsuite/{sim => }/frv/subicc.cgs | 0 sim/testsuite/{sim => }/frv/subx.cgs | 0 sim/testsuite/{sim => }/frv/subxcc.cgs | 0 sim/testsuite/{sim => }/frv/subxi.cgs | 0 sim/testsuite/{sim => }/frv/subxicc.cgs | 0 sim/testsuite/{sim => }/frv/swap.cgs | 0 sim/testsuite/{sim => }/frv/swapi.cgs | 0 sim/testsuite/{sim => }/frv/tc.cgs | 0 sim/testsuite/{sim => }/frv/teq.cgs | 0 sim/testsuite/{sim => }/frv/testutils.inc | 0 sim/testsuite/{sim => }/frv/tge.cgs | 0 sim/testsuite/{sim => }/frv/tgt.cgs | 0 sim/testsuite/{sim => }/frv/thi.cgs | 0 sim/testsuite/{sim => }/frv/tic.cgs | 0 sim/testsuite/{sim => }/frv/tieq.cgs | 0 sim/testsuite/{sim => }/frv/tige.cgs | 0 sim/testsuite/{sim => }/frv/tigt.cgs | 0 sim/testsuite/{sim => }/frv/tihi.cgs | 0 sim/testsuite/{sim => }/frv/tile.cgs | 0 sim/testsuite/{sim => }/frv/tils.cgs | 0 sim/testsuite/{sim => }/frv/tilt.cgs | 0 sim/testsuite/{sim => }/frv/tin.cgs | 0 sim/testsuite/{sim => }/frv/tinc.cgs | 0 sim/testsuite/{sim => }/frv/tine.cgs | 0 sim/testsuite/{sim => }/frv/tino.cgs | 0 sim/testsuite/{sim => }/frv/tinv.cgs | 0 sim/testsuite/{sim => }/frv/tip.cgs | 0 sim/testsuite/{sim => }/frv/tira.cgs | 0 sim/testsuite/{sim => }/frv/tiv.cgs | 0 sim/testsuite/{sim => }/frv/tle.cgs | 0 sim/testsuite/{sim => }/frv/tls.cgs | 0 sim/testsuite/{sim => }/frv/tlt.cgs | 0 sim/testsuite/{sim => }/frv/tn.cgs | 0 sim/testsuite/{sim => }/frv/tnc.cgs | 0 sim/testsuite/{sim => }/frv/tne.cgs | 0 sim/testsuite/{sim => }/frv/tno.cgs | 0 sim/testsuite/{sim => }/frv/tnv.cgs | 0 sim/testsuite/{sim => }/frv/tp.cgs | 0 sim/testsuite/{sim => }/frv/tra.cgs | 0 sim/testsuite/{sim => }/frv/tv.cgs | 0 sim/testsuite/{sim => }/frv/udiv.cgs | 0 sim/testsuite/{sim => }/frv/udivi.cgs | 0 sim/testsuite/{sim => }/frv/umul.cgs | 0 sim/testsuite/{sim => }/frv/umulcc.cgs | 0 sim/testsuite/{sim => }/frv/umuli.cgs | 0 sim/testsuite/{sim => }/frv/umulicc.cgs | 0 sim/testsuite/{sim => }/frv/xor.cgs | 0 sim/testsuite/{sim => }/frv/xorcc.cgs | 0 sim/testsuite/{sim => }/frv/xorcr.cgs | 0 sim/testsuite/{sim => }/frv/xori.cgs | 0 sim/testsuite/{sim => }/frv/xoricc.cgs | 0 sim/testsuite/ft32/ChangeLog | 12 + sim/testsuite/ft32/allinsn.exp | 19 + sim/testsuite/{sim => }/ft32/basic.s | 0 sim/testsuite/{sim => }/ft32/testutils.inc | 0 sim/testsuite/h8300/ChangeLog | 111 + sim/testsuite/{sim => }/h8300/addb.s | 0 sim/testsuite/{sim => }/h8300/addl.s | 0 sim/testsuite/{sim => }/h8300/adds.s | 0 sim/testsuite/{sim => }/h8300/addw.s | 0 sim/testsuite/{sim => }/h8300/addx.s | 0 sim/testsuite/h8300/allinsn.exp | 19 + sim/testsuite/{sim => }/h8300/andb.s | 0 sim/testsuite/{sim => }/h8300/andl.s | 0 sim/testsuite/{sim => }/h8300/andw.s | 0 sim/testsuite/{sim => }/h8300/band.s | 0 sim/testsuite/{sim => }/h8300/bfld.s | 0 sim/testsuite/{sim => }/h8300/biand.s | 0 sim/testsuite/{sim => }/h8300/bra.s | 0 sim/testsuite/{sim => }/h8300/brabc.s | 0 sim/testsuite/{sim => }/h8300/bset.s | 0 sim/testsuite/{sim => }/h8300/cmpb.s | 0 sim/testsuite/{sim => }/h8300/cmpl.s | 0 sim/testsuite/{sim => }/h8300/cmpw.s | 0 sim/testsuite/{sim => }/h8300/daa.s | 0 sim/testsuite/{sim => }/h8300/das.s | 0 sim/testsuite/{sim => }/h8300/dec.s | 0 sim/testsuite/{sim => }/h8300/div.s | 0 sim/testsuite/{sim => }/h8300/extl.s | 0 sim/testsuite/{sim => }/h8300/extw.s | 0 sim/testsuite/{sim => }/h8300/inc.s | 0 sim/testsuite/{sim => }/h8300/jmp.s | 0 sim/testsuite/{sim => }/h8300/ldc.s | 0 sim/testsuite/{sim => }/h8300/ldm.s | 0 sim/testsuite/{sim => }/h8300/mac.s | 0 sim/testsuite/{sim => }/h8300/mova.s | 0 sim/testsuite/{sim => }/h8300/movb.s | 0 sim/testsuite/{sim => }/h8300/movl.s | 0 sim/testsuite/{sim => }/h8300/movmd.s | 0 sim/testsuite/{sim => }/h8300/movsd.s | 0 sim/testsuite/{sim => }/h8300/movw.s | 0 sim/testsuite/{sim => }/h8300/mul.s | 0 sim/testsuite/{sim => }/h8300/neg.s | 0 sim/testsuite/{sim => }/h8300/nop.s | 0 sim/testsuite/{sim => }/h8300/not.s | 0 sim/testsuite/{sim => }/h8300/orb.s | 0 sim/testsuite/{sim => }/h8300/orl.s | 0 sim/testsuite/{sim => }/h8300/orw.s | 0 sim/testsuite/{sim => }/h8300/rotl.s | 0 sim/testsuite/{sim => }/h8300/rotr.s | 0 sim/testsuite/{sim => }/h8300/rotxl.s | 0 sim/testsuite/{sim => }/h8300/rotxr.s | 0 sim/testsuite/{sim => }/h8300/shal.s | 0 sim/testsuite/{sim => }/h8300/shar.s | 0 sim/testsuite/{sim => }/h8300/shll.s | 0 sim/testsuite/{sim => }/h8300/shlr.s | 0 sim/testsuite/{sim => }/h8300/stack.s | 0 sim/testsuite/{sim => }/h8300/stc.s | 0 sim/testsuite/{sim => }/h8300/subb.s | 0 sim/testsuite/{sim => }/h8300/subl.s | 0 sim/testsuite/{sim => }/h8300/subs.s | 0 sim/testsuite/{sim => }/h8300/subw.s | 0 sim/testsuite/{sim => }/h8300/subx.s | 0 sim/testsuite/{sim => }/h8300/tas.s | 0 sim/testsuite/{sim => }/h8300/testutils.inc | 0 sim/testsuite/{sim => }/h8300/xorb.s | 0 sim/testsuite/{sim => }/h8300/xorl.s | 0 sim/testsuite/{sim => }/h8300/xorw.s | 0 sim/testsuite/iq2000/ChangeLog | 7 + sim/testsuite/iq2000/allinsn.exp | 19 + sim/testsuite/{sim => }/iq2000/pass.s | 0 sim/testsuite/{sim => }/iq2000/testutils.inc | 0 sim/testsuite/lib/sim-defs.exp | 25 +- sim/testsuite/lm32/ChangeLog | 7 + sim/testsuite/lm32/allinsn.exp | 19 + sim/testsuite/{sim => }/lm32/pass.s | 0 sim/testsuite/{sim => }/lm32/testutils.inc | 0 sim/testsuite/local.mk | 34 + sim/testsuite/m32c/ChangeLog | 14 + sim/testsuite/m32c/allinsn.exp | 20 + sim/testsuite/{sim => }/m32c/blinky.s | 0 sim/testsuite/{sim => }/m32c/fail.s | 0 sim/testsuite/{sim => }/m32c/gloss.s | 0 sim/testsuite/{sim => }/m32c/pass.s | 0 sim/testsuite/{sim => }/m32c/sample.ld | 0 sim/testsuite/{sim => }/m32c/sample.s | 0 sim/testsuite/{sim => }/m32c/sample2.c | 0 sim/testsuite/{sim => }/m32c/testutils.inc | 0 sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 ---- sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/exit47.s | 7 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/m32r/ChangeLog | 130 + sim/testsuite/{sim => }/m32r/add.cgs | 0 sim/testsuite/{sim => }/m32r/add3.cgs | 0 sim/testsuite/{sim => }/m32r/addi.cgs | 0 sim/testsuite/{sim => }/m32r/addv.cgs | 0 sim/testsuite/{sim => }/m32r/addv3.cgs | 0 sim/testsuite/{sim => }/m32r/addx.cgs | 0 sim/testsuite/m32r/allinsn.exp | 22 + sim/testsuite/{sim => }/m32r/and.cgs | 0 sim/testsuite/{sim => }/m32r/and3.cgs | 0 sim/testsuite/{sim => }/m32r/bc24.cgs | 0 sim/testsuite/{sim => }/m32r/bc8.cgs | 0 sim/testsuite/{sim => }/m32r/beq.cgs | 0 sim/testsuite/{sim => }/m32r/beqz.cgs | 0 sim/testsuite/{sim => }/m32r/bgez.cgs | 0 sim/testsuite/{sim => }/m32r/bgtz.cgs | 0 sim/testsuite/{sim => }/m32r/bl24.cgs | 0 sim/testsuite/{sim => }/m32r/bl8.cgs | 0 sim/testsuite/{sim => }/m32r/blez.cgs | 0 sim/testsuite/{sim => }/m32r/bltz.cgs | 0 sim/testsuite/{sim => }/m32r/bnc24.cgs | 0 sim/testsuite/{sim => }/m32r/bnc8.cgs | 0 sim/testsuite/{sim => }/m32r/bne.cgs | 0 sim/testsuite/{sim => }/m32r/bnez.cgs | 0 sim/testsuite/{sim => }/m32r/bra24.cgs | 0 sim/testsuite/{sim => }/m32r/bra8.cgs | 0 sim/testsuite/{sim => }/m32r/cmp.cgs | 0 sim/testsuite/{sim => }/m32r/cmpi.cgs | 0 sim/testsuite/{sim => }/m32r/cmpu.cgs | 0 sim/testsuite/{sim => }/m32r/cmpui.cgs | 0 sim/testsuite/{sim => }/m32r/div.cgs | 0 sim/testsuite/{sim => }/m32r/divu.cgs | 0 sim/testsuite/m32r/exit47.ms | 11 + sim/testsuite/{sim => }/m32r/hello.ms | 0 sim/testsuite/{sim => }/m32r/hw-trap.ms | 0 sim/testsuite/{sim => }/m32r/jl.cgs | 0 sim/testsuite/{sim => }/m32r/jmp.cgs | 0 sim/testsuite/{sim => }/m32r/ld-d.cgs | 0 sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0 sim/testsuite/{sim => }/m32r/ld.cgs | 0 sim/testsuite/{sim => }/m32r/ld24.cgs | 0 sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldb.cgs | 0 sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldh.cgs | 0 sim/testsuite/{sim => }/m32r/ldi16.cgs | 0 sim/testsuite/{sim => }/m32r/ldi8.cgs | 0 sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldub.cgs | 0 sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0 sim/testsuite/{sim => }/m32r/lduh.cgs | 0 sim/testsuite/{sim => }/m32r/lock.cgs | 0 sim/testsuite/{sim => }/m32r/machi.cgs | 0 sim/testsuite/{sim => }/m32r/maclo.cgs | 0 sim/testsuite/{sim => }/m32r/macwhi.cgs | 0 sim/testsuite/{sim => }/m32r/macwlo.cgs | 0 sim/testsuite/m32r/misc.exp | 22 + sim/testsuite/{sim => }/m32r/mul.cgs | 0 sim/testsuite/{sim => }/m32r/mulhi.cgs | 0 sim/testsuite/{sim => }/m32r/mullo.cgs | 0 sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0 sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0 sim/testsuite/{sim => }/m32r/mv.cgs | 0 sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfc.cgs | 0 sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvtc.cgs | 0 sim/testsuite/{sim => }/m32r/neg.cgs | 0 sim/testsuite/{sim => }/m32r/nop.cgs | 0 sim/testsuite/{sim => }/m32r/not.cgs | 0 sim/testsuite/{sim => }/m32r/or.cgs | 0 sim/testsuite/{sim => }/m32r/or3.cgs | 0 sim/testsuite/{sim => }/m32r/rac.cgs | 0 sim/testsuite/{sim => }/m32r/rach.cgs | 0 sim/testsuite/{sim => }/m32r/rem.cgs | 0 sim/testsuite/{sim => }/m32r/remu.cgs | 0 sim/testsuite/{sim => }/m32r/rte.cgs | 0 sim/testsuite/{sim => }/m32r/seth.cgs | 0 sim/testsuite/{sim => }/m32r/sll.cgs | 0 sim/testsuite/{sim => }/m32r/sll3.cgs | 0 sim/testsuite/{sim => }/m32r/slli.cgs | 0 sim/testsuite/{sim => }/m32r/sra.cgs | 0 sim/testsuite/{sim => }/m32r/sra3.cgs | 0 sim/testsuite/{sim => }/m32r/srai.cgs | 0 sim/testsuite/{sim => }/m32r/srl.cgs | 0 sim/testsuite/{sim => }/m32r/srl3.cgs | 0 sim/testsuite/{sim => }/m32r/srli.cgs | 0 sim/testsuite/{sim => }/m32r/st-d.cgs | 0 sim/testsuite/{sim => }/m32r/st-minus.cgs | 0 sim/testsuite/{sim => }/m32r/st-plus.cgs | 0 sim/testsuite/{sim => }/m32r/st.cgs | 0 sim/testsuite/{sim => }/m32r/stb-d.cgs | 0 sim/testsuite/{sim => }/m32r/stb.cgs | 0 sim/testsuite/{sim => }/m32r/sth-d.cgs | 0 sim/testsuite/{sim => }/m32r/sth.cgs | 0 sim/testsuite/{sim => }/m32r/sub.cgs | 0 sim/testsuite/{sim => }/m32r/subv.cgs | 0 sim/testsuite/{sim => }/m32r/subx.cgs | 0 sim/testsuite/{sim => }/m32r/testutils.inc | 0 sim/testsuite/{sim => }/m32r/trap.cgs | 0 sim/testsuite/{sim => }/m32r/unlock.cgs | 0 sim/testsuite/{sim => }/m32r/uread16.ms | 0 sim/testsuite/{sim => }/m32r/uread32.ms | 0 sim/testsuite/{sim => }/m32r/uwrite16.ms | 0 sim/testsuite/{sim => }/m32r/uwrite32.ms | 0 sim/testsuite/{sim => }/m32r/xor.cgs | 0 sim/testsuite/{sim => }/m32r/xor3.cgs | 0 sim/testsuite/m68hc11/ChangeLog | 7 + sim/testsuite/m68hc11/allinsn.exp | 19 + sim/testsuite/{sim => }/m68hc11/pass.s | 0 sim/testsuite/{sim => }/m68hc11/testutils.inc | 0 sim/testsuite/mcore/ChangeLog | 12 + sim/testsuite/mcore/allinsn.exp | 19 + sim/testsuite/{sim => }/mcore/fail.s | 0 sim/testsuite/{sim => }/mcore/pass.s | 0 sim/testsuite/{sim => }/mcore/testutils.inc | 0 sim/testsuite/microblaze/ChangeLog | 7 + sim/testsuite/microblaze/allinsn.exp | 19 + sim/testsuite/{sim => }/microblaze/pass.s | 0 sim/testsuite/{sim => }/microblaze/testutils.inc | 0 sim/testsuite/mips/ChangeLog | 122 + sim/testsuite/mips/basic.exp | 109 + sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s | 0 sim/testsuite/{sim => }/mips/fpu64-ps.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-1.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-2.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-3.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-4.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp2.s | 0 sim/testsuite/{sim => }/mips/sanity.s | 0 sim/testsuite/{sim => }/mips/testutils.inc | 0 sim/testsuite/{sim => }/mips/utils-dsp.inc | 0 sim/testsuite/{sim => }/mips/utils-fpu.inc | 0 sim/testsuite/{sim => }/mips/utils-mdmx.inc | 0 sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 ---- sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/mn10300/ChangeLog | 7 + sim/testsuite/mn10300/allinsn.exp | 19 + sim/testsuite/{sim => }/mn10300/pass.s | 0 sim/testsuite/{sim => }/mn10300/testutils.inc | 0 sim/testsuite/moxie/ChangeLog | 7 + sim/testsuite/moxie/allinsn.exp | 19 + sim/testsuite/{sim => }/moxie/pass.s | 0 sim/testsuite/{sim => }/moxie/testutils.inc | 0 sim/testsuite/msp430/ChangeLog | 21 + sim/testsuite/{sim => }/msp430/add.s | 0 sim/testsuite/msp430/allinsn.exp | 19 + sim/testsuite/{sim => }/msp430/mpyull_hwmult.s | 0 sim/testsuite/{sim => }/msp430/rrux.s | 0 sim/testsuite/{sim => }/msp430/testutils.inc | 0 sim/testsuite/or1k/ChangeLog | 50 + sim/testsuite/{sim => }/or1k/add.S | 0 sim/testsuite/{sim => }/or1k/adrp.S | 0 sim/testsuite/or1k/alltests.exp | 37 + sim/testsuite/{sim => }/or1k/and.S | 0 sim/testsuite/{sim => }/or1k/basic.S | 0 sim/testsuite/{sim => }/or1k/div.S | 0 sim/testsuite/{sim => }/or1k/ext.S | 0 sim/testsuite/{sim => }/or1k/find.S | 0 sim/testsuite/{sim => }/or1k/flag.S | 0 sim/testsuite/{sim => }/or1k/fpu-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32.S | 0 sim/testsuite/{sim => }/or1k/jump.S | 0 sim/testsuite/{sim => }/or1k/load.S | 0 sim/testsuite/{sim => }/or1k/mac.S | 0 sim/testsuite/{sim => }/or1k/mfspr.S | 0 sim/testsuite/{sim => }/or1k/mul.S | 0 sim/testsuite/{sim => }/or1k/or.S | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h | 0 .../{sim => }/or1k/or1k-asm-test-helpers.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm.h | 0 sim/testsuite/{sim => }/or1k/or1k-test.ld | 0 sim/testsuite/{sim => }/or1k/ror.S | 0 sim/testsuite/{sim => }/or1k/shift.S | 0 sim/testsuite/{sim => }/or1k/spr-defs.h | 0 sim/testsuite/{sim => }/or1k/sub.S | 0 sim/testsuite/{sim => }/or1k/xor.S | 0 sim/testsuite/pru/ChangeLog | 21 + sim/testsuite/{sim => }/pru/add.s | 0 sim/testsuite/pru/allinsn.exp | 37 + sim/testsuite/{sim => }/pru/dmem-zero-pass.s | 0 sim/testsuite/{sim => }/pru/dmem-zero-trap.s | 0 sim/testsuite/{sim => }/pru/dram.s | 0 sim/testsuite/{sim => }/pru/jmp.s | 0 sim/testsuite/{sim => }/pru/lmbd.s | 0 sim/testsuite/{sim => }/pru/loop-imm.s | 0 sim/testsuite/{sim => }/pru/loop-reg.s | 0 sim/testsuite/{sim => }/pru/mul.s | 0 sim/testsuite/{sim => }/pru/subreg.s | 0 sim/testsuite/{sim => }/pru/testutils.inc | 0 sim/testsuite/riscv/ChangeLog | 7 + sim/testsuite/riscv/allinsn.exp | 19 + sim/testsuite/riscv/pass.s | 7 + sim/testsuite/riscv/testutils.inc | 52 + sim/testsuite/sh/ChangeLog | 81 + sim/testsuite/{sim => }/sh/add.s | 0 sim/testsuite/sh/allinsn.exp | 93 + sim/testsuite/{sim => }/sh/and.s | 0 sim/testsuite/{sim => }/sh/bandor.s | 0 sim/testsuite/{sim => }/sh/bandornot.s | 0 sim/testsuite/{sim => }/sh/bclr.s | 0 sim/testsuite/{sim => }/sh/bld.s | 0 sim/testsuite/{sim => }/sh/bldnot.s | 0 sim/testsuite/{sim => }/sh/bset.s | 0 sim/testsuite/{sim => }/sh/bst.s | 0 sim/testsuite/{sim => }/sh/bxor.s | 0 sim/testsuite/{sim => }/sh/clip.s | 0 sim/testsuite/{sim => }/sh/div.s | 0 sim/testsuite/{sim => }/sh/dmxy.s | 0 sim/testsuite/{sim => }/sh/fabs.s | 0 sim/testsuite/{sim => }/sh/fadd.s | 0 sim/testsuite/{sim => }/sh/fail.s | 0 sim/testsuite/{sim => }/sh/fcmpeq.s | 0 sim/testsuite/{sim => }/sh/fcmpgt.s | 0 sim/testsuite/{sim => }/sh/fcnvds.s | 0 sim/testsuite/{sim => }/sh/fcnvsd.s | 0 sim/testsuite/{sim => }/sh/fdiv.s | 0 sim/testsuite/{sim => }/sh/fipr.s | 0 sim/testsuite/{sim => }/sh/fldi0.s | 0 sim/testsuite/{sim => }/sh/fldi1.s | 0 sim/testsuite/{sim => }/sh/flds.s | 0 sim/testsuite/{sim => }/sh/float.s | 0 sim/testsuite/{sim => }/sh/fmac.s | 0 sim/testsuite/{sim => }/sh/fmov.s | 0 sim/testsuite/{sim => }/sh/fmul.s | 0 sim/testsuite/{sim => }/sh/fneg.s | 0 sim/testsuite/{sim => }/sh/fpchg.s | 0 sim/testsuite/{sim => }/sh/frchg.s | 0 sim/testsuite/{sim => }/sh/fsca.s | 0 sim/testsuite/{sim => }/sh/fschg.s | 0 sim/testsuite/{sim => }/sh/fsqrt.s | 0 sim/testsuite/{sim => }/sh/fsrra.s | 0 sim/testsuite/{sim => }/sh/fsub.s | 0 sim/testsuite/{sim => }/sh/ftrc.s | 0 sim/testsuite/{sim => }/sh/ldrc.s | 0 sim/testsuite/{sim => }/sh/loop.s | 0 sim/testsuite/{sim => }/sh/macl.s | 0 sim/testsuite/{sim => }/sh/macw.s | 0 sim/testsuite/{sim => }/sh/mov.s | 0 sim/testsuite/{sim => }/sh/movi.s | 0 sim/testsuite/{sim => }/sh/movli.s | 0 sim/testsuite/{sim => }/sh/movua.s | 0 sim/testsuite/{sim => }/sh/movxy.s | 0 sim/testsuite/{sim => }/sh/mulr.s | 0 sim/testsuite/{sim => }/sh/pabs.s | 0 sim/testsuite/{sim => }/sh/padd.s | 0 sim/testsuite/{sim => }/sh/paddc.s | 0 sim/testsuite/{sim => }/sh/pand.s | 0 sim/testsuite/{sim => }/sh/pass.s | 0 sim/testsuite/{sim => }/sh/pclr.s | 0 sim/testsuite/{sim => }/sh/pdec.s | 0 sim/testsuite/{sim => }/sh/pdmsb.s | 0 sim/testsuite/{sim => }/sh/pinc.s | 0 sim/testsuite/{sim => }/sh/pmuls.s | 0 sim/testsuite/{sim => }/sh/prnd.s | 0 sim/testsuite/{sim => }/sh/pshai.s | 0 sim/testsuite/{sim => }/sh/pshar.s | 0 sim/testsuite/{sim => }/sh/pshli.s | 0 sim/testsuite/{sim => }/sh/pshlr.s | 0 sim/testsuite/{sim => }/sh/psub.s | 0 sim/testsuite/{sim => }/sh/pswap.s | 0 sim/testsuite/{sim => }/sh/pushpop.s | 0 sim/testsuite/{sim => }/sh/resbank.s | 0 sim/testsuite/{sim => }/sh/sett.s | 0 sim/testsuite/{sim => }/sh/shll.s | 0 sim/testsuite/{sim => }/sh/shll16.s | 0 sim/testsuite/{sim => }/sh/shll2.s | 0 sim/testsuite/{sim => }/sh/shll8.s | 0 sim/testsuite/{sim => }/sh/shlr.s | 0 sim/testsuite/{sim => }/sh/shlr16.s | 0 sim/testsuite/{sim => }/sh/shlr2.s | 0 sim/testsuite/{sim => }/sh/shlr8.s | 0 sim/testsuite/{sim => }/sh/swap.s | 0 sim/testsuite/{sim => }/sh/testutils.inc | 0 sim/testsuite/sim/aarch64/ChangeLog | 83 - sim/testsuite/sim/aarch64/allinsn.exp | 15 - sim/testsuite/sim/arm/ChangeLog | 122 - sim/testsuite/sim/arm/allinsn.exp | 28 - sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp | 28 - sim/testsuite/sim/arm/misc.exp | 20 - sim/testsuite/sim/arm/thumb/allthumb.exp | 20 - sim/testsuite/sim/arm/xscale/xscale.exp | 28 - sim/testsuite/sim/avr/ChangeLog | 7 - sim/testsuite/sim/avr/allinsn.exp | 15 - sim/testsuite/sim/bfin/ChangeLog | 370 - sim/testsuite/sim/bfin/allinsn.exp | 43 - sim/testsuite/sim/bfin/s21.s | 298 - sim/testsuite/sim/bpf/ChangeLog | 20 - sim/testsuite/sim/bpf/allinsn.exp | 26 - sim/testsuite/sim/cr16/ChangeLog | 51 - sim/testsuite/sim/cr16/allinsn.exp | 31 - sim/testsuite/sim/cr16/misc.exp | 31 - sim/testsuite/sim/cris/ChangeLog | 197 - sim/testsuite/sim/cris/asm/asm.exp | 45 - sim/testsuite/sim/cris/c/c.exp | 248 - sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 249 - sim/testsuite/sim/frv/ChangeLog | 76 - sim/testsuite/sim/frv/allinsn.exp | 19 - sim/testsuite/sim/frv/fr400/allinsn.exp | 19 - sim/testsuite/sim/frv/fr500/allinsn.exp | 19 - sim/testsuite/sim/frv/fr550/allinsn.exp | 19 - sim/testsuite/sim/frv/interrupts.exp | 19 - sim/testsuite/sim/frv/parallel.exp | 19 - sim/testsuite/sim/ft32/ChangeLog | 8 - sim/testsuite/sim/ft32/allinsn.exp | 15 - sim/testsuite/sim/h8300/ChangeLog | 107 - sim/testsuite/sim/h8300/allinsn.exp | 15 - sim/testsuite/sim/iq2000/ChangeLog | 3 - sim/testsuite/sim/iq2000/allinsn.exp | 15 - sim/testsuite/sim/lm32/ChangeLog | 3 - sim/testsuite/sim/lm32/allinsn.exp | 15 - sim/testsuite/sim/m32c/ChangeLog | 10 - sim/testsuite/sim/m32c/allinsn.exp | 16 - sim/testsuite/sim/m32r/ChangeLog | 122 - sim/testsuite/sim/m32r/allinsn.exp | 21 - sim/testsuite/sim/m32r/misc.exp | 21 - sim/testsuite/sim/m68hc11/ChangeLog | 3 - sim/testsuite/sim/m68hc11/allinsn.exp | 15 - sim/testsuite/sim/mcore/ChangeLog | 8 - sim/testsuite/sim/mcore/allinsn.exp | 15 - sim/testsuite/sim/microblaze/ChangeLog | 3 - sim/testsuite/sim/microblaze/allinsn.exp | 15 - sim/testsuite/sim/mips/ChangeLog | 118 - sim/testsuite/sim/mips/basic.exp | 106 - sim/testsuite/sim/mn10300/ChangeLog | 3 - sim/testsuite/sim/mn10300/allinsn.exp | 15 - sim/testsuite/sim/moxie/ChangeLog | 3 - sim/testsuite/sim/moxie/allinsn.exp | 15 - sim/testsuite/sim/msp430/ChangeLog | 17 - sim/testsuite/sim/msp430/allinsn.exp | 15 - sim/testsuite/sim/or1k/ChangeLog | 46 - sim/testsuite/sim/or1k/alltests.exp | 34 - sim/testsuite/sim/pru/ChangeLog | 17 - sim/testsuite/sim/pru/allinsn.exp | 33 - sim/testsuite/sim/sh/ChangeLog | 77 - sim/testsuite/sim/sh/allinsn.exp | 89 - sim/testsuite/sim/v850/ChangeLog | 19 - sim/testsuite/sim/v850/allinsns.exp | 39 - sim/testsuite/v850/ChangeLog | 23 + sim/testsuite/v850/allinsns.exp | 39 + sim/testsuite/{sim => }/v850/bsh.cgs | 0 sim/testsuite/{sim => }/v850/div.cgs | 0 sim/testsuite/{sim => }/v850/divh.cgs | 0 sim/testsuite/{sim => }/v850/divh_3.cgs | 0 sim/testsuite/{sim => }/v850/divhu.cgs | 0 sim/testsuite/{sim => }/v850/divu.cgs | 0 sim/testsuite/{sim => }/v850/sar.cgs | 0 sim/testsuite/{sim => }/v850/satadd.cgs | 0 sim/testsuite/{sim => }/v850/satsub.cgs | 0 sim/testsuite/{sim => }/v850/satsubi.cgs | 0 sim/testsuite/{sim => }/v850/satsubr.cgs | 0 sim/testsuite/{sim => }/v850/shl.cgs | 0 sim/testsuite/{sim => }/v850/shr.cgs | 0 sim/testsuite/{sim => }/v850/testutils.cgs | 0 sim/testsuite/{sim => }/v850/testutils.inc | 0 sim/v850/ChangeLog | 37 +- sim/v850/aclocal.m4 | 41 +- sim/v850/configure | 2921 +--- sim/v850/configure.ac | 3 +- sim/v850/interp.c | 2 - sim/v850/simops.c | 3 +- 4823 files changed, 115291 insertions(+), 146708 deletions(-) create mode 100644 bfd/cpu-riscv.h create mode 100644 binutils/testsuite/binutils-all/pr26548.d create mode 100644 binutils/testsuite/binutils-all/pr26548.s create mode 100644 binutils/testsuite/binutils-all/pr26548e.d delete mode 100644 gas/config/te-symbian.h create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg-7.d create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg-7.l create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg-7.s create mode 100644 gas/testsuite/gas/aarch64/sysreg-7.d create mode 100644 gas/testsuite/gas/aarch64/sysreg-7.s delete mode 100644 gas/testsuite/gas/all/byte.d delete mode 100644 gas/testsuite/gas/all/byte.l delete mode 100644 gas/testsuite/gas/all/byte.s create mode 100644 gas/testsuite/gas/all/pr27381.d create mode 100644 gas/testsuite/gas/all/pr27381.err create mode 100644 gas/testsuite/gas/all/pr27381.s create mode 100644 gas/testsuite/gas/all/pr27384.d create mode 100644 gas/testsuite/gas/all/pr27384.err create mode 100644 gas/testsuite/gas/all/pr27384.s create mode 100644 gas/testsuite/gas/arm/pr27411.d create mode 100644 gas/testsuite/gas/arm/pr27411.l create mode 100644 gas/testsuite/gas/arm/pr27411.s create mode 100644 gas/testsuite/gas/elf/pr27228.d create mode 100644 gas/testsuite/gas/elf/pr27228.s create mode 100644 gas/testsuite/gas/elf/pr27355.d create mode 100644 gas/testsuite/gas/elf/pr27355.err create mode 100644 gas/testsuite/gas/elf/pr27355.s create mode 100644 gas/testsuite/gas/elf/section28.d create mode 100644 gas/testsuite/gas/elf/section28.s create mode 100644 gas/testsuite/gas/elf/section29.d create mode 100644 gas/testsuite/gas/elf/section29.s delete mode 100644 gas/testsuite/gas/elf/warn-2.s create mode 100644 gas/testsuite/gas/i386/nops-8.d create mode 100644 gas/testsuite/gas/i386/nops-8.s create mode 100644 gas/testsuite/gas/i386/pr27198.d create mode 100644 gas/testsuite/gas/i386/pr27198.err create mode 100644 gas/testsuite/gas/i386/pr27198.s create mode 100644 gas/testsuite/gas/i386/property-cvtpi2pd.d create mode 100644 gas/testsuite/gas/i386/property-cvtpi2pd.s create mode 100644 gas/testsuite/gas/i386/property-cvtpi2ps.d create mode 100644 gas/testsuite/gas/i386/property-cvtpi2ps.s create mode 100644 gas/testsuite/gas/i386/property-ldmxcsr.d create mode 100644 gas/testsuite/gas/i386/property-ldmxcsr.s create mode 100644 gas/testsuite/gas/i386/property-vldmxcsr.d create mode 100644 gas/testsuite/gas/i386/property-vldmxcsr.s create mode 100644 gas/testsuite/gas/i386/property-vzeroall.d create mode 100644 gas/testsuite/gas/i386/property-vzeroall.s delete mode 100644 gas/testsuite/gas/i386/x86-64-property-10.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-11.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-12.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-13.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-2.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-3.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-4.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-5.d delete mode 100644 gas/testsuite/gas/i386/x86-64-property-6.d create mode 100644 gas/testsuite/gas/nios2/relax.d create mode 100644 gas/testsuite/gas/nios2/relax.s delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-32.d delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-64.d delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns.s create mode 100644 gas/testsuite/gas/s390/zarch-arch14.d create mode 100644 gas/testsuite/gas/s390/zarch-arch14.s create mode 100644 gdb/ada-exp.h delete mode 100644 gdb/arm-symbian-tdep.c create mode 100644 gdb/c-exp.h create mode 100644 gdb/dwarf2/sect-names.h create mode 100644 gdb/elf-none-tdep.c create mode 100644 gdb/elf-none-tdep.h create mode 100644 gdb/expop.h create mode 100644 gdb/f-exp.h create mode 100644 gdb/gcore-elf.c create mode 100644 gdb/gcore-elf.h create mode 100644 gdb/m2-exp.h create mode 100644 gdb/riscv-none-tdep.c create mode 100644 gdb/rust-exp.h create mode 100644 gdb/testsuite/gdb.ada/assign_arr/target_wrapper.adb create mode 100644 gdb/testsuite/gdb.ada/enums_overload.exp create mode 100644 gdb/testsuite/gdb.ada/enums_overload/enums_overload.adb create mode 100644 gdb/testsuite/gdb.ada/enums_overload/enums_overload.ads create mode 100644 gdb/testsuite/gdb.ada/enums_overload/enums_overload_main.adb create mode 100644 gdb/testsuite/gdb.ada/local-enum.exp create mode 100644 gdb/testsuite/gdb.ada/local-enum/local.adb create mode 100644 gdb/testsuite/gdb.ada/operator_call.exp create mode 100644 gdb/testsuite/gdb.ada/operator_call/opcall.adb create mode 100644 gdb/testsuite/gdb.ada/operator_call/twovecs.adb create mode 100644 gdb/testsuite/gdb.ada/operator_call/twovecs.ads create mode 100644 gdb/testsuite/gdb.arch/amd64-stap-expressions.S create mode 100644 gdb/testsuite/gdb.arch/amd64-stap-expressions.exp create mode 100644 gdb/testsuite/gdb.arch/riscv-default-tdesc.exp create mode 100644 gdb/testsuite/gdb.base/cast-call.c create mode 100644 gdb/testsuite/gdb.base/cast-call.exp create mode 100644 gdb/testsuite/gdb.base/inferior-noarg.c create mode 100644 gdb/testsuite/gdb.base/inferior-noarg.exp create mode 100644 gdb/testsuite/gdb.base/maint-info-sections.exp create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-step-out-of-function-no-stmt.c create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-step-out-of-function-no-stmt.exp create mode 100644 gdb/testsuite/gdb.dwarf2/dwznolink.exp create mode 100644 gdb/testsuite/gdb.dwarf2/loclists-multiple-cus.c create mode 100644 gdb/testsuite/gdb.dwarf2/loclists-multiple-cus.exp create mode 100644 gdb/testsuite/gdb.dwarf2/loclists-sec-offset.c create mode 100644 gdb/testsuite/gdb.dwarf2/loclists-sec-offset.exp create mode 100644 gdb/testsuite/gdb.dwarf2/rnglists-multiple-cus.exp create mode 100644 gdb/testsuite/gdb.dwarf2/rnglists-sec-offset.exp create mode 100644 gdb/testsuite/gdb.fortran/allocated.exp create mode 100644 gdb/testsuite/gdb.fortran/allocated.f90 create mode 100644 gdb/testsuite/gdb.fortran/associated.exp create mode 100644 gdb/testsuite/gdb.fortran/associated.f90 create mode 100644 gdb/testsuite/gdb.fortran/call-no-debug-func.f90 create mode 100644 gdb/testsuite/gdb.fortran/call-no-debug-prog.f90 create mode 100644 gdb/testsuite/gdb.fortran/call-no-debug.exp create mode 100644 gdb/testsuite/gdb.fortran/lbound-ubound.F90 create mode 100644 gdb/testsuite/gdb.fortran/lbound-ubound.exp create mode 100644 gdb/testsuite/gdb.fortran/rank.exp create mode 100644 gdb/testsuite/gdb.fortran/rank.f90 create mode 100644 gdb/testsuite/gdb.fortran/shape.exp create mode 100644 gdb/testsuite/gdb.fortran/shape.f90 create mode 100644 gdb/testsuite/gdb.fortran/size.exp create mode 100644 gdb/testsuite/gdb.fortran/size.f90 create mode 100644 gdb/testsuite/gdb.gdb/python-helper.exp create mode 100644 gdb/testsuite/gdb.python/py-auto-load-chaining-f1.c create mode 100644 gdb/testsuite/gdb.python/py-auto-load-chaining-f1.o-gdb.py create mode 100644 gdb/testsuite/gdb.python/py-auto-load-chaining-f2.c create mode 100644 gdb/testsuite/gdb.python/py-auto-load-chaining-f2.o-gdb.py create mode 100644 gdb/testsuite/gdb.python/py-auto-load-chaining.c create mode 100644 gdb/testsuite/gdb.python/py-auto-load-chaining.exp create mode 100644 gdb/testsuite/gdb.python/tui-window-disabled.c create mode 100644 gdb/testsuite/gdb.python/tui-window-disabled.exp create mode 100644 gdb/testsuite/gdb.python/tui-window-disabled.py create mode 100644 gdb/testsuite/gdb.threads/attach-non-stop.c create mode 100644 gdb/testsuite/gdb.threads/attach-non-stop.exp create mode 100644 gdb/testsuite/gdb.threads/detach-step-over.c create mode 100644 gdb/testsuite/gdb.threads/detach-step-over.exp create mode 100644 gdb/testsuite/gdb.tui/scroll.exp create mode 100644 gdb/tui/tui-location.c create mode 100644 gdb/tui/tui-location.h create mode 100644 gdb/unittests/gdb_tilde_expand-selftests.c create mode 100644 gnulib/import/basename-lgpl.h create mode 100644 gnulib/import/eloop-threshold.h create mode 100644 gnulib/import/free.c create mode 100644 gnulib/import/idx.h delete mode 100644 gnulib/import/localtime-buffer.c delete mode 100644 gnulib/import/localtime-buffer.h create mode 100644 gnulib/import/m4/clock_time.m4 delete mode 100644 gnulib/import/m4/dirname.m4 create mode 100644 gnulib/import/m4/free.m4 delete mode 100644 gnulib/import/m4/inttypes-pri.m4 delete mode 100644 gnulib/import/m4/localtime-buffer.m4 create mode 100644 gnulib/import/m4/pid_t.m4 create mode 100644 gnulib/import/m4/pipe.m4 create mode 100644 gnulib/import/malloc/scratch_buffer_dupfree.c create mode 100644 gnulib/import/pipe.c create mode 100644 include/gdb/sim-riscv.h create mode 100644 intl/plural-config.h delete mode 100644 ld/emulparams/armsymbian.sh create mode 100644 ld/emulparams/x86-report-relative.sh delete mode 100644 ld/scripttempl/armbpabi.sc delete mode 100644 ld/testsuite/ld-arm/symbian-seg1.d delete mode 100644 ld/testsuite/ld-arm/symbian-seg1.s create mode 100644 ld/testsuite/ld-elf/pr27259.d create mode 100644 ld/testsuite/ld-elf/pr27259.s create mode 100644 ld/testsuite/ld-gc/start2.d create mode 100644 ld/testsuite/ld-gc/start2.s create mode 100644 ld/testsuite/ld-gc/start3.d create mode 100644 ld/testsuite/ld-gc/start3.s create mode 100644 ld/testsuite/ld-gc/start4.d create mode 100644 ld/testsuite/ld-gc/start4.s create mode 100644 ld/testsuite/ld-i386/pr27193.dd create mode 100644 ld/testsuite/ld-i386/pr27193a.o.bz2 create mode 100644 ld/testsuite/ld-i386/pr27193b.s create mode 100644 ld/testsuite/ld-i386/report-reloc-1.d create mode 100644 ld/testsuite/ld-i386/report-reloc-1.l create mode 100644 ld/testsuite/ld-i386/report-reloc-1.s create mode 100644 ld/testsuite/ld-pe/reloc.d create mode 100644 ld/testsuite/ld-pe/reloc.s create mode 100644 ld/testsuite/ld-plugin/pr15146.d create mode 100644 ld/testsuite/ld-plugin/pr15146a.c create mode 100644 ld/testsuite/ld-plugin/pr15146b.c copy binutils/testsuite/binutils-all/empty => ld/testsuite/ld-plugin/pr15146c.c (100%) create mode 100644 ld/testsuite/ld-plugin/pr15146d.c create mode 100644 ld/testsuite/ld-plugin/pr27311.d create mode 100644 ld/testsuite/ld-plugin/pr27311.ver create mode 100644 ld/testsuite/ld-plugin/pr27311a.c create mode 100644 ld/testsuite/ld-plugin/pr27311b.c create mode 100644 ld/testsuite/ld-plugin/pr27311c.c create mode 100644 ld/testsuite/ld-plugin/pr27311d.c create mode 100644 ld/testsuite/ld-plugin/pr27441a.c create mode 100644 ld/testsuite/ld-plugin/pr27441b.c create mode 100644 ld/testsuite/ld-plugin/pr27441c.c create mode 100644 ld/testsuite/ld-plugin/pr27441c.d create mode 100644 ld/testsuite/ld-powerpc/aix-largetoc-1-32.d create mode 100644 ld/testsuite/ld-powerpc/aix-largetoc-1-64.d copy ld/testsuite/ld-powerpc/{aix-abs-branch-1.ex => aix-largetoc-1.ex} (100%) create mode 100644 ld/testsuite/ld-powerpc/aix-largetoc-1.s create mode 100644 ld/testsuite/ld-powerpc/aix-tls-reloc-32.d create mode 100644 ld/testsuite/ld-powerpc/aix-tls-reloc-64.d copy ld/testsuite/ld-powerpc/{aix-abs-branch-1.ex => aix-tls-reloc.ex} (100%) create mode 100644 ld/testsuite/ld-powerpc/aix-tls-reloc.s create mode 100644 ld/testsuite/ld-powerpc/aix-tls-section-32.d create mode 100644 ld/testsuite/ld-powerpc/aix-tls-section-64.d copy ld/testsuite/{ld-elf/indirect5.out => ld-powerpc/aix-tls-section.ex} (100%) create mode 100644 ld/testsuite/ld-powerpc/aix-tls-section.s create mode 100644 ld/testsuite/ld-powerpc/startstop.d create mode 100644 ld/testsuite/ld-powerpc/startstop.r create mode 100644 ld/testsuite/ld-powerpc/startstop.s create mode 100644 ld/testsuite/ld-powerpc/weak1.d create mode 100644 ld/testsuite/ld-powerpc/weak1.r create mode 100644 ld/testsuite/ld-powerpc/weak1.s create mode 100644 ld/testsuite/ld-powerpc/weak1so.d create mode 100644 ld/testsuite/ld-powerpc/weak1so.r create mode 100644 ld/testsuite/ld-riscv-elf/restart-relax.d create mode 100644 ld/testsuite/ld-riscv-elf/restart-relax.s create mode 100644 ld/testsuite/ld-x86-64/pe-x86-64-6.obj.bz2 create mode 100644 ld/testsuite/ld-x86-64/pe-x86-64-6.od create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1-x32.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.l create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.s create mode 100644 libctf/NEWS create mode 100644 libctf/testsuite/libctf-lookup/conflicting-type-syms-a.c create mode 100644 libctf/testsuite/libctf-lookup/conflicting-type-syms-b.c create mode 100644 libctf/testsuite/libctf-lookup/conflicting-type-syms.c create mode 100644 libctf/testsuite/libctf-lookup/conflicting-type-syms.lk create mode 100644 libctf/testsuite/libctf-lookup/enum-symbol-obj.lk create mode 100644 libctf/testsuite/libctf-regression/nonstatic-var-section-ld-exe [...] create mode 100644 libctf/testsuite/libctf-regression/nonstatic-var-section-ld-r-ctf.c create mode 100644 libctf/testsuite/libctf-regression/nonstatic-var-section-ld-r.c create mode 100644 libctf/testsuite/libctf-regression/nonstatic-var-section-ld-r.lk create mode 100644 libctf/testsuite/libctf-regression/nonstatic-var-section-ld.c create mode 100644 libctf/testsuite/libctf-regression/nonstatic-var-section-ld.lk create mode 100644 libctf/testsuite/libctf-regression/type-add-unnamed-struct-ctf.c create mode 100644 libctf/testsuite/libctf-regression/type-add-unnamed-struct.c create mode 100644 libctf/testsuite/libctf-regression/type-add-unnamed-struct.lk create mode 100644 libctf/testsuite/libctf-writable/symtypetab-nonlinker-writeout.c create mode 100644 libctf/testsuite/libctf-writable/symtypetab-nonlinker-writeout.lk create mode 100644 sim/Makefile.am create mode 100644 sim/aclocal.m4 delete mode 100644 sim/common/Makefile.in delete mode 100644 sim/common/acinclude.m4 delete mode 100644 sim/common/aclocal.m4 delete mode 100755 sim/common/configure delete mode 100644 sim/common/configure.ac create mode 100755 sim/common/gennltvals.py delete mode 100755 sim/common/gennltvals.sh delete mode 100755 sim/common/gentvals.sh delete mode 100644 sim/configure.tgt delete mode 100644 sim/igen/config.in create mode 100644 sim/m4/sim_ac_common.m4 create mode 100644 sim/m4/sim_ac_option_alignment.m4 create mode 100644 sim/m4/sim_ac_option_assert.m4 create mode 100644 sim/m4/sim_ac_option_bitsize.m4 create mode 100644 sim/m4/sim_ac_option_cgen_maint.m4 create mode 100644 sim/m4/sim_ac_option_default_model.m4 create mode 100644 sim/m4/sim_ac_option_endian.m4 create mode 100644 sim/m4/sim_ac_option_environment.m4 create mode 100644 sim/m4/sim_ac_option_float.m4 create mode 100644 sim/m4/sim_ac_option_hardware.m4 create mode 100644 sim/m4/sim_ac_option_inline.m4 create mode 100644 sim/m4/sim_ac_option_reserved_bits.m4 create mode 100644 sim/m4/sim_ac_option_scache.m4 create mode 100644 sim/m4/sim_ac_option_smp.m4 create mode 100644 sim/m4/sim_ac_option_warnings.m4 create mode 100644 sim/m4/sim_ac_option_xor_endian.m4 create mode 100644 sim/m4/sim_ac_output.m4 create mode 100644 sim/riscv/ChangeLog create mode 100644 sim/riscv/Makefile.in create mode 100644 sim/riscv/aclocal.m4 copy sim/{aarch64 => riscv}/config.in (100%) create mode 100755 sim/riscv/configure create mode 100644 sim/riscv/configure.ac create mode 100644 sim/riscv/interp.c create mode 100644 sim/riscv/machs.c create mode 100644 sim/riscv/machs.h create mode 100644 sim/riscv/model_list.def create mode 100644 sim/riscv/sim-main.c create mode 100644 sim/riscv/sim-main.h delete mode 100644 sim/testsuite/Makefile.in create mode 100644 sim/testsuite/aarch64/ChangeLog rename sim/testsuite/{sim => }/aarch64/adds.s (100%) rename sim/testsuite/{sim => }/aarch64/addv.s (100%) create mode 100644 sim/testsuite/aarch64/allinsn.exp rename sim/testsuite/{sim => }/aarch64/bit.s (100%) rename sim/testsuite/{sim => }/aarch64/cmtst.s (100%) rename sim/testsuite/{sim => }/aarch64/cnt.s (100%) rename sim/testsuite/{sim => }/aarch64/fcmXX.s (100%) rename sim/testsuite/{sim => }/aarch64/fcmp.s (100%) rename sim/testsuite/{sim => }/aarch64/fcsel.s (100%) rename sim/testsuite/{sim => }/aarch64/fcvtl.s (100%) rename sim/testsuite/{sim => }/aarch64/fcvtz.s (100%) rename sim/testsuite/{sim => }/aarch64/fminnm.s (100%) rename sim/testsuite/{sim => }/aarch64/fstur.s (100%) rename sim/testsuite/{sim => }/aarch64/ldn_multiple.s (100%) rename sim/testsuite/{sim => }/aarch64/ldn_single.s (100%) rename sim/testsuite/{sim => }/aarch64/ldnr.s (100%) rename sim/testsuite/{sim => }/aarch64/mla.s (100%) rename sim/testsuite/{sim => }/aarch64/mls.s (100%) rename sim/testsuite/{sim => }/aarch64/mul.s (100%) rename sim/testsuite/{sim => }/aarch64/pass.s (100%) rename sim/testsuite/{sim => }/aarch64/stn_multiple.s (100%) rename sim/testsuite/{sim => }/aarch64/stn_single.s (100%) rename sim/testsuite/{sim => }/aarch64/sumov.s (100%) rename sim/testsuite/{sim => }/aarch64/sumulh.s (100%) rename sim/testsuite/{sim => }/aarch64/tbnz.s (100%) rename sim/testsuite/{sim => }/aarch64/testutils.inc (100%) rename sim/testsuite/{sim => }/aarch64/uzp.s (100%) rename sim/testsuite/{sim => }/aarch64/xtl.s (100%) rename sim/testsuite/{sim => }/aarch64/xtn.s (100%) create mode 100644 sim/testsuite/arm/ChangeLog rename sim/testsuite/{sim => }/arm/adc.cgs (100%) rename sim/testsuite/{sim => }/arm/add.cgs (100%) create mode 100644 sim/testsuite/arm/allinsn.exp rename sim/testsuite/{sim => }/arm/and.cgs (100%) rename sim/testsuite/{sim => }/arm/b.cgs (100%) rename sim/testsuite/{sim => }/arm/bic.cgs (100%) rename sim/testsuite/{sim => }/arm/bl.cgs (100%) rename sim/testsuite/{sim => }/arm/bx.cgs (100%) rename sim/testsuite/{sim => }/arm/cmn.cgs (100%) rename sim/testsuite/{sim => }/arm/cmp.cgs (100%) rename sim/testsuite/{sim => }/arm/eor.cgs (100%) rename sim/testsuite/{sim => }/arm/hello.ms (100%) create mode 100644 sim/testsuite/arm/iwmmxt/iwmmxt.exp rename sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs (100%) rename sim/testsuite/{sim => }/arm/ldm.cgs (100%) rename sim/testsuite/{sim => }/arm/ldr.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrb.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrh.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrsb.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrsh.cgs (100%) rename sim/testsuite/{sim => }/arm/misaligned1.ms (100%) rename sim/testsuite/{sim => }/arm/misaligned2.ms (100%) rename sim/testsuite/{sim => }/arm/misaligned3.ms (100%) create mode 100644 sim/testsuite/arm/misc.exp rename sim/testsuite/{sim => }/arm/mla.cgs (100%) rename sim/testsuite/{sim => }/arm/mov.cgs (100%) rename sim/testsuite/{sim => }/arm/movw-movt.ms (100%) rename sim/testsuite/{sim => }/arm/mrs.cgs (100%) rename sim/testsuite/{sim => }/arm/msr.cgs (100%) rename sim/testsuite/{sim => }/arm/mul.cgs (100%) rename sim/testsuite/{sim => }/arm/mvn.cgs (100%) rename sim/testsuite/{sim => }/arm/orr.cgs (100%) rename sim/testsuite/{sim => }/arm/rsb.cgs (100%) rename sim/testsuite/{sim => }/arm/rsc.cgs (100%) rename sim/testsuite/{sim => }/arm/sbc.cgs (100%) rename sim/testsuite/{sim => }/arm/smlal.cgs (100%) rename sim/testsuite/{sim => }/arm/smull.cgs (100%) rename sim/testsuite/{sim => }/arm/stm.cgs (100%) rename sim/testsuite/{sim => }/arm/str.cgs (100%) rename sim/testsuite/{sim => }/arm/strb.cgs (100%) rename sim/testsuite/{sim => }/arm/strh.cgs (100%) rename sim/testsuite/{sim => }/arm/sub.cgs (100%) rename sim/testsuite/{sim => }/arm/swi.cgs (100%) rename sim/testsuite/{sim => }/arm/swp.cgs (100%) rename sim/testsuite/{sim => }/arm/swpb.cgs (100%) rename sim/testsuite/{sim => }/arm/teq.cgs (100%) rename sim/testsuite/{sim => }/arm/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/thumb/adc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/addi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/addi8.cgs (100%) create mode 100644 sim/testsuite/arm/thumb/allthumb.exp rename sim/testsuite/{sim => }/arm/thumb/and.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/asr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/b.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bcc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bcs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/beq.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bge.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bgt.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bhi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bic.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ble.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bls.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/blt.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bmi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bne.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bpl.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bvc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bvs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmn.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/eor.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldmia.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldsb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldsh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lsl.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lsr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mul.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mvn.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/neg.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/orr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/pop.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/push-lr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/push.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ror.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sbc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/stmia.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sub.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/subi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/subi8.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/swi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/thumb/tst.cgs (100%) rename sim/testsuite/{sim => }/arm/tst.cgs (100%) rename sim/testsuite/{sim => }/arm/umlal.cgs (100%) rename sim/testsuite/{sim => }/arm/umull.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/blx.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/mia.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/miaph.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/miaxy.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/mra.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/testutils.inc (100%) create mode 100644 sim/testsuite/arm/xscale/xscale.exp create mode 100644 sim/testsuite/avr/ChangeLog create mode 100644 sim/testsuite/avr/allinsn.exp rename sim/testsuite/{sim => }/avr/pass.s (100%) rename sim/testsuite/{sim => }/avr/testutils.inc (100%) rename sim/testsuite/{sim => }/bfin/.gitignore (100%) rename sim/testsuite/{sim => }/bfin/10272_small.s (100%) rename sim/testsuite/{sim => }/bfin/10436.s (100%) rename sim/testsuite/{sim => }/bfin/10622.s (100%) rename sim/testsuite/{sim => }/bfin/10742.s (100%) rename sim/testsuite/{sim => }/bfin/10799.s (100%) rename sim/testsuite/{sim => }/bfin/11080.s (100%) rename sim/testsuite/{sim => }/bfin/7641.s (100%) create mode 100644 sim/testsuite/bfin/ChangeLog rename sim/testsuite/{sim => }/bfin/PN_generator.s (100%) rename sim/testsuite/{sim => }/bfin/a0.s (100%) rename sim/testsuite/{sim => }/bfin/a0shift.S (100%) rename sim/testsuite/{sim => }/bfin/a1.s (100%) rename sim/testsuite/{sim => }/bfin/a10.s (100%) rename sim/testsuite/{sim => }/bfin/a11.S (100%) rename sim/testsuite/{sim => }/bfin/a12.s (100%) rename sim/testsuite/{sim => }/bfin/a2.s (100%) rename sim/testsuite/{sim => }/bfin/a20.S (100%) rename sim/testsuite/{sim => }/bfin/a21.s (100%) rename sim/testsuite/{sim => }/bfin/a22.s (100%) rename sim/testsuite/{sim => }/bfin/a23.s (100%) rename sim/testsuite/{sim => }/bfin/a24.s (100%) rename sim/testsuite/{sim => }/bfin/a25.s (100%) rename sim/testsuite/{sim => }/bfin/a26.s (100%) rename sim/testsuite/{sim => }/bfin/a3.s (100%) rename sim/testsuite/{sim => }/bfin/a30.s (100%) rename sim/testsuite/{sim => }/bfin/a4.s (100%) rename sim/testsuite/{sim => }/bfin/a5.s (100%) rename sim/testsuite/{sim => }/bfin/a6.s (100%) rename sim/testsuite/{sim => }/bfin/a7.s (100%) rename sim/testsuite/{sim => }/bfin/a8.s (100%) rename sim/testsuite/{sim => }/bfin/a9.s (100%) rename sim/testsuite/{sim => }/bfin/abs-2.S (100%) rename sim/testsuite/{sim => }/bfin/abs-3.S (100%) rename sim/testsuite/{sim => }/bfin/abs-4.S (100%) rename sim/testsuite/{sim => }/bfin/abs.S (100%) rename sim/testsuite/{sim => }/bfin/abs_acc.s (100%) rename sim/testsuite/{sim => }/bfin/acc-rot.s (100%) rename sim/testsuite/{sim => }/bfin/acp5_19.s (100%) rename sim/testsuite/{sim => }/bfin/acp5_4.s (100%) rename sim/testsuite/{sim => }/bfin/add_imm7.s (100%) rename sim/testsuite/{sim => }/bfin/add_shift.S (100%) rename sim/testsuite/{sim => }/bfin/add_sub_acc.s (100%) rename sim/testsuite/{sim => }/bfin/addsub_flags.S (100%) rename sim/testsuite/{sim => }/bfin/algnbug1.s (100%) rename sim/testsuite/{sim => }/bfin/algnbug2.s (100%) create mode 100644 sim/testsuite/bfin/allinsn.exp rename sim/testsuite/{sim => }/bfin/argc.c (100%) rename sim/testsuite/{sim => }/bfin/ashift.s (100%) rename sim/testsuite/{sim => }/bfin/ashift_flags.s (100%) rename sim/testsuite/{sim => }/bfin/ashift_left.s (100%) rename sim/testsuite/{sim => }/bfin/b0.S (100%) rename sim/testsuite/{sim => }/bfin/b1.s (100%) rename sim/testsuite/{sim => }/bfin/b2.S (100%) rename sim/testsuite/{sim => }/bfin/brcc.s (100%) rename sim/testsuite/{sim => }/bfin/brevadd.s (100%) rename sim/testsuite/{sim => }/bfin/byteop16m.s (100%) rename sim/testsuite/{sim => }/bfin/byteop16p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop1p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop2p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop3p.s (100%) rename sim/testsuite/{sim => }/bfin/byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%) rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%) rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%) rename sim/testsuite/{sim => }/bfin/cc0.s (100%) rename sim/testsuite/{sim => }/bfin/cc1.s (100%) rename sim/testsuite/{sim => }/bfin/cc5.S (100%) rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%) rename sim/testsuite/{sim => }/bfin/cec-ifetch.S (100%) rename sim/testsuite/{sim => }/bfin/cec-multi-pending.S (100%) rename sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-non-operating-env.s (100%) rename sim/testsuite/{sim => }/bfin/cec-raise-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S (100%) rename sim/testsuite/{sim => }/bfin/cec-system-call.S (100%) rename sim/testsuite/{sim => }/bfin/cir.s (100%) rename sim/testsuite/{sim => }/bfin/cir1.s (100%) rename sim/testsuite/{sim => }/bfin/cli-sti.s (100%) rename sim/testsuite/{sim => }/bfin/cmpacc.s (100%) rename sim/testsuite/{sim => }/bfin/cmpdreg.S (100%) rename sim/testsuite/{sim => }/bfin/compare.s (100%) rename sim/testsuite/{sim => }/bfin/conv_enc_gen.s (100%) rename sim/testsuite/{sim => }/bfin/cycles.s (100%) rename sim/testsuite/{sim => }/bfin/d0.s (100%) rename sim/testsuite/{sim => }/bfin/d1.s (100%) rename sim/testsuite/{sim => }/bfin/d2.s (100%) rename sim/testsuite/{sim => }/bfin/dbg_brprd_ntkn_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_brtkn_nprd_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_basic.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_umode.S (100%) rename sim/testsuite/{sim => }/bfin/disalnexcpt_implicit.S (100%) rename sim/testsuite/{sim => }/bfin/div0.s (100%) rename sim/testsuite/{sim => }/bfin/divq.s (100%) rename sim/testsuite/{sim => }/bfin/dotproduct.s (100%) rename sim/testsuite/{sim => }/bfin/dotproduct2.s (100%) rename sim/testsuite/{sim => }/bfin/double_prec_mult.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a4.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a7.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a8.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d0.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d1.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_neg.S (100%) rename sim/testsuite/{sim => }/bfin/dsp_s1.s (100%) rename sim/testsuite/{sim => }/bfin/e0.s (100%) rename sim/testsuite/{sim => }/bfin/edn_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s (100%) rename sim/testsuite/{sim => }/bfin/events.s (100%) rename sim/testsuite/{sim => }/bfin/f221.s (100%) rename sim/testsuite/{sim => }/bfin/fact.s (100%) rename sim/testsuite/{sim => }/bfin/fir.s (100%) rename sim/testsuite/{sim => }/bfin/fsm.s (100%) rename sim/testsuite/{sim => }/bfin/greg2.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-bits.S (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-in.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-out.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-nested.s (100%) rename sim/testsuite/{sim => }/bfin/i0.s (100%) rename sim/testsuite/{sim => }/bfin/iir.s (100%) rename sim/testsuite/{sim => }/bfin/issue103.s (100%) rename sim/testsuite/{sim => }/bfin/issue109.s (100%) rename sim/testsuite/{sim => }/bfin/issue112.s (100%) rename sim/testsuite/{sim => }/bfin/issue113.s (100%) rename sim/testsuite/{sim => }/bfin/issue117.s (100%) rename sim/testsuite/{sim => }/bfin/issue118.s (100%) rename sim/testsuite/{sim => }/bfin/issue119.s (100%) rename sim/testsuite/{sim => }/bfin/issue121.s (100%) rename sim/testsuite/{sim => }/bfin/issue123.s (100%) rename sim/testsuite/{sim => }/bfin/issue124.s (100%) rename sim/testsuite/{sim => }/bfin/issue125.s (100%) rename sim/testsuite/{sim => }/bfin/issue126.s (100%) rename sim/testsuite/{sim => }/bfin/issue127.s (100%) rename sim/testsuite/{sim => }/bfin/issue129.s (100%) rename sim/testsuite/{sim => }/bfin/issue139.S (100%) rename sim/testsuite/{sim => }/bfin/issue140.S (100%) rename sim/testsuite/{sim => }/bfin/issue142.s (100%) rename sim/testsuite/{sim => }/bfin/issue144.s (100%) rename sim/testsuite/{sim => }/bfin/issue146.S (100%) rename sim/testsuite/{sim => }/bfin/issue175.s (100%) rename sim/testsuite/{sim => }/bfin/issue205.s (100%) rename sim/testsuite/{sim => }/bfin/issue257.s (100%) rename sim/testsuite/{sim => }/bfin/issue272.S (100%) rename sim/testsuite/{sim => }/bfin/issue83.s (100%) rename sim/testsuite/{sim => }/bfin/issue89.s (100%) rename sim/testsuite/{sim => }/bfin/l0.s (100%) rename sim/testsuite/{sim => }/bfin/l0shift.s (100%) rename sim/testsuite/{sim => }/bfin/l2_loop.s (100%) rename sim/testsuite/{sim => }/bfin/link-2.s (100%) rename sim/testsuite/{sim => }/bfin/link.s (100%) rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_align.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_default.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S (100%) rename sim/testsuite/{sim => }/bfin/load.s (100%) rename sim/testsuite/{sim => }/bfin/logic.s (100%) rename sim/testsuite/{sim => }/bfin/loop_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/loop_strncpy.s (100%) rename sim/testsuite/{sim => }/bfin/lp0.s (100%) rename sim/testsuite/{sim => }/bfin/lp1.s (100%) rename sim/testsuite/{sim => }/bfin/lsetup.s (100%) rename sim/testsuite/{sim => }/bfin/m0boundary.s (100%) rename sim/testsuite/{sim => }/bfin/m1.S (100%) rename sim/testsuite/{sim => }/bfin/m10.s (100%) rename sim/testsuite/{sim => }/bfin/m11.s (100%) rename sim/testsuite/{sim => }/bfin/m12.s (100%) rename sim/testsuite/{sim => }/bfin/m13.s (100%) rename sim/testsuite/{sim => }/bfin/m14.s (100%) rename sim/testsuite/{sim => }/bfin/m15.s (100%) rename sim/testsuite/{sim => }/bfin/m16.s (100%) rename sim/testsuite/{sim => }/bfin/m17.s (100%) rename sim/testsuite/{sim => }/bfin/m2.s (100%) rename sim/testsuite/{sim => }/bfin/m3.s (100%) rename sim/testsuite/{sim => }/bfin/m4.s (100%) rename sim/testsuite/{sim => }/bfin/m5.s (100%) rename sim/testsuite/{sim => }/bfin/m6.s (100%) rename sim/testsuite/{sim => }/bfin/m7.s (100%) rename sim/testsuite/{sim => }/bfin/m8.s (100%) rename sim/testsuite/{sim => }/bfin/m9.s (100%) rename sim/testsuite/{sim => }/bfin/mac2halfreg.S (100%) rename sim/testsuite/{sim => }/bfin/math.s (100%) rename sim/testsuite/{sim => }/bfin/max_min_flags.s (100%) rename sim/testsuite/{sim => }/bfin/mc_s2.s (100%) rename sim/testsuite/{sim => }/bfin/mdma-32bit-1d-neg-count.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-8bit-1d-neg-count.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-skel.h (100%) rename sim/testsuite/{sim => }/bfin/mem3.s (100%) rename sim/testsuite/{sim => }/bfin/mmr-exception.s (100%) rename sim/testsuite/{sim => }/bfin/move.s (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.10.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5_10.s (100%) rename sim/testsuite/{sim => }/bfin/mult.s (100%) rename sim/testsuite/{sim => }/bfin/neg-2.S (100%) rename sim/testsuite/{sim => }/bfin/neg-3.S (100%) rename sim/testsuite/{sim => }/bfin/neg.S (100%) rename sim/testsuite/{sim => }/bfin/nshift.s (100%) rename sim/testsuite/{sim => }/bfin/pr.s (100%) rename sim/testsuite/{sim => }/bfin/push-pop-multiple.s (100%) rename sim/testsuite/{sim => }/bfin/push-pop.s (100%) rename sim/testsuite/{sim => }/bfin/pushpopreg_1.s (100%) rename sim/testsuite/{sim => }/bfin/quadaddsub.s (100%) rename sim/testsuite/{sim => }/bfin/random_0001.s (100%) rename sim/testsuite/{sim => }/bfin/random_0002.S (100%) rename sim/testsuite/{sim => }/bfin/random_0003.S (100%) rename sim/testsuite/{sim => }/bfin/random_0004.S (100%) rename sim/testsuite/{sim => }/bfin/random_0005.S (100%) rename sim/testsuite/{sim => }/bfin/random_0006.S (100%) rename sim/testsuite/{sim => }/bfin/random_0007.S (100%) rename sim/testsuite/{sim => }/bfin/random_0008.S (100%) rename sim/testsuite/{sim => }/bfin/random_0009.S (100%) rename sim/testsuite/{sim => }/bfin/random_0010.S (100%) rename sim/testsuite/{sim => }/bfin/random_0011.S (100%) rename sim/testsuite/{sim => }/bfin/random_0012.S (100%) rename sim/testsuite/{sim => }/bfin/random_0013.S (100%) rename sim/testsuite/{sim => }/bfin/random_0014.S (100%) rename sim/testsuite/{sim => }/bfin/random_0015.S (100%) rename sim/testsuite/{sim => }/bfin/random_0016.S (100%) rename sim/testsuite/{sim => }/bfin/random_0017.S (100%) rename sim/testsuite/{sim => }/bfin/random_0018.S (100%) rename sim/testsuite/{sim => }/bfin/random_0019.S (100%) rename sim/testsuite/{sim => }/bfin/random_0020.S (100%) rename sim/testsuite/{sim => }/bfin/random_0021.S (100%) rename sim/testsuite/{sim => }/bfin/random_0022.S (100%) rename sim/testsuite/{sim => }/bfin/random_0023.S (100%) rename sim/testsuite/{sim => }/bfin/random_0024.S (100%) rename sim/testsuite/{sim => }/bfin/random_0025.S (100%) rename sim/testsuite/{sim => }/bfin/random_0026.S (100%) rename sim/testsuite/{sim => }/bfin/random_0027.S (100%) rename sim/testsuite/{sim => }/bfin/random_0028.S (100%) rename sim/testsuite/{sim => }/bfin/random_0029.S (100%) rename sim/testsuite/{sim => }/bfin/random_0030.S (100%) rename sim/testsuite/{sim => }/bfin/random_0031.S (100%) rename sim/testsuite/{sim => }/bfin/random_0032.S (100%) rename sim/testsuite/{sim => }/bfin/random_0033.S (100%) rename sim/testsuite/{sim => }/bfin/random_0034.S (100%) rename sim/testsuite/{sim => }/bfin/random_0035.S (100%) rename sim/testsuite/{sim => }/bfin/random_0036.S (100%) rename sim/testsuite/{sim => }/bfin/random_0037.S (100%) rename sim/testsuite/{sim => }/bfin/run-tests.sh (100%) rename sim/testsuite/{sim => }/bfin/s0.s (100%) rename sim/testsuite/{sim => }/bfin/s1.s (100%) rename sim/testsuite/{sim => }/bfin/s10.s (100%) rename sim/testsuite/{sim => }/bfin/s11.s (100%) rename sim/testsuite/{sim => }/bfin/s12.s (100%) rename sim/testsuite/{sim => }/bfin/s13.s (100%) rename sim/testsuite/{sim => }/bfin/s14.s (100%) rename sim/testsuite/{sim => }/bfin/s15.s (100%) rename sim/testsuite/{sim => }/bfin/s16.s (100%) rename sim/testsuite/{sim => }/bfin/s17.s (100%) rename sim/testsuite/{sim => }/bfin/s18.s (100%) rename sim/testsuite/{sim => }/bfin/s19.s (100%) rename sim/testsuite/{sim => }/bfin/s2.s (100%) rename sim/testsuite/{sim => }/bfin/s20.s (100%) create mode 100644 sim/testsuite/bfin/s21.s rename sim/testsuite/{sim => }/bfin/s3.s (100%) rename sim/testsuite/{sim => }/bfin/s30.s (100%) rename sim/testsuite/{sim => }/bfin/s4.s (100%) rename sim/testsuite/{sim => }/bfin/s5.s (100%) rename sim/testsuite/{sim => }/bfin/s6.s (100%) rename sim/testsuite/{sim => }/bfin/s7.s (100%) rename sim/testsuite/{sim => }/bfin/s8.s (100%) rename sim/testsuite/{sim => }/bfin/s9.s (100%) rename sim/testsuite/{sim => }/bfin/saatest.s (100%) rename sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all32bitopcodes.lds (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg0opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg1opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg2opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_allopcodes.h (100%) rename sim/testsuite/{sim => }/bfin/se_brtarget_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui2.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui3.S (100%) rename sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S (100%) rename sim/testsuite/{sim => }/bfin/se_cc_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_cof.S (100%) rename sim/testsuite/{sim => }/bfin/se_event_quad.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_dagprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S (100%) rename sim/testsuite/{sim => }/bfin/se_illegalcombination.S (100%) rename sim/testsuite/{sim => }/bfin/se_kill_wbbr.S (100%) rename sim/testsuite/{sim => }/bfin/se_kills2.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_disable.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_01.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_lr.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S (100%) rename sim/testsuite/{sim => }/bfin/se_lsetup_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S (100%) rename sim/testsuite/{sim => }/bfin/se_more_ret_haz.S (100%) rename sim/testsuite/{sim => }/bfin/se_mv2lp.S (100%) rename sim/testsuite/{sim => }/bfin/se_oneins_zoff.S (100%) rename sim/testsuite/{sim => }/bfin/se_popkill.S (100%) rename sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S (100%) rename sim/testsuite/{sim => }/bfin/se_rets_hazard.s (100%) rename sim/testsuite/{sim => }/bfin/se_rts_rti.S (100%) rename sim/testsuite/{sim => }/bfin/se_ssstep_dagprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_ssync.S (100%) rename sim/testsuite/{sim => }/bfin/se_stall_if2.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction1.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction2.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction3.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction4.S (100%) rename sim/testsuite/{sim => }/bfin/se_usermode_protviol.S (100%) rename sim/testsuite/{sim => }/bfin/seqstat.s (100%) rename sim/testsuite/{sim => }/bfin/sign.s (100%) rename sim/testsuite/{sim => }/bfin/simple0.s (100%) rename sim/testsuite/{sim => }/bfin/sri.s (100%) rename sim/testsuite/{sim => }/bfin/stk.s (100%) rename sim/testsuite/{sim => }/bfin/stk2.s (100%) rename sim/testsuite/{sim => }/bfin/stk3.s (100%) rename sim/testsuite/{sim => }/bfin/stk4.s (100%) rename sim/testsuite/{sim => }/bfin/stk5.s (100%) rename sim/testsuite/{sim => }/bfin/stk6.s (100%) rename sim/testsuite/{sim => }/bfin/syscfg.s (100%) rename sim/testsuite/{sim => }/bfin/tar10622.s (100%) rename sim/testsuite/{sim => }/bfin/test-dma.h (100%) rename sim/testsuite/{sim => }/bfin/test.h (100%) rename sim/testsuite/{sim => }/bfin/testset.s (100%) rename sim/testsuite/{sim => }/bfin/testset2.s (100%) rename sim/testsuite/{sim => }/bfin/testutils.inc (100%) rename sim/testsuite/{sim => }/bfin/unlink.S (100%) rename sim/testsuite/{sim => }/bfin/up0.s (100%) rename sim/testsuite/{sim => }/bfin/usp.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs-2.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs-3.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg-2.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg-3.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg.S (100%) rename sim/testsuite/{sim => }/bfin/vecadd.s (100%) rename sim/testsuite/{sim => }/bfin/vit_max.s (100%) rename sim/testsuite/{sim => }/bfin/vit_max2.s (100%) rename sim/testsuite/{sim => }/bfin/viterbi2.s (100%) rename sim/testsuite/{sim => }/bfin/wtf.s (100%) rename sim/testsuite/{sim => }/bfin/x1.s (100%) rename sim/testsuite/{sim => }/bfin/zcall.s (100%) rename sim/testsuite/{sim => }/bfin/zeroflagrnd.s (100%) create mode 100644 sim/testsuite/bpf/ChangeLog create mode 100644 sim/testsuite/bpf/allinsn.exp rename sim/testsuite/{sim => }/bpf/alu.s (100%) rename sim/testsuite/{sim => }/bpf/alu32.s (100%) rename sim/testsuite/{sim => }/bpf/endbe.s (100%) rename sim/testsuite/{sim => }/bpf/endle.s (100%) rename sim/testsuite/{sim => }/bpf/jmp.s (100%) rename sim/testsuite/{sim => }/bpf/jmp32.s (100%) rename sim/testsuite/{sim => }/bpf/ldabs.s (100%) rename sim/testsuite/{sim => }/bpf/mem.s (100%) rename sim/testsuite/{sim => }/bpf/mov.s (100%) rename sim/testsuite/{sim => }/bpf/testutils.inc (100%) rename sim/testsuite/{sim => }/bpf/xadd.s (100%) delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac create mode 100644 sim/testsuite/cr16/ChangeLog rename sim/testsuite/{sim => }/cr16/addb.cgs (100%) rename sim/testsuite/{sim => }/cr16/addd.cgs (100%) rename sim/testsuite/{sim => }/cr16/addi.cgs (100%) rename sim/testsuite/{sim => }/cr16/addw.cgs (100%) create mode 100644 sim/testsuite/cr16/allinsn.exp rename sim/testsuite/{sim => }/cr16/andb.cgs (100%) rename sim/testsuite/{sim => }/cr16/andd.cgs (100%) rename sim/testsuite/{sim => }/cr16/andw.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashub.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashub_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashud.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashud_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashuw.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashuw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/bal1_24.cgs (100%) rename sim/testsuite/{sim => }/cr16/bal2_24.cgs (100%) rename sim/testsuite/{sim => }/cr16/bcc.cgs (100%) rename sim/testsuite/{sim => }/cr16/bcs.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq0b.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq0w.cgs (100%) rename sim/testsuite/{sim => }/cr16/bge.cgs (100%) rename sim/testsuite/{sim => }/cr16/bgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/bhi.cgs (100%) rename sim/testsuite/{sim => }/cr16/bhs.cgs (100%) rename sim/testsuite/{sim => }/cr16/bht.cgs (100%) rename sim/testsuite/{sim => }/cr16/blo.cgs (100%) rename sim/testsuite/{sim => }/cr16/bls.cgs (100%) rename sim/testsuite/{sim => }/cr16/blt.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne0b.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne0w.cgs (100%) rename sim/testsuite/{sim => }/cr16/br.cgs (100%) rename sim/testsuite/{sim => }/cr16/cbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/cbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpb.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpd.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpi.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpw.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/excp.cgs (100%) rename sim/testsuite/{sim => }/cr16/hello.ms (100%) rename sim/testsuite/{sim => }/cr16/hw-trap.ms (100%) rename sim/testsuite/{sim => }/cr16/jal.cgs (100%) rename sim/testsuite/{sim => }/cr16/jcc.cgs (100%) rename sim/testsuite/{sim => }/cr16/jcs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jeq.cgs (100%) rename sim/testsuite/{sim => }/cr16/jfc.cgs (100%) rename sim/testsuite/{sim => }/cr16/jfs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jge.cgs (100%) rename sim/testsuite/{sim => }/cr16/jgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/jhi.cgs (100%) rename sim/testsuite/{sim => }/cr16/jhs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jlo.cgs (100%) rename sim/testsuite/{sim => }/cr16/jls.cgs (100%) rename sim/testsuite/{sim => }/cr16/jlt.cgs (100%) rename sim/testsuite/{sim => }/cr16/jne.cgs (100%) rename sim/testsuite/{sim => }/cr16/jump.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadb.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadd.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadm.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadmp.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lpr-spr.cgs (100%) rename sim/testsuite/{sim => }/cr16/lprd-sprd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/macqw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macuw.cgs (100%) create mode 100644 sim/testsuite/cr16/misc.exp rename sim/testsuite/{sim => }/cr16/movb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movd.cgs (100%) rename sim/testsuite/{sim => }/cr16/movw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movzb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movzw.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulb.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulsb.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/muluw.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulw.cgs (100%) rename sim/testsuite/{sim => }/cr16/nop.cgs (100%) rename sim/testsuite/{sim => }/cr16/orb.cgs (100%) rename sim/testsuite/{sim => }/cr16/ord.cgs (100%) rename sim/testsuite/{sim => }/cr16/orw.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop1.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop2.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop3.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret1.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret2.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret3.cgs (100%) rename sim/testsuite/{sim => }/cr16/push1.cgs (100%) rename sim/testsuite/{sim => }/cr16/push2.cgs (100%) rename sim/testsuite/{sim => }/cr16/push3.cgs (100%) rename sim/testsuite/{sim => }/cr16/sbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/sbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/scc.cgs (100%) rename sim/testsuite/{sim => }/cr16/scs.cgs (100%) rename sim/testsuite/{sim => }/cr16/seq.cgs (100%) rename sim/testsuite/{sim => }/cr16/sfc.cgs (100%) rename sim/testsuite/{sim => }/cr16/sfs.cgs (100%) rename sim/testsuite/{sim => }/cr16/sge.cgs (100%) rename sim/testsuite/{sim => }/cr16/sgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/shi.cgs (100%) rename sim/testsuite/{sim => }/cr16/shs.cgs (100%) rename sim/testsuite/{sim => }/cr16/slo.cgs (100%) rename sim/testsuite/{sim => }/cr16/sls.cgs (100%) rename sim/testsuite/{sim => }/cr16/slt.cgs (100%) rename sim/testsuite/{sim => }/cr16/sne.cgs (100%) rename sim/testsuite/{sim => }/cr16/storb.cgs (100%) rename sim/testsuite/{sim => }/cr16/stord.cgs (100%) rename sim/testsuite/{sim => }/cr16/storw.cgs (100%) rename sim/testsuite/{sim => }/cr16/subb.cgs (100%) rename sim/testsuite/{sim => }/cr16/subd.cgs (100%) rename sim/testsuite/{sim => }/cr16/subi.cgs (100%) rename sim/testsuite/{sim => }/cr16/subw.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/testutils.inc (100%) rename sim/testsuite/{sim => }/cr16/uread16.ms (100%) rename sim/testsuite/{sim => }/cr16/uread32.ms (100%) rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%) rename sim/testsuite/{sim => }/cr16/xord.cgs (100%) rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%) create mode 100644 sim/testsuite/cris/ChangeLog rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addiv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addoc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addom.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addoq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addswpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andr.ms (100%) create mode 100644 sim/testsuite/cris/asm/asm.exp rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%) rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/break.ms (100%) rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movprv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movprv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movrss.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movscpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movscr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsrpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movssr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movucpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movucr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movum.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movumpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movur.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movurpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%) rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/not.ms (100%) rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/pcplus.ms (100%) rename sim/testsuite/{sim => }/cris/asm/pid1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw11.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw12.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw13.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw14.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw15.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw16.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw17.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ret.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfe.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfn.ms (100%) rename sim/testsuite/{sim => }/cris/asm/sbfs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/scc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/sfe.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/swap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/test.ms (100%) rename sim/testsuite/{sim => }/cris/asm/testutils.inc (100%) rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmemv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmemv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvm1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvm2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/user.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x0-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x0-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x1-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x1-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x10-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x2-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x2-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x3-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x3-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x4-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x5-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x5-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x6-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x6-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x7-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x7-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x8-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x9-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/xor.ms (100%) rename sim/testsuite/{sim => }/cris/c/access1.c (100%) rename sim/testsuite/{sim => }/cris/c/append1.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso1.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso2.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso3.c (100%) create mode 100644 sim/testsuite/cris/c/c.exp rename sim/testsuite/{sim => }/cris/c/clone1.c (100%) rename sim/testsuite/{sim => }/cris/c/clone2.c (100%) rename sim/testsuite/{sim => }/cris/c/clone3.c (100%) rename sim/testsuite/{sim => }/cris/c/clone4.c (100%) rename sim/testsuite/{sim => }/cris/c/clone5.c (100%) rename sim/testsuite/{sim => }/cris/c/clone6.c (100%) rename sim/testsuite/{sim => }/cris/c/ex1.c (100%) rename sim/testsuite/{sim => }/cris/c/exitg1.c (100%) rename sim/testsuite/{sim => }/cris/c/exitg2.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl1.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl2.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/getcwd1.c (100%) rename sim/testsuite/{sim => }/cris/c/gettod.c (100%) rename sim/testsuite/{sim => }/cris/c/hello.c (100%) rename sim/testsuite/{sim => }/cris/c/helloaout.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn2.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn3.c (100%) rename sim/testsuite/{sim => }/cris/c/kill1.c (100%) rename sim/testsuite/{sim => }/cris/c/kill2.c (100%) rename sim/testsuite/{sim => }/cris/c/kill3.c (100%) rename sim/testsuite/{sim => }/cris/c/mapbrk.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap1.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap2.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap3.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap4.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap5.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap6.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap7.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap8.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect1.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect2.c (100%) rename sim/testsuite/{sim => }/cris/c/mremap.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf1.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf2.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf3.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf4.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf5.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe1.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe2.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe3.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe4.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe5.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe6.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe7.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink1.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink10.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink11.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink2.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink3.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink4.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink5.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink6.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink7.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink8.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink9.c (100%) rename sim/testsuite/{sim => }/cris/c/rename2.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c (100%) rename sim/testsuite/{sim => }/cris/c/sched1.c (100%) rename sim/testsuite/{sim => }/cris/c/sched2.c (100%) rename sim/testsuite/{sim => }/cris/c/sched3.c (100%) rename sim/testsuite/{sim => }/cris/c/sched4.c (100%) rename sim/testsuite/{sim => }/cris/c/sched5.c (100%) rename sim/testsuite/{sim => }/cris/c/sched6.c (100%) rename sim/testsuite/{sim => }/cris/c/sched7.c (100%) rename sim/testsuite/{sim => }/cris/c/sched8.c (100%) rename sim/testsuite/{sim => }/cris/c/sched9.c (100%) rename sim/testsuite/{sim => }/cris/c/seek1.c (100%) rename sim/testsuite/{sim => }/cris/c/seek2.c (100%) rename sim/testsuite/{sim => }/cris/c/seek3.c (100%) rename sim/testsuite/{sim => }/cris/c/seek4.c (100%) rename sim/testsuite/{sim => }/cris/c/setrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/settls1.c (100%) rename sim/testsuite/{sim => }/cris/c/sig1.c (100%) rename sim/testsuite/{sim => }/cris/c/sig10.c (100%) rename sim/testsuite/{sim => }/cris/c/sig11.c (100%) rename sim/testsuite/{sim => }/cris/c/sig12.c (100%) rename sim/testsuite/{sim => }/cris/c/sig13.c (100%) rename sim/testsuite/{sim => }/cris/c/sig2.c (100%) rename sim/testsuite/{sim => }/cris/c/sig3.c (100%) rename sim/testsuite/{sim => }/cris/c/sig4.c (100%) rename sim/testsuite/{sim => }/cris/c/sig5.c (100%) rename sim/testsuite/{sim => }/cris/c/sig6.c (100%) rename sim/testsuite/{sim => }/cris/c/sig7.c (100%) rename sim/testsuite/{sim => }/cris/c/sig8.c (100%) rename sim/testsuite/{sim => }/cris/c/sig9.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn1.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn2.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn3.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn4.c (100%) rename sim/testsuite/{sim => }/cris/c/sjlj.c (100%) rename sim/testsuite/{sim => }/cris/c/sock1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat2.c (100%) rename sim/testsuite/{sim => }/cris/c/stat3.c (100%) rename sim/testsuite/{sim => }/cris/c/stat4.c (100%) rename sim/testsuite/{sim => }/cris/c/stat5.c (100%) rename sim/testsuite/{sim => }/cris/c/stat7.c (100%) rename sim/testsuite/{sim => }/cris/c/stat8.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall1.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall2.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall3.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall4.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall5.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall6.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall7.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall8.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl1.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl2.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread2.c (100%) rename sim/testsuite/{sim => }/cris/c/thread3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread4.c (100%) rename sim/testsuite/{sim => }/cris/c/thread5.c (100%) rename sim/testsuite/{sim => }/cris/c/time1.c (100%) rename sim/testsuite/{sim => }/cris/c/time2.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/ugetrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/uname1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev2.c (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s (100%) create mode 100644 sim/testsuite/cris/hw/rv-n-cris/rvc.exp rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/testutils.inc (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial3.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.r (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial5.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms (100%) delete mode 100644 sim/testsuite/d10v-elf/ChangeLog delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/hello.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld-d.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld-i.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld-id.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld-im.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld-ip.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-d.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-i.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-id.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-im.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-ip.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st-d.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st-i.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st-id.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st-im.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st-ip.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st-is.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-d.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-i.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-id.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-im.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-ip.s delete mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-is.s delete mode 100644 sim/testsuite/d10v-elf/t-dbt.s delete mode 100644 sim/testsuite/d10v-elf/t-ld-st.s delete mode 100644 sim/testsuite/d10v-elf/t-mac.s delete mode 100644 sim/testsuite/d10v-elf/t-macros.i delete mode 100644 sim/testsuite/d10v-elf/t-mod-ld-pre.s delete mode 100644 sim/testsuite/d10v-elf/t-msbu.s delete mode 100644 sim/testsuite/d10v-elf/t-mulxu.s delete mode 100644 sim/testsuite/d10v-elf/t-mvtac.s delete mode 100644 sim/testsuite/d10v-elf/t-mvtc.s delete mode 100644 sim/testsuite/d10v-elf/t-rac.s delete mode 100644 sim/testsuite/d10v-elf/t-rachi.s delete mode 100644 sim/testsuite/d10v-elf/t-rdt.s delete mode 100644 sim/testsuite/d10v-elf/t-rep.s delete mode 100644 sim/testsuite/d10v-elf/t-rie-xx.s delete mode 100644 sim/testsuite/d10v-elf/t-rte.s delete mode 100644 sim/testsuite/d10v-elf/t-sac.s delete mode 100644 sim/testsuite/d10v-elf/t-sachi.s delete mode 100644 sim/testsuite/d10v-elf/t-sadd.s delete mode 100644 sim/testsuite/d10v-elf/t-slae.s delete mode 100644 sim/testsuite/d10v-elf/t-sp.s delete mode 100644 sim/testsuite/d10v-elf/t-sub.s delete mode 100644 sim/testsuite/d10v-elf/t-sub2w.s delete mode 100644 sim/testsuite/d10v-elf/t-subi.s delete mode 100644 sim/testsuite/d10v-elf/t-trap.s create mode 100644 sim/testsuite/d10v/ChangeLog create mode 100644 sim/testsuite/d10v/allinsn.exp create mode 100644 sim/testsuite/d10v/exit47.s create mode 100644 sim/testsuite/d10v/hello.s create mode 100644 sim/testsuite/d10v/t-ae-ld-d.s create mode 100644 sim/testsuite/d10v/t-ae-ld-i.s create mode 100644 sim/testsuite/d10v/t-ae-ld-id.s create mode 100644 sim/testsuite/d10v/t-ae-ld-im.s create mode 100644 sim/testsuite/d10v/t-ae-ld-ip.s create mode 100644 sim/testsuite/d10v/t-ae-ld2w-d.s create mode 100644 sim/testsuite/d10v/t-ae-ld2w-i.s create mode 100644 sim/testsuite/d10v/t-ae-ld2w-id.s create mode 100644 sim/testsuite/d10v/t-ae-ld2w-im.s create mode 100644 sim/testsuite/d10v/t-ae-ld2w-ip.s create mode 100644 sim/testsuite/d10v/t-ae-st-d.s create mode 100644 sim/testsuite/d10v/t-ae-st-i.s create mode 100644 sim/testsuite/d10v/t-ae-st-id.s create mode 100644 sim/testsuite/d10v/t-ae-st-im.s create mode 100644 sim/testsuite/d10v/t-ae-st-ip.s create mode 100644 sim/testsuite/d10v/t-ae-st-is.s create mode 100644 sim/testsuite/d10v/t-ae-st2w-d.s create mode 100644 sim/testsuite/d10v/t-ae-st2w-i.s create mode 100644 sim/testsuite/d10v/t-ae-st2w-id.s create mode 100644 sim/testsuite/d10v/t-ae-st2w-im.s create mode 100644 sim/testsuite/d10v/t-ae-st2w-ip.s create mode 100644 sim/testsuite/d10v/t-ae-st2w-is.s create mode 100644 sim/testsuite/d10v/t-dbt.s create mode 100644 sim/testsuite/d10v/t-ld-st.s create mode 100644 sim/testsuite/d10v/t-mac.s create mode 100644 sim/testsuite/d10v/t-macros.i create mode 100644 sim/testsuite/d10v/t-mod-ld-pre.s create mode 100644 sim/testsuite/d10v/t-msbu.s create mode 100644 sim/testsuite/d10v/t-mulxu.s create mode 100644 sim/testsuite/d10v/t-mvtac.s create mode 100644 sim/testsuite/d10v/t-mvtc.s create mode 100644 sim/testsuite/d10v/t-rac.s create mode 100644 sim/testsuite/d10v/t-rachi.s create mode 100644 sim/testsuite/d10v/t-rdt.s create mode 100644 sim/testsuite/d10v/t-rep.s create mode 100644 sim/testsuite/d10v/t-rie-xx.s create mode 100644 sim/testsuite/d10v/t-rte.s create mode 100644 sim/testsuite/d10v/t-sac.s create mode 100644 sim/testsuite/d10v/t-sachi.s create mode 100644 sim/testsuite/d10v/t-sadd.s create mode 100644 sim/testsuite/d10v/t-slae.s create mode 100644 sim/testsuite/d10v/t-sp.s create mode 100644 sim/testsuite/d10v/t-sub.s create mode 100644 sim/testsuite/d10v/t-sub2w.s create mode 100644 sim/testsuite/d10v/t-subi.s create mode 100644 sim/testsuite/d10v/t-trap.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100644 sim/testsuite/frv-elf/cache.s delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/exit47.s delete mode 100644 sim/testsuite/frv-elf/grloop.s delete mode 100644 sim/testsuite/frv-elf/hello.s delete mode 100644 sim/testsuite/frv-elf/loop.s create mode 100644 sim/testsuite/frv/ChangeLog rename sim/testsuite/{sim => }/frv/add.cgs (100%) rename sim/testsuite/{sim => }/frv/add.pcgs (100%) rename sim/testsuite/{sim => }/frv/addcc.cgs (100%) rename sim/testsuite/{sim => }/frv/addi.cgs (100%) rename sim/testsuite/{sim => }/frv/addicc.cgs (100%) rename sim/testsuite/{sim => }/frv/addx.cgs (100%) rename sim/testsuite/{sim => }/frv/addxcc.cgs (100%) rename sim/testsuite/{sim => }/frv/addxi.cgs (100%) rename sim/testsuite/{sim => }/frv/addxicc.cgs (100%) create mode 100644 sim/testsuite/frv/allinsn.exp rename sim/testsuite/{sim => }/frv/and.cgs (100%) rename sim/testsuite/{sim => }/frv/andcc.cgs (100%) rename sim/testsuite/{sim => }/frv/andcr.cgs (100%) rename sim/testsuite/{sim => }/frv/andi.cgs (100%) rename sim/testsuite/{sim => }/frv/andicc.cgs (100%) rename sim/testsuite/{sim => }/frv/andncr.cgs (100%) rename sim/testsuite/{sim => }/frv/bar.cgs (100%) rename sim/testsuite/{sim => }/frv/bc.cgs (100%) rename sim/testsuite/{sim => }/frv/bcclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bceqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bchilr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclslr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcplr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcralr.cgs (100%) rename sim/testsuite/{sim => }/frv/bctrlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/beq.cgs (100%) rename sim/testsuite/{sim => }/frv/beqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bge.cgs (100%) rename sim/testsuite/{sim => }/frv/bgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bgt.cgs (100%) rename sim/testsuite/{sim => }/frv/bgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bhi.cgs (100%) rename sim/testsuite/{sim => }/frv/bhilr.cgs (100%) rename sim/testsuite/{sim => }/frv/ble.cgs (100%) rename sim/testsuite/{sim => }/frv/blelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bls.cgs (100%) rename sim/testsuite/{sim => }/frv/blslr.cgs (100%) rename sim/testsuite/{sim => }/frv/blt.cgs (100%) rename sim/testsuite/{sim => }/frv/bltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bn.cgs (100%) rename sim/testsuite/{sim => }/frv/bnc.cgs (100%) rename sim/testsuite/{sim => }/frv/bnclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bne.cgs (100%) rename sim/testsuite/{sim => }/frv/bnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bnlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bno.cgs (100%) rename sim/testsuite/{sim => }/frv/bnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/bnv.cgs (100%) rename sim/testsuite/{sim => }/frv/bnvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bp.cgs (100%) rename sim/testsuite/{sim => }/frv/bplr.cgs (100%) rename sim/testsuite/{sim => }/frv/bra.cgs (100%) rename sim/testsuite/{sim => }/frv/bralr.cgs (100%) rename sim/testsuite/{sim => }/frv/branch.pcgs (100%) rename sim/testsuite/{sim => }/frv/break.cgs (100%) rename sim/testsuite/{sim => }/frv/bv.cgs (100%) rename sim/testsuite/{sim => }/frv/bvlr.cgs (100%) create mode 100644 sim/testsuite/frv/cache.ms rename sim/testsuite/{sim => }/frv/cadd.cgs (100%) rename sim/testsuite/{sim => }/frv/caddcc.cgs (100%) rename sim/testsuite/{sim => }/frv/call.cgs (100%) rename sim/testsuite/{sim => }/frv/call.pcgs (100%) rename sim/testsuite/{sim => }/frv/callil.cgs (100%) rename sim/testsuite/{sim => }/frv/calll.cgs (100%) rename sim/testsuite/{sim => }/frv/cand.cgs (100%) rename sim/testsuite/{sim => }/frv/candcc.cgs (100%) rename sim/testsuite/{sim => }/frv/ccalll.cgs (100%) rename sim/testsuite/{sim => }/frv/cckc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/cckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cckls.cgs (100%) rename sim/testsuite/{sim => }/frv/ccklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckn.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cckno.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknv.cgs (100%) rename sim/testsuite/{sim => }/frv/cckp.cgs (100%) rename sim/testsuite/{sim => }/frv/cckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cckv.cgs (100%) rename sim/testsuite/{sim => }/frv/ccmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cfabss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcko.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcku.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckue.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckug.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckul.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckule.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/cfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/cfnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/cfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cjmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/ckc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/ckge.cgs (100%) rename sim/testsuite/{sim => }/frv/ckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/ckle.cgs (100%) rename sim/testsuite/{sim => }/frv/ckls.cgs (100%) rename sim/testsuite/{sim => }/frv/cklt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckn.cgs (100%) rename sim/testsuite/{sim => }/frv/cknc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckne.cgs (100%) rename sim/testsuite/{sim => }/frv/ckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cknv.cgs (100%) rename sim/testsuite/{sim => }/frv/ckp.cgs (100%) rename sim/testsuite/{sim => }/frv/ckra.cgs (100%) rename sim/testsuite/{sim => }/frv/ckv.cgs (100%) rename sim/testsuite/{sim => }/frv/cld.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldd.cgs (100%) rename sim/testsuite/{sim => }/frv/clddf.cgs (100%) rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/clddu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldq.cgs (100%) rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldub.cgs (100%) rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/clduh.cgs (100%) rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%) rename sim/testsuite/{sim => }/frv/clrga.cgs (100%) rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmand.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%) rename sim/testsuite/{sim => }/frv/cmor.cgs (100%) rename sim/testsuite/{sim => }/frv/cmov.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cnot.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%) rename sim/testsuite/{sim => }/frv/commitga.cgs (100%) rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cop1.cgs (100%) rename sim/testsuite/{sim => }/frv/cop2.cgs (100%) rename sim/testsuite/{sim => }/frv/cor.cgs (100%) rename sim/testsuite/{sim => }/frv/corcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cscan.cgs (100%) rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/csll.cgs (100%) rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csmul.cgs (100%) rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csra.cgs (100%) rename sim/testsuite/{sim => }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => }/frv/cstu.cgs (100%) rename sim/testsuite/{sim => }/frv/csub.cgs (100%) rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cswap.cgs (100%) rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/cxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/dcef.cgs (100%) rename sim/testsuite/{sim => }/frv/dcei.cgs (100%) rename sim/testsuite/{sim => }/frv/dcf.cgs (100%) rename sim/testsuite/{sim => }/frv/dci.cgs (100%) create mode 100644 sim/testsuite/frv/exit47.ms rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => }/frv/faddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbug.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbul.cgs (100%) rename sim/testsuite/{sim => }/frv/fbule.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fckge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckle.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckne.cgs (100%) rename sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) create mode 100644 sim/testsuite/frv/fr400/allinsn.exp rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) create mode 100644 sim/testsuite/frv/fr500/allinsn.exp rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) create mode 100644 sim/testsuite/frv/fr550/allinsn.exp rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) create mode 100644 sim/testsuite/frv/interrupts.exp rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nld.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldq.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldub.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/nop.cgs (100%) rename sim/testsuite/{sim => }/frv/norcr.cgs (100%) rename sim/testsuite/{sim => }/frv/norncr.cgs (100%) rename sim/testsuite/{sim => }/frv/not.cgs (100%) rename sim/testsuite/{sim => }/frv/notcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%) rename sim/testsuite/{sim => }/frv/or.cgs (100%) rename sim/testsuite/{sim => }/frv/orcc.cgs (100%) rename sim/testsuite/{sim => }/frv/orcr.cgs (100%) rename sim/testsuite/{sim => }/frv/ori.cgs (100%) rename sim/testsuite/{sim => }/frv/oricc.cgs (100%) rename sim/testsuite/{sim => }/frv/orncr.cgs (100%) create mode 100644 sim/testsuite/frv/parallel.exp rename sim/testsuite/{sim => }/frv/ret.cgs (100%) rename sim/testsuite/{sim => }/frv/rett.cgs (100%) rename sim/testsuite/{sim => }/frv/scan.cgs (100%) rename sim/testsuite/{sim => }/frv/scani.cgs (100%) rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethilo.pcgs (100%) rename sim/testsuite/{sim => }/frv/setlo.cgs (100%) rename sim/testsuite/{sim => }/frv/setlos.cgs (100%) rename sim/testsuite/{sim => }/frv/sll.cgs (100%) rename sim/testsuite/{sim => }/frv/sllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/slli.cgs (100%) rename sim/testsuite/{sim => }/frv/sllicc.cgs (100%) rename sim/testsuite/{sim => }/frv/smul.cgs (100%) rename sim/testsuite/{sim => }/frv/smulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/smuli.cgs (100%) rename sim/testsuite/{sim => }/frv/smulicc.cgs (100%) rename sim/testsuite/{sim => }/frv/sra.cgs (100%) rename sim/testsuite/{sim => }/frv/sracc.cgs (100%) rename sim/testsuite/{sim => }/frv/srai.cgs (100%) rename sim/testsuite/{sim => }/frv/sraicc.cgs (100%) rename sim/testsuite/{sim => }/frv/srl.cgs (100%) rename sim/testsuite/{sim => }/frv/srlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/srli.cgs (100%) rename sim/testsuite/{sim => }/frv/srlicc.cgs (100%) rename sim/testsuite/{sim => }/frv/st.cgs (100%) rename sim/testsuite/{sim => }/frv/stb.cgs (100%) rename sim/testsuite/{sim => }/frv/stbf.cgs (100%) rename sim/testsuite/{sim => }/frv/stbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stbi.cgs (100%) rename sim/testsuite/{sim => }/frv/stbu.cgs (100%) rename sim/testsuite/{sim => }/frv/stc.cgs (100%) rename sim/testsuite/{sim => }/frv/stcu.cgs (100%) rename sim/testsuite/{sim => }/frv/std.cgs (100%) rename sim/testsuite/{sim => }/frv/std.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdc.cgs (100%) rename sim/testsuite/{sim => }/frv/stdc.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdcu.cgs (100%) rename sim/testsuite/{sim => }/frv/stdf.cgs (100%) rename sim/testsuite/{sim => }/frv/stdf.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stdi.cgs (100%) rename sim/testsuite/{sim => }/frv/stdu.cgs (100%) rename sim/testsuite/{sim => }/frv/stf.cgs (100%) rename sim/testsuite/{sim => }/frv/stfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stfu.cgs (100%) rename sim/testsuite/{sim => }/frv/sth.cgs (100%) rename sim/testsuite/{sim => }/frv/sthf.cgs (100%) rename sim/testsuite/{sim => }/frv/sthfi.cgs (100%) rename sim/testsuite/{sim => }/frv/sthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/sthi.cgs (100%) rename sim/testsuite/{sim => }/frv/sthu.cgs (100%) rename sim/testsuite/{sim => }/frv/sti.cgs (100%) rename sim/testsuite/{sim => }/frv/stq.cgs (100%) rename sim/testsuite/{sim => }/frv/stq.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqc.cgs (100%) rename sim/testsuite/{sim => }/frv/stqc.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/stqf.cgs (100%) rename sim/testsuite/{sim => }/frv/stqf.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stqi.cgs (100%) rename sim/testsuite/{sim => }/frv/stqu.cgs (100%) rename sim/testsuite/{sim => }/frv/stu.cgs (100%) rename sim/testsuite/{sim => }/frv/sub.cgs (100%) rename sim/testsuite/{sim => }/frv/subcc.cgs (100%) rename sim/testsuite/{sim => }/frv/subi.cgs (100%) rename sim/testsuite/{sim => }/frv/subicc.cgs (100%) rename sim/testsuite/{sim => }/frv/subx.cgs (100%) rename sim/testsuite/{sim => }/frv/subxcc.cgs (100%) rename sim/testsuite/{sim => }/frv/subxi.cgs (100%) rename sim/testsuite/{sim => }/frv/subxicc.cgs (100%) rename sim/testsuite/{sim => }/frv/swap.cgs (100%) rename sim/testsuite/{sim => }/frv/swapi.cgs (100%) rename sim/testsuite/{sim => }/frv/tc.cgs (100%) rename sim/testsuite/{sim => }/frv/teq.cgs (100%) rename sim/testsuite/{sim => }/frv/testutils.inc (100%) rename sim/testsuite/{sim => }/frv/tge.cgs (100%) rename sim/testsuite/{sim => }/frv/tgt.cgs (100%) rename sim/testsuite/{sim => }/frv/thi.cgs (100%) rename sim/testsuite/{sim => }/frv/tic.cgs (100%) rename sim/testsuite/{sim => }/frv/tieq.cgs (100%) rename sim/testsuite/{sim => }/frv/tige.cgs (100%) rename sim/testsuite/{sim => }/frv/tigt.cgs (100%) rename sim/testsuite/{sim => }/frv/tihi.cgs (100%) rename sim/testsuite/{sim => }/frv/tile.cgs (100%) rename sim/testsuite/{sim => }/frv/tils.cgs (100%) rename sim/testsuite/{sim => }/frv/tilt.cgs (100%) rename sim/testsuite/{sim => }/frv/tin.cgs (100%) rename sim/testsuite/{sim => }/frv/tinc.cgs (100%) rename sim/testsuite/{sim => }/frv/tine.cgs (100%) rename sim/testsuite/{sim => }/frv/tino.cgs (100%) rename sim/testsuite/{sim => }/frv/tinv.cgs (100%) rename sim/testsuite/{sim => }/frv/tip.cgs (100%) rename sim/testsuite/{sim => }/frv/tira.cgs (100%) rename sim/testsuite/{sim => }/frv/tiv.cgs (100%) rename sim/testsuite/{sim => }/frv/tle.cgs (100%) rename sim/testsuite/{sim => }/frv/tls.cgs (100%) rename sim/testsuite/{sim => }/frv/tlt.cgs (100%) rename sim/testsuite/{sim => }/frv/tn.cgs (100%) rename sim/testsuite/{sim => }/frv/tnc.cgs (100%) rename sim/testsuite/{sim => }/frv/tne.cgs (100%) rename sim/testsuite/{sim => }/frv/tno.cgs (100%) rename sim/testsuite/{sim => }/frv/tnv.cgs (100%) rename sim/testsuite/{sim => }/frv/tp.cgs (100%) rename sim/testsuite/{sim => }/frv/tra.cgs (100%) rename sim/testsuite/{sim => }/frv/tv.cgs (100%) rename sim/testsuite/{sim => }/frv/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/umul.cgs (100%) rename sim/testsuite/{sim => }/frv/umulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/umuli.cgs (100%) rename sim/testsuite/{sim => }/frv/umulicc.cgs (100%) rename sim/testsuite/{sim => }/frv/xor.cgs (100%) rename sim/testsuite/{sim => }/frv/xorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/xorcr.cgs (100%) rename sim/testsuite/{sim => }/frv/xori.cgs (100%) rename sim/testsuite/{sim => }/frv/xoricc.cgs (100%) create mode 100644 sim/testsuite/ft32/ChangeLog create mode 100644 sim/testsuite/ft32/allinsn.exp rename sim/testsuite/{sim => }/ft32/basic.s (100%) rename sim/testsuite/{sim => }/ft32/testutils.inc (100%) create mode 100644 sim/testsuite/h8300/ChangeLog rename sim/testsuite/{sim => }/h8300/addb.s (100%) rename sim/testsuite/{sim => }/h8300/addl.s (100%) rename sim/testsuite/{sim => }/h8300/adds.s (100%) rename sim/testsuite/{sim => }/h8300/addw.s (100%) rename sim/testsuite/{sim => }/h8300/addx.s (100%) create mode 100644 sim/testsuite/h8300/allinsn.exp rename sim/testsuite/{sim => }/h8300/andb.s (100%) rename sim/testsuite/{sim => }/h8300/andl.s (100%) rename sim/testsuite/{sim => }/h8300/andw.s (100%) rename sim/testsuite/{sim => }/h8300/band.s (100%) rename sim/testsuite/{sim => }/h8300/bfld.s (100%) rename sim/testsuite/{sim => }/h8300/biand.s (100%) rename sim/testsuite/{sim => }/h8300/bra.s (100%) rename sim/testsuite/{sim => }/h8300/brabc.s (100%) rename sim/testsuite/{sim => }/h8300/bset.s (100%) rename sim/testsuite/{sim => }/h8300/cmpb.s (100%) rename sim/testsuite/{sim => }/h8300/cmpl.s (100%) rename sim/testsuite/{sim => }/h8300/cmpw.s (100%) rename sim/testsuite/{sim => }/h8300/daa.s (100%) rename sim/testsuite/{sim => }/h8300/das.s (100%) rename sim/testsuite/{sim => }/h8300/dec.s (100%) rename sim/testsuite/{sim => }/h8300/div.s (100%) rename sim/testsuite/{sim => }/h8300/extl.s (100%) rename sim/testsuite/{sim => }/h8300/extw.s (100%) rename sim/testsuite/{sim => }/h8300/inc.s (100%) rename sim/testsuite/{sim => }/h8300/jmp.s (100%) rename sim/testsuite/{sim => }/h8300/ldc.s (100%) rename sim/testsuite/{sim => }/h8300/ldm.s (100%) rename sim/testsuite/{sim => }/h8300/mac.s (100%) rename sim/testsuite/{sim => }/h8300/mova.s (100%) rename sim/testsuite/{sim => }/h8300/movb.s (100%) rename sim/testsuite/{sim => }/h8300/movl.s (100%) rename sim/testsuite/{sim => }/h8300/movmd.s (100%) rename sim/testsuite/{sim => }/h8300/movsd.s (100%) rename sim/testsuite/{sim => }/h8300/movw.s (100%) rename sim/testsuite/{sim => }/h8300/mul.s (100%) rename sim/testsuite/{sim => }/h8300/neg.s (100%) rename sim/testsuite/{sim => }/h8300/nop.s (100%) rename sim/testsuite/{sim => }/h8300/not.s (100%) rename sim/testsuite/{sim => }/h8300/orb.s (100%) rename sim/testsuite/{sim => }/h8300/orl.s (100%) rename sim/testsuite/{sim => }/h8300/orw.s (100%) rename sim/testsuite/{sim => }/h8300/rotl.s (100%) rename sim/testsuite/{sim => }/h8300/rotr.s (100%) rename sim/testsuite/{sim => }/h8300/rotxl.s (100%) rename sim/testsuite/{sim => }/h8300/rotxr.s (100%) rename sim/testsuite/{sim => }/h8300/shal.s (100%) rename sim/testsuite/{sim => }/h8300/shar.s (100%) rename sim/testsuite/{sim => }/h8300/shll.s (100%) rename sim/testsuite/{sim => }/h8300/shlr.s (100%) rename sim/testsuite/{sim => }/h8300/stack.s (100%) rename sim/testsuite/{sim => }/h8300/stc.s (100%) rename sim/testsuite/{sim => }/h8300/subb.s (100%) rename sim/testsuite/{sim => }/h8300/subl.s (100%) rename sim/testsuite/{sim => }/h8300/subs.s (100%) rename sim/testsuite/{sim => }/h8300/subw.s (100%) rename sim/testsuite/{sim => }/h8300/subx.s (100%) rename sim/testsuite/{sim => }/h8300/tas.s (100%) rename sim/testsuite/{sim => }/h8300/testutils.inc (100%) rename sim/testsuite/{sim => }/h8300/xorb.s (100%) rename sim/testsuite/{sim => }/h8300/xorl.s (100%) rename sim/testsuite/{sim => }/h8300/xorw.s (100%) create mode 100644 sim/testsuite/iq2000/ChangeLog create mode 100644 sim/testsuite/iq2000/allinsn.exp rename sim/testsuite/{sim => }/iq2000/pass.s (100%) rename sim/testsuite/{sim => }/iq2000/testutils.inc (100%) create mode 100644 sim/testsuite/lm32/ChangeLog create mode 100644 sim/testsuite/lm32/allinsn.exp rename sim/testsuite/{sim => }/lm32/pass.s (100%) rename sim/testsuite/{sim => }/lm32/testutils.inc (100%) create mode 100644 sim/testsuite/local.mk create mode 100644 sim/testsuite/m32c/ChangeLog create mode 100644 sim/testsuite/m32c/allinsn.exp rename sim/testsuite/{sim => }/m32c/blinky.s (100%) rename sim/testsuite/{sim => }/m32c/fail.s (100%) rename sim/testsuite/{sim => }/m32c/gloss.s (100%) rename sim/testsuite/{sim => }/m32c/pass.s (100%) rename sim/testsuite/{sim => }/m32c/sample.ld (100%) rename sim/testsuite/{sim => }/m32c/sample.s (100%) rename sim/testsuite/{sim => }/m32c/sample2.c (100%) rename sim/testsuite/{sim => }/m32c/testutils.inc (100%) delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/exit47.s delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s create mode 100644 sim/testsuite/m32r/ChangeLog rename sim/testsuite/{sim => }/m32r/add.cgs (100%) rename sim/testsuite/{sim => }/m32r/add3.cgs (100%) rename sim/testsuite/{sim => }/m32r/addi.cgs (100%) rename sim/testsuite/{sim => }/m32r/addv.cgs (100%) rename sim/testsuite/{sim => }/m32r/addv3.cgs (100%) rename sim/testsuite/{sim => }/m32r/addx.cgs (100%) create mode 100644 sim/testsuite/m32r/allinsn.exp rename sim/testsuite/{sim => }/m32r/and.cgs (100%) rename sim/testsuite/{sim => }/m32r/and3.cgs (100%) rename sim/testsuite/{sim => }/m32r/bc24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bc8.cgs (100%) rename sim/testsuite/{sim => }/m32r/beq.cgs (100%) rename sim/testsuite/{sim => }/m32r/beqz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bgez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bgtz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bl24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bl8.cgs (100%) rename sim/testsuite/{sim => }/m32r/blez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bltz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnc24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnc8.cgs (100%) rename sim/testsuite/{sim => }/m32r/bne.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bra24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bra8.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmp.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpi.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpu.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpui.cgs (100%) rename sim/testsuite/{sim => }/m32r/div.cgs (100%) rename sim/testsuite/{sim => }/m32r/divu.cgs (100%) create mode 100644 sim/testsuite/m32r/exit47.ms rename sim/testsuite/{sim => }/m32r/hello.ms (100%) rename sim/testsuite/{sim => }/m32r/hw-trap.ms (100%) rename sim/testsuite/{sim => }/m32r/jl.cgs (100%) rename sim/testsuite/{sim => }/m32r/jmp.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld-plus.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld24.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldb-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldb.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldh-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldh.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldi16.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldi8.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldub-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldub.cgs (100%) rename sim/testsuite/{sim => }/m32r/lduh-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/lduh.cgs (100%) rename sim/testsuite/{sim => }/m32r/lock.cgs (100%) rename sim/testsuite/{sim => }/m32r/machi.cgs (100%) rename sim/testsuite/{sim => }/m32r/maclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/macwhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/macwlo.cgs (100%) create mode 100644 sim/testsuite/m32r/misc.exp rename sim/testsuite/{sim => }/m32r/mul.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mullo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulwhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulwlo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mv.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfachi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfaclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfacmi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfc.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtachi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtaclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtc.cgs (100%) rename sim/testsuite/{sim => }/m32r/neg.cgs (100%) rename sim/testsuite/{sim => }/m32r/nop.cgs (100%) rename sim/testsuite/{sim => }/m32r/not.cgs (100%) rename sim/testsuite/{sim => }/m32r/or.cgs (100%) rename sim/testsuite/{sim => }/m32r/or3.cgs (100%) rename sim/testsuite/{sim => }/m32r/rac.cgs (100%) rename sim/testsuite/{sim => }/m32r/rach.cgs (100%) rename sim/testsuite/{sim => }/m32r/rem.cgs (100%) rename sim/testsuite/{sim => }/m32r/remu.cgs (100%) rename sim/testsuite/{sim => }/m32r/rte.cgs (100%) rename sim/testsuite/{sim => }/m32r/seth.cgs (100%) rename sim/testsuite/{sim => }/m32r/sll.cgs (100%) rename sim/testsuite/{sim => }/m32r/sll3.cgs (100%) rename sim/testsuite/{sim => }/m32r/slli.cgs (100%) rename sim/testsuite/{sim => }/m32r/sra.cgs (100%) rename sim/testsuite/{sim => }/m32r/sra3.cgs (100%) rename sim/testsuite/{sim => }/m32r/srai.cgs (100%) rename sim/testsuite/{sim => }/m32r/srl.cgs (100%) rename sim/testsuite/{sim => }/m32r/srl3.cgs (100%) rename sim/testsuite/{sim => }/m32r/srli.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-minus.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-plus.cgs (100%) rename sim/testsuite/{sim => }/m32r/st.cgs (100%) rename sim/testsuite/{sim => }/m32r/stb-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/stb.cgs (100%) rename sim/testsuite/{sim => }/m32r/sth-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/sth.cgs (100%) rename sim/testsuite/{sim => }/m32r/sub.cgs (100%) rename sim/testsuite/{sim => }/m32r/subv.cgs (100%) rename sim/testsuite/{sim => }/m32r/subx.cgs (100%) rename sim/testsuite/{sim => }/m32r/testutils.inc (100%) rename sim/testsuite/{sim => }/m32r/trap.cgs (100%) rename sim/testsuite/{sim => }/m32r/unlock.cgs (100%) rename sim/testsuite/{sim => }/m32r/uread16.ms (100%) rename sim/testsuite/{sim => }/m32r/uread32.ms (100%) rename sim/testsuite/{sim => }/m32r/uwrite16.ms (100%) rename sim/testsuite/{sim => }/m32r/uwrite32.ms (100%) rename sim/testsuite/{sim => }/m32r/xor.cgs (100%) rename sim/testsuite/{sim => }/m32r/xor3.cgs (100%) create mode 100644 sim/testsuite/m68hc11/ChangeLog create mode 100644 sim/testsuite/m68hc11/allinsn.exp rename sim/testsuite/{sim => }/m68hc11/pass.s (100%) rename sim/testsuite/{sim => }/m68hc11/testutils.inc (100%) create mode 100644 sim/testsuite/mcore/ChangeLog create mode 100644 sim/testsuite/mcore/allinsn.exp rename sim/testsuite/{sim => }/mcore/fail.s (100%) rename sim/testsuite/{sim => }/mcore/pass.s (100%) rename sim/testsuite/{sim => }/mcore/testutils.inc (100%) create mode 100644 sim/testsuite/microblaze/ChangeLog create mode 100644 sim/testsuite/microblaze/allinsn.exp rename sim/testsuite/{sim => }/microblaze/pass.s (100%) rename sim/testsuite/{sim => }/microblaze/testutils.inc (100%) create mode 100644 sim/testsuite/mips/ChangeLog create mode 100644 sim/testsuite/mips/basic.exp rename sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s (100%) rename sim/testsuite/{sim => }/mips/fpu64-ps.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-1.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-2.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-3.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-4.s (100%) rename sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s (100%) rename sim/testsuite/{sim => }/mips/mdmx-ob.s (100%) rename sim/testsuite/{sim => }/mips/mips32-dsp.s (100%) rename sim/testsuite/{sim => }/mips/mips32-dsp2.s (100%) rename sim/testsuite/{sim => }/mips/sanity.s (100%) rename sim/testsuite/{sim => }/mips/testutils.inc (100%) rename sim/testsuite/{sim => }/mips/utils-dsp.inc (100%) rename sim/testsuite/{sim => }/mips/utils-fpu.inc (100%) rename sim/testsuite/{sim => }/mips/utils-mdmx.inc (100%) delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac create mode 100644 sim/testsuite/mn10300/ChangeLog create mode 100644 sim/testsuite/mn10300/allinsn.exp rename sim/testsuite/{sim => }/mn10300/pass.s (100%) rename sim/testsuite/{sim => }/mn10300/testutils.inc (100%) create mode 100644 sim/testsuite/moxie/ChangeLog create mode 100644 sim/testsuite/moxie/allinsn.exp rename sim/testsuite/{sim => }/moxie/pass.s (100%) rename sim/testsuite/{sim => }/moxie/testutils.inc (100%) create mode 100644 sim/testsuite/msp430/ChangeLog rename sim/testsuite/{sim => }/msp430/add.s (100%) create mode 100644 sim/testsuite/msp430/allinsn.exp rename sim/testsuite/{sim => }/msp430/mpyull_hwmult.s (100%) rename sim/testsuite/{sim => }/msp430/rrux.s (100%) rename sim/testsuite/{sim => }/msp430/testutils.inc (100%) create mode 100644 sim/testsuite/or1k/ChangeLog rename sim/testsuite/{sim => }/or1k/add.S (100%) rename sim/testsuite/{sim => }/or1k/adrp.S (100%) create mode 100644 sim/testsuite/or1k/alltests.exp rename sim/testsuite/{sim => }/or1k/and.S (100%) rename sim/testsuite/{sim => }/or1k/basic.S (100%) rename sim/testsuite/{sim => }/or1k/div.S (100%) rename sim/testsuite/{sim => }/or1k/ext.S (100%) rename sim/testsuite/{sim => }/or1k/find.S (100%) rename sim/testsuite/{sim => }/or1k/flag.S (100%) rename sim/testsuite/{sim => }/or1k/fpu-unordered.S (100%) rename sim/testsuite/{sim => }/or1k/fpu.S (100%) rename sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S (100%) rename sim/testsuite/{sim => }/or1k/fpu64a32.S (100%) rename sim/testsuite/{sim => }/or1k/jump.S (100%) rename sim/testsuite/{sim => }/or1k/load.S (100%) rename sim/testsuite/{sim => }/or1k/mac.S (100%) rename sim/testsuite/{sim => }/or1k/mfspr.S (100%) rename sim/testsuite/{sim => }/or1k/mul.S (100%) rename sim/testsuite/{sim => }/or1k/or.S (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test-helpers.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-test.ld (100%) rename sim/testsuite/{sim => }/or1k/ror.S (100%) rename sim/testsuite/{sim => }/or1k/shift.S (100%) rename sim/testsuite/{sim => }/or1k/spr-defs.h (100%) rename sim/testsuite/{sim => }/or1k/sub.S (100%) rename sim/testsuite/{sim => }/or1k/xor.S (100%) create mode 100644 sim/testsuite/pru/ChangeLog rename sim/testsuite/{sim => }/pru/add.s (100%) create mode 100644 sim/testsuite/pru/allinsn.exp rename sim/testsuite/{sim => }/pru/dmem-zero-pass.s (100%) rename sim/testsuite/{sim => }/pru/dmem-zero-trap.s (100%) rename sim/testsuite/{sim => }/pru/dram.s (100%) rename sim/testsuite/{sim => }/pru/jmp.s (100%) rename sim/testsuite/{sim => }/pru/lmbd.s (100%) rename sim/testsuite/{sim => }/pru/loop-imm.s (100%) rename sim/testsuite/{sim => }/pru/loop-reg.s (100%) rename sim/testsuite/{sim => }/pru/mul.s (100%) rename sim/testsuite/{sim => }/pru/subreg.s (100%) rename sim/testsuite/{sim => }/pru/testutils.inc (100%) create mode 100644 sim/testsuite/riscv/ChangeLog create mode 100644 sim/testsuite/riscv/allinsn.exp create mode 100644 sim/testsuite/riscv/pass.s create mode 100644 sim/testsuite/riscv/testutils.inc create mode 100644 sim/testsuite/sh/ChangeLog rename sim/testsuite/{sim => }/sh/add.s (100%) create mode 100644 sim/testsuite/sh/allinsn.exp rename sim/testsuite/{sim => }/sh/and.s (100%) rename sim/testsuite/{sim => }/sh/bandor.s (100%) rename sim/testsuite/{sim => }/sh/bandornot.s (100%) rename sim/testsuite/{sim => }/sh/bclr.s (100%) rename sim/testsuite/{sim => }/sh/bld.s (100%) rename sim/testsuite/{sim => }/sh/bldnot.s (100%) rename sim/testsuite/{sim => }/sh/bset.s (100%) rename sim/testsuite/{sim => }/sh/bst.s (100%) rename sim/testsuite/{sim => }/sh/bxor.s (100%) rename sim/testsuite/{sim => }/sh/clip.s (100%) rename sim/testsuite/{sim => }/sh/div.s (100%) rename sim/testsuite/{sim => }/sh/dmxy.s (100%) rename sim/testsuite/{sim => }/sh/fabs.s (100%) rename sim/testsuite/{sim => }/sh/fadd.s (100%) rename sim/testsuite/{sim => }/sh/fail.s (100%) rename sim/testsuite/{sim => }/sh/fcmpeq.s (100%) rename sim/testsuite/{sim => }/sh/fcmpgt.s (100%) rename sim/testsuite/{sim => }/sh/fcnvds.s (100%) rename sim/testsuite/{sim => }/sh/fcnvsd.s (100%) rename sim/testsuite/{sim => }/sh/fdiv.s (100%) rename sim/testsuite/{sim => }/sh/fipr.s (100%) rename sim/testsuite/{sim => }/sh/fldi0.s (100%) rename sim/testsuite/{sim => }/sh/fldi1.s (100%) rename sim/testsuite/{sim => }/sh/flds.s (100%) rename sim/testsuite/{sim => }/sh/float.s (100%) rename sim/testsuite/{sim => }/sh/fmac.s (100%) rename sim/testsuite/{sim => }/sh/fmov.s (100%) rename sim/testsuite/{sim => }/sh/fmul.s (100%) rename sim/testsuite/{sim => }/sh/fneg.s (100%) rename sim/testsuite/{sim => }/sh/fpchg.s (100%) rename sim/testsuite/{sim => }/sh/frchg.s (100%) rename sim/testsuite/{sim => }/sh/fsca.s (100%) rename sim/testsuite/{sim => }/sh/fschg.s (100%) rename sim/testsuite/{sim => }/sh/fsqrt.s (100%) rename sim/testsuite/{sim => }/sh/fsrra.s (100%) rename sim/testsuite/{sim => }/sh/fsub.s (100%) rename sim/testsuite/{sim => }/sh/ftrc.s (100%) rename sim/testsuite/{sim => }/sh/ldrc.s (100%) rename sim/testsuite/{sim => }/sh/loop.s (100%) rename sim/testsuite/{sim => }/sh/macl.s (100%) rename sim/testsuite/{sim => }/sh/macw.s (100%) rename sim/testsuite/{sim => }/sh/mov.s (100%) rename sim/testsuite/{sim => }/sh/movi.s (100%) rename sim/testsuite/{sim => }/sh/movli.s (100%) rename sim/testsuite/{sim => }/sh/movua.s (100%) rename sim/testsuite/{sim => }/sh/movxy.s (100%) rename sim/testsuite/{sim => }/sh/mulr.s (100%) rename sim/testsuite/{sim => }/sh/pabs.s (100%) rename sim/testsuite/{sim => }/sh/padd.s (100%) rename sim/testsuite/{sim => }/sh/paddc.s (100%) rename sim/testsuite/{sim => }/sh/pand.s (100%) rename sim/testsuite/{sim => }/sh/pass.s (100%) rename sim/testsuite/{sim => }/sh/pclr.s (100%) rename sim/testsuite/{sim => }/sh/pdec.s (100%) rename sim/testsuite/{sim => }/sh/pdmsb.s (100%) rename sim/testsuite/{sim => }/sh/pinc.s (100%) rename sim/testsuite/{sim => }/sh/pmuls.s (100%) rename sim/testsuite/{sim => }/sh/prnd.s (100%) rename sim/testsuite/{sim => }/sh/pshai.s (100%) rename sim/testsuite/{sim => }/sh/pshar.s (100%) rename sim/testsuite/{sim => }/sh/pshli.s (100%) rename sim/testsuite/{sim => }/sh/pshlr.s (100%) rename sim/testsuite/{sim => }/sh/psub.s (100%) rename sim/testsuite/{sim => }/sh/pswap.s (100%) rename sim/testsuite/{sim => }/sh/pushpop.s (100%) rename sim/testsuite/{sim => }/sh/resbank.s (100%) rename sim/testsuite/{sim => }/sh/sett.s (100%) rename sim/testsuite/{sim => }/sh/shll.s (100%) rename sim/testsuite/{sim => }/sh/shll16.s (100%) rename sim/testsuite/{sim => }/sh/shll2.s (100%) rename sim/testsuite/{sim => }/sh/shll8.s (100%) rename sim/testsuite/{sim => }/sh/shlr.s (100%) rename sim/testsuite/{sim => }/sh/shlr16.s (100%) rename sim/testsuite/{sim => }/sh/shlr2.s (100%) rename sim/testsuite/{sim => }/sh/shlr8.s (100%) rename sim/testsuite/{sim => }/sh/swap.s (100%) rename sim/testsuite/{sim => }/sh/testutils.inc (100%) delete mode 100644 sim/testsuite/sim/aarch64/ChangeLog delete mode 100644 sim/testsuite/sim/aarch64/allinsn.exp delete mode 100644 sim/testsuite/sim/arm/ChangeLog delete mode 100644 sim/testsuite/sim/arm/allinsn.exp delete mode 100644 sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp delete mode 100644 sim/testsuite/sim/arm/misc.exp delete mode 100644 sim/testsuite/sim/arm/thumb/allthumb.exp delete mode 100644 sim/testsuite/sim/arm/xscale/xscale.exp delete mode 100644 sim/testsuite/sim/avr/ChangeLog delete mode 100644 sim/testsuite/sim/avr/allinsn.exp delete mode 100644 sim/testsuite/sim/bfin/ChangeLog delete mode 100644 sim/testsuite/sim/bfin/allinsn.exp delete mode 100644 sim/testsuite/sim/bfin/s21.s delete mode 100644 sim/testsuite/sim/bpf/ChangeLog delete mode 100644 sim/testsuite/sim/bpf/allinsn.exp delete mode 100644 sim/testsuite/sim/cr16/ChangeLog delete mode 100644 sim/testsuite/sim/cr16/allinsn.exp delete mode 100644 sim/testsuite/sim/cr16/misc.exp delete mode 100644 sim/testsuite/sim/cris/ChangeLog delete mode 100644 sim/testsuite/sim/cris/asm/asm.exp delete mode 100644 sim/testsuite/sim/cris/c/c.exp delete mode 100644 sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp delete mode 100644 sim/testsuite/sim/frv/ChangeLog delete mode 100644 sim/testsuite/sim/frv/allinsn.exp delete mode 100644 sim/testsuite/sim/frv/fr400/allinsn.exp delete mode 100644 sim/testsuite/sim/frv/fr500/allinsn.exp delete mode 100644 sim/testsuite/sim/frv/fr550/allinsn.exp delete mode 100644 sim/testsuite/sim/frv/interrupts.exp delete mode 100644 sim/testsuite/sim/frv/parallel.exp delete mode 100644 sim/testsuite/sim/ft32/ChangeLog delete mode 100644 sim/testsuite/sim/ft32/allinsn.exp delete mode 100644 sim/testsuite/sim/h8300/ChangeLog delete mode 100644 sim/testsuite/sim/h8300/allinsn.exp delete mode 100644 sim/testsuite/sim/iq2000/ChangeLog delete mode 100644 sim/testsuite/sim/iq2000/allinsn.exp delete mode 100644 sim/testsuite/sim/lm32/ChangeLog delete mode 100644 sim/testsuite/sim/lm32/allinsn.exp delete mode 100644 sim/testsuite/sim/m32c/ChangeLog delete mode 100644 sim/testsuite/sim/m32c/allinsn.exp delete mode 100644 sim/testsuite/sim/m32r/ChangeLog delete mode 100644 sim/testsuite/sim/m32r/allinsn.exp delete mode 100644 sim/testsuite/sim/m32r/misc.exp delete mode 100644 sim/testsuite/sim/m68hc11/ChangeLog delete mode 100644 sim/testsuite/sim/m68hc11/allinsn.exp delete mode 100644 sim/testsuite/sim/mcore/ChangeLog delete mode 100644 sim/testsuite/sim/mcore/allinsn.exp delete mode 100644 sim/testsuite/sim/microblaze/ChangeLog delete mode 100644 sim/testsuite/sim/microblaze/allinsn.exp delete mode 100644 sim/testsuite/sim/mips/ChangeLog delete mode 100644 sim/testsuite/sim/mips/basic.exp delete mode 100644 sim/testsuite/sim/mn10300/ChangeLog delete mode 100644 sim/testsuite/sim/mn10300/allinsn.exp delete mode 100644 sim/testsuite/sim/moxie/ChangeLog delete mode 100644 sim/testsuite/sim/moxie/allinsn.exp delete mode 100644 sim/testsuite/sim/msp430/ChangeLog delete mode 100644 sim/testsuite/sim/msp430/allinsn.exp delete mode 100644 sim/testsuite/sim/or1k/ChangeLog delete mode 100644 sim/testsuite/sim/or1k/alltests.exp delete mode 100644 sim/testsuite/sim/pru/ChangeLog delete mode 100644 sim/testsuite/sim/pru/allinsn.exp delete mode 100644 sim/testsuite/sim/sh/ChangeLog delete mode 100644 sim/testsuite/sim/sh/allinsn.exp delete mode 100644 sim/testsuite/sim/v850/ChangeLog delete mode 100644 sim/testsuite/sim/v850/allinsns.exp create mode 100644 sim/testsuite/v850/ChangeLog create mode 100644 sim/testsuite/v850/allinsns.exp rename sim/testsuite/{sim => }/v850/bsh.cgs (100%) rename sim/testsuite/{sim => }/v850/div.cgs (100%) rename sim/testsuite/{sim => }/v850/divh.cgs (100%) rename sim/testsuite/{sim => }/v850/divh_3.cgs (100%) rename sim/testsuite/{sim => }/v850/divhu.cgs (100%) rename sim/testsuite/{sim => }/v850/divu.cgs (100%) rename sim/testsuite/{sim => }/v850/sar.cgs (100%) rename sim/testsuite/{sim => }/v850/satadd.cgs (100%) rename sim/testsuite/{sim => }/v850/satsub.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubi.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubr.cgs (100%) rename sim/testsuite/{sim => }/v850/shl.cgs (100%) rename sim/testsuite/{sim => }/v850/shr.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.inc (100%)