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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-allyesconfig in repository toolchain/ci/qemu.

from 4ba2565831 Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/q [...] adds a17ec44dba tests: improve error message when saving TLS PSK file fails adds dcd23e9cae tests: support QTEST_TRACE env variable adds 0c2b6c85c9 tests: print newline after QMP response in qtest logs adds 4b2bbca7a0 migration: fix use of TLS PSK credentials with a UNIX socket adds 19da6edfe8 tests: switch MigrateStart struct to be stack allocated adds ffed54f6e5 tests: merge code for UNIX and TCP migration pre-copy tests adds b3caa7b55e tests: introduce ability to provide hooks for migration prec [...] adds 243e006686 tests: switch migration FD passing test to use common precop [...] adds 00fbe7f6ad tests: expand the migration precopy helper to support failures adds 83174765da migration: Postpone releasing MigrationState.hostname adds 7f692ec79a migration: Drop multifd tls_hostname cache adds ea2faf0c35 migration: Add pss.postcopy_requested status adds f444eeda71 migration: Move migrate_allow_multifd and helpers into migration.c adds 929068ec2f migration: Export ram_load_postcopy() adds a39e933962 migration: Move channel setup out of postcopy_try_recover() adds 08401c0426 migration: Allow migrate-recover to run multiple times adds f912ec5b2d migration: Fix operator type adds 552de79bfd migration: Read state once adds a74782936d Merge tag 'pull-migration-20220421a' of https://gitlab.com/d [...] adds 9c4888c995 hw/ssi: Add Ibex SPI device model adds 9972479fac riscv: opentitan: Connect opentitan SPI Host adds a46d410c5c target/riscv: Define simpler privileged spec version numbering adds 3a4af26d7a target/riscv: Add the privileged spec version 1.12.0 adds a4b2fa4331 target/riscv: Introduce privilege version field in the CSR ops. adds 3e6a417c8a target/riscv: Add support for mconfigptr adds 29a9ec9bd8 target/riscv: Add *envcfg* CSRs support adds 7100fe6c24 target/riscv: Enable privileged spec version 1.12 adds 8b5c807bc0 target/riscv: cpu: Fixup indentation adds 33fe584f70 target/riscv: Allow software access to MIP SEIP adds 95799e36c1 target/riscv: Add initial support for the Sdtrig extension adds c341e886d9 target/riscv: optimize condition assign for scale < 0 adds f32d82f6c3 target/riscv: optimize helper for vmv<nr>r.v adds 0e2c377023 target/riscv: misa to ISA string conversion fix adds a775398be2 target/riscv: Add isa extenstion strings to the device tree adds f06193c40b target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 adds ac684717c3 target/riscv: Use cpu_loop_exit_restore directly from mmu faults adds 8f013700eb hw/riscv: virt: Exit if the user provided -bios in combinati [...] adds 6248a8fe4d target/riscv/pmp: fix NAPOT range computation overflow adds d6db2c0fab hw/riscv: virt: fix DT property mmu-type when CPU mmu option [...] adds 231a90c085 hw/intc: Add .impl.[min|max]_access_size declaration in RISC [...] adds d42df0ea5d hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RI [...] adds e2f01f3c2e hw/intc: Make RISC-V ACLINT mtime MMIO register writable adds 8124f819d0 hw/intc: riscv_aclint: Add reset function of ACLINT devices adds b5f6379d13 target/riscv: debug: Implement debug related TCGCPUOps adds 1acdb3b013 target/riscv: cpu: Add a config option for native debug adds b6092544fc target/riscv: csr: Hook debug CSR read/write adds 38b4e781a4 target/riscv: machine: Add debug state description adds c9711bd778 target/riscv: cpu: Enable native debug feature adds 013577de8f hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() adds faee5441a0 hw/riscv: boot: Support 64bit fdt address. adds 10cd282ee4 Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:ali [...] adds 86a518bba4 dump: Use ERRP_GUARD() adds 046bc4160b dump: Remove the sh_info variable adds 862a395858 dump: Introduce shdr_num to decrease complexity adds 344107e07b dump: Remove the section if when calculating the memory offset adds e71d353360 dump: Add more offset variables adds 05bbaa5040 dump: Introduce dump_is_64bit() helper function adds bc7d558017 dump: Consolidate phdr note writes adds 5ff2e5a3e1 dump: Cleanup dump_begin write functions adds c68124738b dump: Consolidate elf note function adds a64b4e179a include/qemu: rename Windows context definitions to expose bitness adds fb21efe99a dump/win_dump: add helper macros for Windows dump header access adds c4fe30921f include/qemu: add 32-bit Windows dump structures adds f5daa8293b dump/win_dump: add 32-bit guest Windows support adds f7f40b8198 Merge tag 'dump-pull-request' of gitlab.com:marcandre.lureau [...] adds 2a19903697 hw/intc/arm_gicv3_its: Add missing blank line adds 89ac9d0cba hw/intc/arm_gicv3: Sanity-check num-cpu property adds 671927a116 hw/intc/arm_gicv3: Insist that redist region capacity matche [...] adds 50a3a309e1 hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers adds 9acd2d3373 target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 adds c3c9a09073 hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" adds 50d84584d3 hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 adds 9de53de60c hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI adds 0cdf7a5dc8 hw/intc/arm_gicv3_its: Implement VMAPP adds 93f4fdcd4d hw/intc/arm_gicv3_its: Distinguish success and error cases o [...] adds f0175135e7 hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" adds c411db7bf7 hw/intc/arm_gicv3_its: Factor out CTE lookup sequence adds 2d692e2b31 hw/intc/arm_gicv3_its: Split out process_its_cmd() physical [...] adds 469cf23bf8 hw/intc/arm_gicv3_its: Handle virtual interrupts in process_ [...] adds 7c087bd330 hw/intc/arm_gicv3: Keep pointers to every connected ITS adds 3851af4585 hw/intc/arm_gicv3_its: Implement VMOVP adds f76ba95a03 hw/intc/arm_gicv3_its: Implement VSYNC adds a686e85d2b hw/intc/arm_gicv3_its: Implement INV command properly adds d4014320a4 hw/intc/arm_gicv3_its: Implement INV for virtual interrupts adds 3c64a42c0b hw/intc/arm_gicv3_its: Implement VMOVI adds c6dd2f9950 hw/intc/arm_gicv3_its: Implement VINVALL adds ae3b3ba15c hw/intc/arm_gicv3: Implement GICv4's new redistributor frame adds 641be69745 hw/intc/arm_gicv3: Implement new GICv4 redistributor registers adds 10337638bb hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3 [...] adds c3f21b065a hw/intc/arm_gicv3_cpuif: Support vLPIs adds 189d1d9d57 hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq u [...] adds e97be73c97 hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one [...] adds 99ba56d25b hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all [...] adds 6631480c9a hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes adds b76eb5f4db hw/intc/arm_gicv3_redist: Factor out "update bit in pending [...] adds d7d39749e6 hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() adds 932f0480d0 hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() adds ab6ef25179 hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov [...] adds c6f797d519 hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() adds e031346d98 hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() adds 1b19ccfa38 hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() adds e2d5e189aa hw/intc/arm_gicv3: Update ID and feature registers for GICv4 adds 445d5825da hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 adds 5a389a9aec hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() adds f31985a77a hw/arm/virt: Abstract out calculation of redistributor regio [...] adds 7cf3f8d243 hw/arm/virt: Support TCG GICv4 adds c42fb26b13 target/arm: Update ISAR fields for ARMv8.8 adds f527d66183 target/arm: Update SCR_EL3 bits to ARMv8.8 adds ad1e60184c target/arm: Update SCTLR bits to ARMv9.2 adds a3bc906f8e target/arm: Change DisasContext.aarch64 to bool adds 5322155240 target/arm: Change CPUArchState.aarch64 to bool adds 4f4c2a4ba2 target/arm: Extend store_cpu_offset to take field size adds 2ab370873f target/arm: Change DisasContext.thumb to bool adds 063bbd8061 target/arm: Change CPUArchState.thumb to bool adds a4c88675d6 target/arm: Remove fpexc32_access adds 667a4e6235 target/arm: Split out set_btype_raw adds e01aa38d48 target/arm: Split out gen_rebuild_hflags adds fe12080c5f target/arm: Simplify GEN_SHIFT in translate.c adds 099d1c2088 target/arm: Simplify gen_sar adds c89a9d139b target/arm: Simplify aa32 DISAS_WFI adds 01d90db599 target/arm: Use tcg_constant in translate-m-nocp.c adds d9b47e97e7 target/arm: Use tcg_constant in translate-neon.c adds aa5b0b29b1 target/arm: Use smin/smax for do_sat_addsub_32 adds 230c90ceb4 target/arm: Use tcg_constant in translate-vfp.c adds 2c2c65c01e target/arm: Use tcg_constant_i32 in translate.h adds c3ca7d56c4 hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntr [...] adds 754f756cc4 Merge tag 'pull-target-arm-20220422-1' of https://git.linaro [...] new 747421e949 Implements Backend Program conventions for vhost-user-scsi new 096b778f14 contrib/vhost-user-blk: add missing GOptionEntry NULL terminator new d45c83328f virtiofsd: Add docs/helper for killpriv_v2/no_killpriv_v2 option new c49abc8406 Merge tag 'block-pull-request' of https://gitlab.com/stefanh [...] new 80dd5aff1b block: add 'force' parameter to 'blockdev-change-medium' command new 093a13acbf iotests: replace calls to log(qemu_io(...)) with qemu_io_log() new a190524967 iotests/163: Fix broken qemu-io invocation new e9039c0451 iotests: Don't check qemu_io() output for specific error strings new aaa0c0ef82 iotests/040: Don't check image pattern on zero-length image new 4897629173 iotests/040: Fix TestCommitWithFilters test new b2d68a8e56 iotests: create generic qemu_tool() function new 6dede6a493 iotests: rebase qemu_io() on top of qemu_tool() new 7acb2ddfec iotests/migration-permissions: use assertRaises() for qemu_i [...] new db1646a639 iotests/image-fleecing: switch to qemu_io() new 23d44dcb7c iotests: remove qemu_io_pipe_and_status() new 72cfb937b8 iotests: remove qemu_io_silent() and qemu_io_silent_check(). new 40bfeae134 iotests: make qemu_io_log() check return codes by default new 348a0740af iotests/108: Fix when missing user_allow_other new a1755db71e Merge tag 'pull-block-2022-04-25' of https://gitlab.com/hrei [...]

The 19 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: block/qapi-sysemu.c | 3 +- contrib/elf2dmp/main.c | 6 +- contrib/vhost-user-blk/vhost-user-blk.c | 3 +- contrib/vhost-user-scsi/vhost-user-scsi.c | 79 ++- docs/system/arm/virt.rst | 5 +- docs/tools/virtiofsd.rst | 5 + dump/dump.c | 372 +++++----- dump/win_dump.c | 305 +++++--- hmp-commands.hx | 13 +- hw/arm/smmuv3.c | 2 +- hw/arm/virt.c | 102 ++- hw/intc/arm_gicv3_common.c | 54 +- hw/intc/arm_gicv3_cpuif.c | 195 +++++- hw/intc/arm_gicv3_dist.c | 7 +- hw/intc/arm_gicv3_its.c | 776 ++++++++++++++++++--- hw/intc/arm_gicv3_its_kvm.c | 2 + hw/intc/arm_gicv3_kvm.c | 5 + hw/intc/arm_gicv3_redist.c | 480 ++++++++++--- hw/intc/gicv3_internal.h | 213 +++++- hw/intc/riscv_aclint.c | 144 +++- hw/intc/trace-events | 18 +- hw/riscv/boot.c | 12 +- hw/riscv/opentitan.c | 36 +- hw/riscv/virt.c | 24 +- hw/ssi/ibex_spi_host.c | 612 ++++++++++++++++ hw/ssi/meson.build | 1 + hw/ssi/trace-events | 7 + include/hw/arm/virt.h | 19 +- include/hw/core/tcg-cpu-ops.h | 1 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 19 + include/hw/intc/riscv_aclint.h | 1 + include/hw/riscv/boot.h | 4 +- include/hw/riscv/opentitan.h | 30 +- include/hw/ssi/ibex_spi_host.h | 94 +++ include/qemu/win_dump_defs.h | 115 ++- include/sysemu/dump.h | 9 +- linux-user/arm/cpu_loop.c | 2 +- migration/channel.c | 1 - migration/migration.c | 66 +- migration/migration.h | 4 +- migration/multifd.c | 29 +- migration/multifd.h | 4 - migration/ram.c | 10 +- migration/ram.h | 1 + migration/savevm.c | 3 - migration/tls.c | 4 - monitor/hmp-cmds.c | 4 +- qapi/block.json | 6 + target/arm/cpu.c | 16 +- target/arm/cpu.h | 59 +- target/arm/helper-a64.c | 4 +- target/arm/helper.c | 19 +- target/arm/hvf/hvf.c | 2 +- target/arm/m_helper.c | 6 +- target/arm/op_helper.c | 13 - target/arm/translate-a32.h | 13 +- target/arm/translate-a64.c | 50 +- target/arm/translate-m-nocp.c | 12 +- target/arm/translate-neon.c | 21 +- target/arm/translate-sve.c | 9 +- target/arm/translate-vfp.c | 76 +- target/arm/translate.c | 101 +-- target/arm/translate.h | 17 +- target/riscv/cpu.c | 120 +++- target/riscv/cpu.h | 40 +- target/riscv/cpu_bits.h | 40 ++ target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c | 282 +++++++- target/riscv/debug.c | 441 ++++++++++++ target/riscv/debug.h | 114 +++ target/riscv/helper.h | 5 +- target/riscv/insn_trans/trans_rvv.c.inc | 25 +- target/riscv/machine.c | 55 ++ target/riscv/meson.build | 1 + target/riscv/pmp.c | 14 +- target/riscv/vector_helper.c | 31 +- tests/qemu-iotests/030 | 85 ++- tests/qemu-iotests/040 | 53 +- tests/qemu-iotests/056 | 2 +- tests/qemu-iotests/108 | 2 +- tests/qemu-iotests/149 | 6 +- tests/qemu-iotests/163 | 5 +- tests/qemu-iotests/205 | 4 +- tests/qemu-iotests/216 | 12 +- tests/qemu-iotests/218 | 5 +- tests/qemu-iotests/224 | 4 +- tests/qemu-iotests/242 | 6 +- tests/qemu-iotests/245 | 17 +- tests/qemu-iotests/255 | 4 +- tests/qemu-iotests/258 | 11 +- tests/qemu-iotests/298 | 17 +- tests/qemu-iotests/303 | 4 +- tests/qemu-iotests/310 | 22 +- tests/qemu-iotests/iotests.py | 69 +- tests/qemu-iotests/tests/image-fleecing | 30 +- tests/qemu-iotests/tests/migration-permissions | 28 +- tests/qemu-iotests/tests/mirror-ready-cancel-error | 2 +- tests/qemu-iotests/tests/nbd-reconnect-on-open | 2 +- tests/qemu-iotests/tests/stream-error-on-reset | 4 +- tests/qtest/libqtest.c | 13 +- tests/qtest/migration-test.c | 368 +++++----- tests/unit/crypto-tls-psk-helpers.c | 2 +- tools/virtiofsd/helper.c | 3 + ui/cocoa.m | 1 + 105 files changed, 4854 insertions(+), 1443 deletions(-) create mode 100644 hw/ssi/ibex_spi_host.c create mode 100644 include/hw/ssi/ibex_spi_host.h create mode 100644 target/riscv/debug.c create mode 100644 target/riscv/debug.h