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from 136330bf637 aarch64: PR target/108840 Simplify register shift RTX costs [...] new 2c7bf8036df [aarch64] Use wzr/xzr for assigning 0 to vector element.

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Summary of changes: gcc/config/aarch64/aarch64-simd.md | 14 +++++++++ gcc/testsuite/gcc.target/aarch64/vec-set-zero.c | 40 +++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/vec-set-zero.c