This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.

from d70075373a Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/vir [...] adds 0fbb5d2d3c target/riscv/pmp: fix no pmp illegal intrs adds 6fd3f397ca hw/dma: sifive_pdma: support high 32-bit access of 64-bit register adds e6b0408a17 hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers adds 83b92b8efc hw/intc: sifive_plic: Add a reset function adds fb926d57cc hw/intc: sifive_plic: Cleanup the write function adds b79e1c76c0 hw/intc: sifive_plic: Cleanup the read function adds 41bcc44a25 hw/intc: sifive_plic: Cleanup remaining functions adds 6ca7155a8c target/riscv: Mark the Hypervisor extension as non experimental adds 07cb270a9a target/riscv: Enable the Hypervisor extension by default adds 8f972e5b4b hw/riscv: Use error_fatal for SoC realisation adds d4452c6924 hw/riscv: virt: Allow support for 32 cores adds b3e0204968 roms/opensbi: Upgrade from v0.9 to v1.0 adds 629ccdaa4e target/riscv: rvv-1.0: Call the correct RVF/RVD check functi [...] adds 91cade44cd target/riscv: rvv-1.0: Call the correct RVF/RVD check functi [...] adds 79e6176ea0 target/riscv: rvv-1.0: Call the correct RVF/RVD check functi [...] adds dfdb46a376 target/riscv: Fix position of 'experimental' comment adds fc313c6434 exec/memop: Adding signedness to quad definitions adds c7f9dd5465 exec/memop: Adding signed quad and octo defines adds e9d07601f6 qemu/int128: addition of div/rem 128-bit operations adds 344b4a82fc target/riscv: additional macros to check instruction support adds a1a3aac448 target/riscv: separation of bitwise logic and arithmetic helpers adds 2b5470843a target/riscv: array for the 64 upper bits of 128-bit registers adds 332dab6878 target/riscv: setup everything for rv64 to support rv128 execution adds 76a361066f target/riscv: moving some insns close to similar insns adds a2f827ff4f target/riscv: accessors to registers upper part and 128-bit [...] adds 568f247f69 target/riscv: support for 128-bit bitwise instructions adds 57c108b864 target/riscv: support for 128-bit U-type instructions adds 6bf4bbed20 target/riscv: support for 128-bit shift instructions adds 7fd40f8679 target/riscv: support for 128-bit arithmetic instructions adds b3a5d1fbeb target/riscv: support for 128-bit M extension adds 2c64ab66c1 target/riscv: adding high part of some csrs adds 961738ffea target/riscv: helper functions to wrap calls to 128-bit csr insns adds 7934fdeee7 target/riscv: modification of the trans_csrxx for 128-bit support adds 457c360f9c target/riscv: actual functions to realize crs 128-bit insns adds ea7b5d5af6 target/riscv: Set the opcode in DisasContext adds 86d0c45739 target/riscv: Fixup setting GVA adds 48eaeb56de target/riscv: Implement the stval/mtval illegal instruction adds afe3326258 Merge tag 'pull-riscv-to-apply-20220108' of github.com:alist [...] adds 73d72229fc bsd-user/mips*: Remove mips support adds aa3a242830 bsd-user/freebsd: Create common target_os_ucontext.h file adds 19bf129f82 bsd-user: create a per-arch signal.c file adds 4dca396631 bsd-user/i386/target_arch_signal.h: Remove target_sigcontext adds c504713f34 bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.h adds 679041b1ef bsd-user/i386/target_arch_signal.h: Update mcontext_t to mat [...] adds f7d5ed6184 bsd-user/i386: Move the inlines into signal.c adds fc1fc2c78e bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontext adds c104b7505b bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.h adds 164f94bc30 bsd-user/x86_64/target_arch_signal.h: Fill in mcontext_t adds 1b4e358a61 bsd-user/x86_64: Move functions into signal.c adds 108fffe536 bsd-user/target_os_signal.h: Move signal prototypes to targe [...] adds c186aa67de bsd-user/arm/target_arch_sysarch.h: Use consistent include guards adds 559d09a6cd bsd-user/arm/target_syscall.h: Add copyright and update name adds 8c98705bb9 bsd-user/arm/target_arch_cpu.c: Target specific TLS routines adds ca5d32a3f3 bsd-user/arm/target_arch_cpu.h: CPU Loop definitions adds e17d4c9a37 bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs adds 06efe3bfce bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implem [...] adds 70985aec1c bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions adds ef1412bd84 bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions adds 8d450c9a30 bsd-user/arm/target_arch_cpu.h: Implement system call dispatch adds bcacf30808 bsd-user/arm/target_arch_reg.h: Implement core dump register [...] adds dacfdf3ba4 bsd-user/arm/target_arch_vmparam.h: Parameters for arm addre [...] adds eacb50b8d9 bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm adds f10521cc22 bsd-user/arm/target_arch_thread.h: Routines to create and sw [...] adds 082e65314b bsd-user/arm/target_arch_elf.h: arm defines for ELF adds 6c5d60fa78 bsd-user/arm/target_arch_elf.h: arm get hwcap adds 883d19ccf9 bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl adds 156d75579f bsd-user/arm/target_arch_signal.h: arm specific signal regis [...] adds 03fd4028f1 bsd-user/arm/target_arch_signal.h: arm machine context and t [...] adds 2cb1e6432f bsd-user/arm/target_arch_signal.h: Define size of *context_t adds 781be8666c bsd-user/arm/signal.c: arm set_sigtramp_args adds 38ce1471c9 bsd-user/arm/signal.c: arm get_mcontext adds d6d4509a9f bsd-user/arm/signal.c: arm set_mcontext adds 3ac34cc985 bsd-user/arm/signal.c: arm get_ucontext_sigreturn adds ca4fc704a4 bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE adds 18fe5d99f2 bsd-user: add arm target build adds df722e33d5 Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/q [...]

No new revisions were added by this update.

Summary of changes: accel/tcg/cputlb.c | 30 +- accel/tcg/ldst_common.c.inc | 8 +- accel/tcg/user-exec.c | 8 +- bsd-user/arm/signal.c | 196 ++++++ bsd-user/{netbsd/host-os.h => arm/target_arch.h} | 13 +- .../{freebsd/os-strace.h => arm/target_arch_cpu.c} | 24 +- bsd-user/arm/target_arch_cpu.h | 211 ++++++ bsd-user/arm/target_arch_elf.h | 128 ++++ bsd-user/arm/target_arch_reg.h | 60 ++ bsd-user/arm/target_arch_signal.h | 88 +++ bsd-user/{x86_64 => arm}/target_arch_sigtramp.h | 24 +- bsd-user/arm/target_arch_sysarch.h | 6 +- bsd-user/arm/target_arch_thread.h | 82 +++ bsd-user/arm/target_arch_vmparam.h | 48 ++ bsd-user/arm/target_syscall.h | 27 +- bsd-user/freebsd/target_os_signal.h | 3 - bsd-user/freebsd/target_os_ucontext.h | 44 ++ bsd-user/i386/signal.c | 55 ++ bsd-user/i386/target_arch_signal.h | 95 ++- bsd-user/mips/target_arch_sysarch.h | 69 -- bsd-user/mips/target_syscall.h | 52 -- bsd-user/mips64/target_arch_sysarch.h | 69 -- bsd-user/mips64/target_syscall.h | 53 -- bsd-user/x86_64/{target_arch_signal.h => signal.c} | 47 +- bsd-user/x86_64/target_arch_signal.h | 103 +-- .../targets/{arm-softmmu.mak => arm-bsd-user.mak} | 2 - disas/riscv.c | 5 + hw/dma/sifive_pdma.c | 181 +++++- hw/intc/sifive_plic.c | 254 +++----- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- include/disas/dis-asm.h | 1 + include/exec/memop.h | 15 +- include/hw/riscv/virt.h | 2 +- include/qemu/int128.h | 27 + include/tcg/tcg-op.h | 4 +- meson.build | 2 +- pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 78680 -> 108504 bytes pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 727464 -> 838904 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 75096 -> 105296 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 781264 -> 934696 bytes roms/opensbi | 2 +- target/alpha/translate.c | 32 +- target/arm/helper-a64.c | 8 +- target/arm/translate-a32.h | 4 +- target/arm/translate-a64.c | 8 +- target/arm/translate-neon.c | 6 +- target/arm/translate-sve.c | 10 +- target/arm/translate-vfp.c | 8 +- target/arm/translate.c | 2 +- target/cris/translate.c | 2 +- target/hppa/translate.c | 4 +- target/i386/tcg/mem_helper.c | 2 +- target/i386/tcg/translate.c | 36 +- target/m68k/op_helper.c | 2 +- target/mips/tcg/micromips_translate.c.inc | 10 +- target/mips/tcg/translate.c | 58 +- target/mips/tcg/tx79_translate.c | 8 +- target/ppc/translate.c | 32 +- target/ppc/translate/fixedpoint-impl.c.inc | 22 +- target/ppc/translate/fp-impl.c.inc | 4 +- target/ppc/translate/vsx-impl.c.inc | 42 +- target/riscv/cpu.c | 34 +- target/riscv/cpu.h | 24 + target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 24 +- target/riscv/csr.c | 194 +++++- target/riscv/gdbstub.c | 5 + target/riscv/helper.h | 9 + target/riscv/insn16.decode | 27 +- target/riscv/insn32.decode | 25 + target/riscv/insn_trans/trans_rva.c.inc | 22 +- target/riscv/insn_trans/trans_rvb.c.inc | 48 +- target/riscv/insn_trans/trans_rvd.c.inc | 4 +- target/riscv/insn_trans/trans_rvh.c.inc | 4 +- target/riscv/insn_trans/trans_rvi.c.inc | 716 ++++++++++++++++++--- target/riscv/insn_trans/trans_rvm.c.inc | 192 +++++- target/riscv/insn_trans/trans_rvv.c.inc | 78 ++- target/riscv/m128_helper.c | 109 ++++ target/riscv/machine.c | 22 + target/riscv/meson.build | 1 + target/riscv/op_helper.c | 47 +- target/riscv/translate.c | 257 +++++++- target/s390x/tcg/insn-data.def | 28 +- target/s390x/tcg/mem_helper.c | 8 +- target/s390x/tcg/translate.c | 8 +- target/s390x/tcg/translate_vx.c.inc | 18 +- target/sh4/translate.c | 12 +- target/sparc/translate.c | 36 +- target/tricore/translate.c | 4 +- target/xtensa/translate.c | 4 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 10 +- tcg/i386/tcg-target.c.inc | 12 +- tcg/mips/tcg-target.c.inc | 12 +- tcg/ppc/tcg-target.c.inc | 16 +- tcg/riscv/tcg-target.c.inc | 6 +- tcg/s390x/tcg-target.c.inc | 18 +- tcg/sparc/tcg-target.c.inc | 16 +- tcg/tcg.c | 4 +- tcg/tci.c | 16 +- util/int128.c | 147 +++++ util/meson.build | 1 + 105 files changed, 3411 insertions(+), 1158 deletions(-) create mode 100644 bsd-user/arm/signal.c copy bsd-user/{netbsd/host-os.h => arm/target_arch.h} (73%) copy bsd-user/{freebsd/os-strace.h => arm/target_arch_cpu.c} (59%) create mode 100644 bsd-user/arm/target_arch_cpu.h create mode 100644 bsd-user/arm/target_arch_elf.h create mode 100644 bsd-user/arm/target_arch_reg.h create mode 100644 bsd-user/arm/target_arch_signal.h copy bsd-user/{x86_64 => arm}/target_arch_sigtramp.h (50%) create mode 100644 bsd-user/arm/target_arch_thread.h create mode 100644 bsd-user/arm/target_arch_vmparam.h create mode 100644 bsd-user/freebsd/target_os_ucontext.h create mode 100644 bsd-user/i386/signal.c delete mode 100644 bsd-user/mips/target_arch_sysarch.h delete mode 100644 bsd-user/mips/target_syscall.h delete mode 100644 bsd-user/mips64/target_arch_sysarch.h delete mode 100644 bsd-user/mips64/target_syscall.h copy bsd-user/x86_64/{target_arch_signal.h => signal.c} (50%) copy configs/targets/{arm-softmmu.mak => arm-bsd-user.mak} (82%) create mode 100644 target/riscv/m128_helper.c create mode 100644 util/int128.c