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from e0a7233e1d2 s390: testsuite: Fix backprop-6.c new 47de95d801c RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

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Summary of changes: gcc/config/riscv/riscv-c.cc | 3 + gcc/config/riscv/riscv.cc | 87 ++++++++++++++++- .../riscv/rvv/base/riscv_rvv_vector_bits-1.c | 6 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-10.c | 53 ++++++++++ .../riscv/rvv/base/riscv_rvv_vector_bits-11.c | 76 +++++++++++++++ .../riscv/rvv/base/riscv_rvv_vector_bits-12.c | 14 +++ .../riscv/rvv/base/riscv_rvv_vector_bits-13.c | 10 ++ .../pr112554.c => base/riscv_rvv_vector_bits-14.c} | 14 ++- .../riscv/rvv/base/riscv_rvv_vector_bits-15.c | 10 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-16.c | 11 +++ .../riscv/rvv/base/riscv_rvv_vector_bits-17.c | 10 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-18.c | 45 +++++++++ .../riscv/rvv/base/riscv_rvv_vector_bits-2.c | 6 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-3.c | 6 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-4.c | 6 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-5.c | 6 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-6.c | 6 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-7.c | 76 +++++++++++++++ .../riscv/rvv/base/riscv_rvv_vector_bits-8.c | 75 ++++++++++++++ .../riscv/rvv/base/riscv_rvv_vector_bits-9.c | 76 +++++++++++++++ .../riscv/rvv/base/riscv_rvv_vector_bits.h | 108 +++++++++++++++++++++ 21 files changed, 694 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-13.c copy gcc/testsuite/gcc.target/riscv/rvv/{autovec/pr112554.c => base/riscv_rvv_vect [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits.h