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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_ubsan in repository toolchain/ci/gcc.

from fddb7f65129 Disable generating load/store vector pairs for block copies. adds 9489a1ab05a xtensa: Tweak some widen multiplications adds fddf0e1057f xtensa: Consider the Loop Option when setmemsi is expanded [...] adds ccd02e734e0 xtensa: Improve instruction cost estimation and suggestion adds cd02f15f1ae xtensa: Improve constant synthesis for both integer and flo [...] adds cbd842717ec Daily bump. adds 494bec02500 PR96463: Optimise svld1rq from vectors for little endian AA [...] adds ff500e1cf16 gcc: xtensa: fix pr95571 test for call0 ABI

No new revisions were added by this update.

Summary of changes: gcc/ChangeLog | 50 ++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 59 ++++ gcc/config/aarch64/aarch64.cc | 95 ++++-- gcc/config/xtensa/xtensa-protos.h | 1 + gcc/config/xtensa/xtensa.cc | 320 ++++++++++++++++++--- gcc/config/xtensa/xtensa.md | 135 +++++++-- gcc/config/xtensa/xtensa.opt | 4 + gcc/testsuite/ChangeLog | 6 + gcc/testsuite/g++.target/xtensa/pr95571.C | 6 + .../aarch64/sve/acle/general/pr96463-1.c | 29 ++ .../aarch64/sve/acle/general/pr96463-2.c | 29 ++ .../gcc.target/xtensa/constsynth_2insns.c | 44 +++ .../gcc.target/xtensa/constsynth_3insns.c | 24 ++ .../gcc.target/xtensa/constsynth_double.c | 11 + gcc/tree-cfg.cc | 40 ++- 16 files changed, 738 insertions(+), 117 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c create mode 100644 gcc/testsuite/gcc.target/xtensa/constsynth_2insns.c create mode 100644 gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c create mode 100644 gcc/testsuite/gcc.target/xtensa/constsynth_double.c