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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Os in repository toolchain/ci/llvm-project.

from 68b4673feaa CodeGen: Preserve packed attribute in constStructWithPadding. adds b18e314a7cb [RISCV] Fix RISCVAsmParser::ParseRegister and add tests adds 997947961a0 [RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsm [...] adds 6778b53e957 [ELF] De-virtualize findOrphanPos, excludeLibs and handleAR [...] adds 6a6e808b699 [TargetLowering] improve the default expansion of uaddsat/usubsat adds 9a4453592bf [DAGCombine] Fold (x & ~y) | y patterns adds 738146ab333 [LLD][ELF] - Replace one of the tests with a YAML version. adds 30673299d45 [ARM] Add some CBZ constant island tests. NFC adds e0b48a80150 [ARM] Search backwards for CMP when combining into CBZ adds a3a2f9424e0 [InstCombine] add tests for rotate by constant using funnel [...] adds b3bcd957718 [InstCombine] canonicalize rotate right by constant to rotate left adds ef2d9799435 [ConstantRange] Add fromKnownBits() method adds 10ba65cc48f [AMDGPU] Regenerate some f16/i16 tests. adds d1477e989ce [ARM] Fixed an assumption of power-of-2 vector MVT adds e30aa6a1362 [AMDGPU] Prepare for introduction of v3 and v5 MVTs adds 12509d87f3a [X86] Remove the _alt forms of XOP VPCOM instructions. Use [...] adds affead9ad0a [X86] Remove the _alt forms of AVX512 VPCMP instructions. U [...] adds 322e2dbee12 [ValueTracking] Use ConstantRange overflow check for signed [...] adds 5e7b62de056 [ConstantRange] Add assertion for KnownBits validity; NFC adds e0c1f9e76d5 AMDGPU: Partially fix default device for HSA adds 884a18d7925 RegAllocFast: Add hint to debug printing adds baa94ef03bc [ARM] Check that CPSR does not have other uses adds c302b9b5fe0 [CodeGen] Prepare for introduction of v3 and v5 MVTs new c4e128e2219 [CodeGen] Defined MVTs v3i32, v3f32, v5i32, v5f32 new 04cc28fe133 [X86] Merge printf32mem/printi32mem into a single printdwor [...] new 4873056ced0 Remove immarg from llvm.expect new 541bccf4d91 Add testcase from bug 41079

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Summary of changes: clang/test/CodeGen/builtin-expect.c | 17 + lld/ELF/Driver.cpp | 3 +- lld/ELF/Relocations.cpp | 3 +- lld/ELF/Writer.cpp | 3 +- lld/test/ELF/invalid/Inputs/data-encoding.a | Bin 156 -> 0 bytes lld/test/ELF/invalid/data-encoding.test | 17 + lld/test/ELF/invalid/invalid-elf.test | 4 - llvm/docs/LangRef.rst | 3 +- llvm/include/llvm/CodeGen/SelectionDAG.h | 3 + llvm/include/llvm/CodeGen/TargetLowering.h | 3 + llvm/include/llvm/CodeGen/ValueTypes.td | 166 ++-- llvm/include/llvm/IR/ConstantRange.h | 6 + llvm/include/llvm/IR/Intrinsics.td | 4 +- llvm/include/llvm/Support/MachineValueType.h | 178 ++-- .../llvm/Support/X86DisassemblerDecoderCommon.h | 1 - llvm/lib/Analysis/ValueTracking.cpp | 75 +- llvm/lib/CodeGen/RegAllocFast.cpp | 3 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 22 + llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 + .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 30 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 9 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 + llvm/lib/CodeGen/ValueTypes.cpp | 8 + llvm/lib/IR/ConstantRange.cpp | 21 + llvm/lib/Support/TargetParser.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 3 +- llvm/lib/Target/AMDGPU/GCNProcessors.td | 4 + llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 98 ++- llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 +- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 32 +- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 72 +- .../Target/X86/Disassembler/X86Disassembler.cpp | 145 ---- .../Target/X86/InstPrinter/X86ATTInstPrinter.cpp | 154 +++- .../lib/Target/X86/InstPrinter/X86ATTInstPrinter.h | 32 +- .../X86/InstPrinter/X86InstPrinterCommon.cpp | 125 ++- .../Target/X86/InstPrinter/X86InstPrinterCommon.h | 3 +- .../Target/X86/InstPrinter/X86IntelInstPrinter.cpp | 151 +++- .../Target/X86/InstPrinter/X86IntelInstPrinter.h | 37 +- llvm/lib/Target/X86/X86InstrAVX512.td | 95 +-- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 4 +- llvm/lib/Target/X86/X86InstrInfo.td | 72 +- llvm/lib/Target/X86/X86InstrXOP.td | 26 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 27 +- llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll | 15 +- .../Analysis/CostModel/AMDGPU/extractelement.ll | 9 + llvm/test/Analysis/CostModel/AMDGPU/fabs.ll | 10 + llvm/test/Analysis/CostModel/AMDGPU/fadd.ll | 15 +- llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll | 22 +- llvm/test/Analysis/CostModel/AMDGPU/fmul.ll | 15 +- llvm/test/Analysis/CostModel/AMDGPU/fsub.ll | 15 +- llvm/test/Analysis/CostModel/AMDGPU/mul.ll | 15 +- llvm/test/CodeGen/AArch64/sat-add.ll | 24 +- llvm/test/CodeGen/AArch64/uadd_sat_vec.ll | 21 +- .../unfold-masked-merge-scalar-variablemask.ll | 6 +- ...nfold-masked-merge-vector-variablemask-const.ll | 7 +- llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 173 +++- llvm/test/CodeGen/AMDGPU/call-return-types.ll | 42 +- llvm/test/CodeGen/AMDGPU/calling-conventions.ll | 90 ++ .../AMDGPU/flat-error-unsupported-gpu-hsa.ll | 15 + llvm/test/CodeGen/AMDGPU/kernel-args.ll | 116 +++ llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 5 +- llvm/test/CodeGen/AMDGPU/max.i16.ll | 412 +++++++++- llvm/test/CodeGen/AMDGPU/select.f16.ll | 912 +++++++++++++++++---- llvm/test/CodeGen/AMDGPU/v_madak_f16.ll | 131 ++- llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll | 67 ++ llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir | 317 +++++++ .../X86/unfold-masked-merge-scalar-variablemask.ll | 12 +- ...nfold-masked-merge-vector-variablemask-const.ll | 49 +- llvm/test/MC/RISCV/cfi-regs-invalid.s | 7 + llvm/test/MC/RISCV/cfi-regs-valid.s | 137 ++++ llvm/test/MC/X86/avx512-encodings.s | 4 +- llvm/test/TableGen/intrinsic-varargs.td | 2 +- llvm/test/Transforms/InstCombine/fsh.ll | 40 +- .../Transforms/LowerExpectIntrinsic/PR33346.ll | 4 +- llvm/test/Verifier/intrinsic-immarg.ll | 9 - .../test/tools/llvm-mca/X86/BdVer2/resources-xop.s | 64 +- .../tools/llvm-mca/X86/Generic/resources-xop.s | 64 +- llvm/unittests/IR/ConstantRangeTest.cpp | 65 ++ llvm/utils/TableGen/CodeGenTarget.cpp | 4 + llvm/utils/TableGen/X86RecognizableInstr.cpp | 4 - 82 files changed, 3535 insertions(+), 1088 deletions(-) delete mode 100644 lld/test/ELF/invalid/Inputs/data-encoding.a create mode 100644 lld/test/ELF/invalid/data-encoding.test create mode 100644 llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll create mode 100644 llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll create mode 100644 llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir create mode 100644 llvm/test/MC/RISCV/cfi-regs-invalid.s create mode 100644 llvm/test/MC/RISCV/cfi-regs-valid.s