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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project.

from e2549a0a251 [DebugInfo] Fix for DW_OP_LLVM_fragment in DIExpression::is [...] adds 91661573fde [X86] Convert PICStyles::Style to scoped enum class. NFCI. adds 8f29e4407cc [X86][SSE] combineX86ShufflesRecursively - don't bother mer [...] adds ce7d5a6bbee gn build: (manually) merge 3a399c09 / add76dd3c adds 910718bd038 [opaque pointer types] Add element type argument to IRBuild [...] adds a18a8db0d49 [SelectionDAG] Fixed null check after dereferencing warning. NFCI. adds f39d95ea04b [BitcodeReader] Fixed null pointer dereferencing warning. NFCI. adds 46f372a4aa5 [BitcodeReader] Fixed null check after dereferencing warnin [...] adds 505a44ae9cf [BitcodeReader] Fixed use after move warnings. NFCI. adds 60cb193a40f [LoopUnrollAndJam] Fixed null check after dereferencing war [...] adds 914128ab12f [LoopUnrollRuntime] Fixed null check after dereferencing wa [...] adds 8262a5b7016 [CHR] Fixed null check after dereferencing warning. NFCI. adds 8308187fd9b [InstructionCombining] Fixed null check after dereferencing [...] adds b8685cf3042 [InstructionCompares] Fixed null check after dereferencing [...] adds d825ed24d2f Revert "[InstructionCompares] Fixed null check after derefe [...] adds 717965ae578 [MemorySSA] Fixed null check after dereferencing warning. NFCI. adds decd8c4844a [SCEV] Fixed 'Uninitialized variable 'ContainsAddRec' used. [...] adds 5b37c018d5c Revert "[InstructionCombining] Fixed null check after deref [...] adds 058b5028def Reland '[InstructionCombining] Fixed null check after deref [...] adds c3d6f0ddeee [SILoadStoreOptimizer] Fixed typo. NFCI. adds 3fbd1c00b0f [SIMachineScheduler] Fixed ''then' statement is equivalent [...] adds 3f087e38a2e [X86][SSE] combineX86ShufflesRecursively - at Depth==0, onl [...] adds 5257a954267 [mips] Add disassembler tests for `sigrie` instruction. NFC adds cf954e54f75 [mips] Add disassembler tests for `octeon` CPU. NFC adds 52efd673692 [mips] Move test case for Octeon instructions to cnmips sub [...] adds e345bc6e65a [compiler-rt] [msan] Support POSIX iconv(3) on NetBSD 9.99.17+ adds 858b15cb9cf [compiler-rt] [msan] Correct the __libc_thr_keycreate prototype adds 31e14f41a21 clang/Modules: Sink CompilerInstance::KnownModules into ModuleMap adds 8d7ccb37440 Set the floating point status register as reserved adds 80bf88d8bc8 [lldb] Add trailing dots to comments in Value.cpp adds ae10661a812 [lldb] Provide a getter for m_materializer_up in LLVMUserEx [...] adds df12a75a196 [lldb] Also disable de-registration of EHFrames in IRExecutionUnit adds 848007cfbc7 [lldb][NFC] Make test/python_api/module_section test smaller adds 2be17087f8c [LV] Apply sink-after & interleave-groups as VPlan transfor [...] adds 580310ff0c5 [SystemZ] Improve handling of huge PC relative immediate offsets. adds 25b486ac4f3 [lldb][NFC] Remove unused ExpressionParser::Parse adds bc728d58424 [lldb][NFC] Remove Ocaml from TypeSystem::LLVMCastKind adds 91167e22eca [hwasan] Remove lazy thread-initialisation adds 51b4b17eb7e [RISCV] Implement the TargetLowering::getRegisterByName hook adds 3169f0129a6 [FIX] Removed duplicated v4f16 and v8f16 declarations adds 31ed36d0447 [X86] SimplifyDemandedVectorElts - attempt to recombine tar [...] adds ef85f47595a [llvm-readobj] Change errors to warnings for symbol section [...] adds 499c90afe90 [InstSimplify] add more tests for fcmp+select; NFC adds 22f9429149a [SystemZ] Add GHC calling convention adds 82888b78d47 [OpenCL] Fix address space for const method call from nonco [...] adds ad87f244b42 [InstSimplify] add more tests for fcmp+select; NFC adds 659bd73d136 [InstSimplify] use FMF to improve fcmp+select fold adds 6bae5d16a28 [ARM] Add vrev32 NEON fp16 patterns adds 1c616a9266b [ARM] More MVE shuffle tests for sequences that can be conv [...] adds d3ec06d2197 Revert "[LV] Apply sink-after & interleave-groups as VPlan [...] adds a3915ca9f90 gn build: add deps, see discussion on D69130 adds 9cd13deb293 gn build: run "gn format" adds 4168a2e9de3 gn build: (manually) merge 51b4b17eb adds d4a7855b68d [SystemZ] Fix typo adds d142ec6fef9 Fix compilation warning. NFC. adds b556ce39927 [IR] adjust assert when replacing undef elements in vector [...] adds 91b0cad8132 [ARM] Use isFMAFasterThanFMulAndFAdd for MVE adds 6c5827975cf [OpenCL] Fix FileCheck pattern adds 03cde3a7ccd [X86] Regenerate known-signbits-vector.ll tests. adds a0324e91137 SanitizerMask::bitPosToMask - fix operator precedence warni [...] adds b7b170c9b46 [MachineVerifier] Improve verification of live-in lists. adds bf6744dfb24 [SystemZ] Use LivePhysRegs instead of isCCLiveOut() in Sys [...] adds 0bab0538d8c [test] Use system locale for mri-utf8.test adds 55507110b98 [Diagnostics] Improve some error messages related to bad us [...] adds 1abb2c1a39f AliasSetTracker - fix uninitialized variable warnings. NFCI. adds 9ad9d1531b9 [X86] Convert ShrinkMode to scoped enum class. NFCI. adds b80c41cd3c0 [SLP]Fix PR43799: Crash on different sizes of GEP indices. adds b14ff0caecb Fix buildbots troubled by b7b170c. adds 9ba16615fa0 [Sema] Make helper in TreeTransform.h 'inline' instead of ' [...] adds 664f84e2464 [FPEnv][SelectionDAG] Refactor strict FP node construction new 2c6fae179e6 ELF: Discard .ARM.exidx sections for empty functions instea [...] new ab76cfdd200 Recommit "[CodeView] Add option to disable inline line tables." new 40d0d4e2335 Lower generic MASSV entries to PowerPC subtarget-specific entries new 73c3137a82c Fix static analysis warnings in ARM calling convention lowering new 667223c3ed6 gn build: Merge 40d0d4e2335 new 692b42fbb05 MCDwarfFile::DirIndex - fix uninitialized variable warning. NFCI. new 67286c87854 createMCObjectStreamer - fix uninitialized variable warning. NFCI. new e1000f1d674 VirtualFileSystem - fix uninitialized variable warnings. NFCI. new a8653da4320 [X86] Fix uninitialized variable warnings. NFCI.

The 9 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: clang/include/clang/Basic/CodeGenOptions.def | 2 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 6 +- clang/include/clang/Basic/Sanitizers.h | 9 +- clang/include/clang/Driver/Options.td | 11 +- clang/include/clang/Frontend/CompilerInstance.h | 4 - clang/include/clang/Lex/ModuleMap.h | 17 +- clang/lib/CodeGen/CGBuilder.h | 2 +- clang/lib/CodeGen/CGExpr.cpp | 3 +- clang/lib/CodeGen/CodeGenFunction.cpp | 4 + clang/lib/Driver/ToolChains/Clang.cpp | 6 + clang/lib/Driver/ToolChains/Darwin.cpp | 4 +- clang/lib/Frontend/CompilerInstance.cpp | 34 +- clang/lib/Frontend/CompilerInvocation.cpp | 1 + clang/lib/Sema/SemaCast.cpp | 2 +- clang/lib/Sema/SemaOverload.cpp | 5 +- clang/lib/Sema/TreeTransform.h | 2 +- .../CodeGen/debug-info-no-inline-line-tables.c | 31 + clang/test/CodeGenOpenCLCXX/addrspace-of-this.cl | 13 +- clang/test/SemaCXX/dynamic-cast.cpp | 12 +- clang/test/SemaTemplate/instantiate-cast.cpp | 2 +- compiler-rt/lib/hwasan/hwasan_interceptors.cpp | 28 +- compiler-rt/lib/hwasan/hwasan_linux.cpp | 7 +- compiler-rt/lib/msan/msan_interceptors.cpp | 5 +- compiler-rt/test/msan/iconv.cpp | 11 +- lld/ELF/SyntheticSections.cpp | 8 +- lld/test/ELF/arm-exidx-empty-fn.s | 41 ++ lldb/include/lldb/Expression/Expression.h | 4 + lldb/include/lldb/Expression/ExpressionParser.h | 11 - lldb/include/lldb/Expression/IRExecutionUnit.h | 2 + lldb/include/lldb/Expression/LLVMUserExpression.h | 2 + lldb/include/lldb/Symbol/TypeSystem.h | 1 - .../test/python_api/module_section/main.cpp | 134 +---- lldb/source/Core/Value.cpp | 4 +- .../ExpressionParser/Clang/ClangExpressionParser.h | 2 +- .../ExpressionParser/Clang/ClangFunctionCaller.cpp | 8 +- .../ExpressionParser/Clang/ClangUserExpression.cpp | 4 +- llvm/docs/LangRef.rst | 7 + llvm/include/llvm/Analysis/AliasSetTracker.h | 4 +- llvm/include/llvm/Analysis/VecFuncs.def | 11 +- llvm/include/llvm/CodeGen/LivePhysRegs.h | 3 + llvm/include/llvm/IR/Attributes.td | 1 + llvm/include/llvm/IR/IRBuilder.h | 14 +- llvm/include/llvm/IR/Instructions.h | 5 - llvm/include/llvm/MC/MCDwarf.h | 2 +- llvm/include/llvm/Support/TargetRegistry.h | 2 +- llvm/lib/Analysis/InstructionSimplify.cpp | 17 +- llvm/lib/Analysis/MemorySSA.cpp | 1 + llvm/lib/Analysis/ScalarEvolution.cpp | 2 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 13 +- llvm/lib/CodeGen/MachineVerifier.cpp | 26 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 46 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- llvm/lib/IR/Constants.cpp | 2 +- llvm/lib/Support/VirtualFileSystem.cpp | 4 +- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 2 +- llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 7 +- llvm/lib/Target/ARM/ARMCallingConv.cpp | 44 +- llvm/lib/Target/ARM/ARMCallingConv.td | 20 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 30 + llvm/lib/Target/ARM/ARMISelLowering.h | 11 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 24 +- llvm/lib/Target/ARM/ARMInstrNEON.td | 16 +- llvm/lib/Target/PowerPC/CMakeLists.txt | 1 + llvm/lib/Target/PowerPC/PPC.h | 7 +- llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp | 164 +++++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 4 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 19 + llvm/lib/Target/RISCV/RISCVISelLowering.h | 7 + .../Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 22 +- llvm/lib/Target/SystemZ/SystemZCallingConv.h | 7 + llvm/lib/Target/SystemZ/SystemZCallingConv.td | 27 + llvm/lib/Target/SystemZ/SystemZElimCompare.cpp | 13 +- llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp | 21 + llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 49 +- llvm/lib/Target/SystemZ/SystemZISelLowering.h | 2 +- llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp | 4 + .../Target/X86/X86AvoidStoreForwardingBlocks.cpp | 8 +- llvm/lib/Target/X86/X86FixupLEAs.cpp | 4 +- llvm/lib/Target/X86/X86FixupSetCC.cpp | 4 +- llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 16 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 275 +++++---- llvm/lib/Target/X86/X86IndirectBranchTracking.cpp | 4 +- llvm/lib/Target/X86/X86OptimizeLEAs.cpp | 6 +- llvm/lib/Target/X86/X86RegisterInfo.cpp | 3 + llvm/lib/Target/X86/X86RetpolineThunks.cpp | 12 +- .../lib/Target/X86/X86SpeculativeLoadHardening.cpp | 12 +- llvm/lib/Target/X86/X86Subtarget.cpp | 14 +- llvm/lib/Target/X86/X86Subtarget.h | 8 +- llvm/lib/Target/X86/X86WinAllocaExpander.cpp | 16 +- llvm/lib/Target/X86/X86WinEHState.cpp | 2 +- .../InstCombine/InstructionCombining.cpp | 7 +- .../Instrumentation/ControlHeightReduction.cpp | 2 +- .../Instrumentation/HWAddressSanitizer.cpp | 29 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 41 +- llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp | 4 +- llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp | 4 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 24 +- llvm/test/CodeGen/ARM/vrev.ll | 243 ++++++-- llvm/test/CodeGen/PowerPC/lower-massv-attr.ll | 29 + llvm/test/CodeGen/PowerPC/lower-massv.ll | 603 +++++++++++++++++++ llvm/test/CodeGen/RISCV/get-register-invalid.ll | 12 + llvm/test/CodeGen/RISCV/get-register-noreserve.ll | 38 ++ llvm/test/CodeGen/RISCV/get-register-reserve.ll | 34 ++ llvm/test/CodeGen/SystemZ/ghc-cc-01.ll | 103 ++++ llvm/test/CodeGen/SystemZ/ghc-cc-02.ll | 14 + llvm/test/CodeGen/SystemZ/ghc-cc-03.ll | 11 + llvm/test/CodeGen/SystemZ/ghc-cc-04.ll | 16 + llvm/test/CodeGen/SystemZ/ghc-cc-05.ll | 16 + llvm/test/CodeGen/SystemZ/ghc-cc-06.ll | 12 + llvm/test/CodeGen/SystemZ/ghc-cc-07.ll | 12 + llvm/test/CodeGen/SystemZ/la-05.ll | 31 + .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 13 +- llvm/test/CodeGen/Thumb2/mve-shufflemov.ll | 664 +++++++++++++++++++++ .../CodeGen/X86/avx512-intrinsics-fast-isel.ll | 16 +- llvm/test/CodeGen/X86/known-signbits-vector.ll | 319 +++++----- llvm/test/CodeGen/X86/pr34080-2.ll | 2 +- llvm/test/CodeGen/X86/shrink_vmul.ll | 202 ++++--- llvm/test/CodeGen/X86/vec_smulo.ll | 152 ++--- llvm/test/CodeGen/X86/vec_umulo.ll | 140 +++-- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 62 ++ .../HWAddressSanitizer/lazy-thread-init.ll | 39 -- .../Mips/mips32r6/valid-mips32r6-el.txt | 1 + .../Disassembler/Mips/mips32r6/valid-mips32r6.txt | 1 + .../Mips/mips64r6/valid-mips64r6-el.txt | 1 + .../Disassembler/Mips/mips64r6/valid-mips64r6.txt | 1 + llvm/test/MC/Disassembler/Mips/octeon/valid-el.txt | 31 + llvm/test/MC/Disassembler/Mips/octeon/valid.txt | 31 + .../Mips/{octeon-instructions.s => cnmips/valid.s} | 0 llvm/test/MC/SystemZ/insn-bad.s | 6 + llvm/test/MachineVerifier/live-ins-01.mir | 57 ++ llvm/test/MachineVerifier/live-ins-02.mir | 32 + llvm/test/MachineVerifier/live-ins-03.mir | 36 ++ llvm/test/Object/invalid.test | 7 +- .../Transforms/Inline/no-inline-line-tables.ll | 99 +++ llvm/test/Transforms/InstSimplify/fcmp-select.ll | 168 ++++++ .../test/Transforms/SLPVectorizer/X86/crash_gep.ll | 23 + llvm/test/tools/llvm-ar/mri-nonascii.test | 21 + llvm/test/tools/llvm-ar/mri-utf8.test | 23 - .../tools/llvm-readobj/elf-section-symbols.test | 85 +++ llvm/test/tools/llvm-readobj/elf-symbol-shndx.test | 113 +++- llvm/test/tools/yaml2obj/dynamic-symbols.yaml | 7 +- llvm/test/tools/yaml2obj/elf-sht-symtab-shndx.yaml | 8 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 68 ++- .../llvm/lib/Target/AArch64/AsmParser/BUILD.gn | 5 +- .../gn/secondary/llvm/lib/Target/AArch64/BUILD.gn | 10 +- .../gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn | 1 + .../llvm/lib/Target/RISCV/AsmParser/BUILD.gn | 5 +- .../gn/secondary/llvm/lib/Target/RISCV/BUILD.gn | 3 + .../secondary/llvm/lib/Transforms/Scalar/BUILD.gn | 2 +- .../secondary/llvm/unittests/Target/X86/BUILD.gn | 2 - .../llvm/unittests/Transforms/Utils/BUILD.gn | 2 +- 151 files changed, 4058 insertions(+), 1174 deletions(-) create mode 100644 clang/test/CodeGen/debug-info-no-inline-line-tables.c create mode 100644 lld/test/ELF/arm-exidx-empty-fn.s create mode 100644 llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp create mode 100644 llvm/test/CodeGen/PowerPC/lower-massv-attr.ll create mode 100644 llvm/test/CodeGen/PowerPC/lower-massv.ll create mode 100644 llvm/test/CodeGen/RISCV/get-register-invalid.ll create mode 100644 llvm/test/CodeGen/RISCV/get-register-noreserve.ll create mode 100644 llvm/test/CodeGen/RISCV/get-register-reserve.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-01.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-02.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-03.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-04.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-05.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-06.ll create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-07.ll create mode 100644 llvm/test/CodeGen/SystemZ/la-05.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-shufflemov.ll delete mode 100644 llvm/test/Instrumentation/HWAddressSanitizer/lazy-thread-init.ll create mode 100644 llvm/test/MC/Disassembler/Mips/octeon/valid-el.txt create mode 100644 llvm/test/MC/Disassembler/Mips/octeon/valid.txt rename llvm/test/MC/Mips/{octeon-instructions.s => cnmips/valid.s} (100%) create mode 100644 llvm/test/MachineVerifier/live-ins-01.mir create mode 100644 llvm/test/MachineVerifier/live-ins-02.mir create mode 100644 llvm/test/MachineVerifier/live-ins-03.mir create mode 100644 llvm/test/Transforms/Inline/no-inline-line-tables.ll create mode 100644 llvm/test/tools/llvm-ar/mri-nonascii.test delete mode 100644 llvm/test/tools/llvm-ar/mri-utf8.test create mode 100644 llvm/test/tools/llvm-readobj/elf-section-symbols.test