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from 760a278a3f5 [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. new a138ea5c865 [AArch64] Refactor the Exynos scheduling predicates new 2c91ebe7ab6 [x86] fix formatting; NFC

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Summary of changes: include/llvm/Target/TargetInstrPredicate.td | 2 +- lib/Target/AArch64/AArch64.td | 1 + lib/Target/AArch64/AArch64InstrInfo.cpp | 209 +-------------------- lib/Target/AArch64/AArch64InstrInfo.h | 9 - lib/Target/AArch64/AArch64SchedExynosM1.td | 122 ++++++------ lib/Target/AArch64/AArch64SchedExynosM3.td | 113 +++++------ lib/Target/AArch64/AArch64SchedPredExynos.td | 124 ++++++++++++ lib/Target/X86/X86ISelLowering.cpp | 36 ++-- .../llvm-mca/AArch64/Exynos/extended-register.s | 44 ++--- .../llvm-mca/AArch64/Exynos/register-offset.s | 29 ++- .../llvm-mca/AArch64/Exynos/shifted-register.s | 24 +-- 11 files changed, 314 insertions(+), 399 deletions(-) create mode 100644 lib/Target/AArch64/AArch64SchedPredExynos.td