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from 1636f16 Updating branches/google/testing to r264688 adds b76dcf4 [Codegen] Decrease minimum jump table density. adds f074043 [PowerPC] Refactor popcnt[dw] target features adds d2695ae [llvm-readobj] Support GNU style dyn-relocations adds 031bfc2 LiveVariables: Do not remove dead flags from vreg operands adds eacfdd5 RegisterPressure: Simplify liveness tracking when lanemasks a [...] adds f81b307 [SimlifyCFG] Prevent passes from destroying canonical loop st [...] adds 859d69a BitcodeReader: Allow METADATA_STRINGS to only have !"" adds c4a8612 AVX-512: fixed a bug in fp_to_uint pattern on KNL adds 98ebf8c fixed typo - CHECK-LABEL adds 5a15e95 Added 2 notes 1) Skylake and KNL support for X86 2) masked in [...] adds 0848da2 fixed typo - CHECK-LABEL adds 7c78d07 fix CHECK_NOT -> CHECK-NOT adds b5f67e4 [mips] Correct MIPS16 jal/jalx to have uimm26 offsets and add [...] adds b4efa11 [mips] Test commit: Mark insertNoop as dead code (NFC) adds 7ef71aa [llvm-readobj] NFC: Remove unneeded parenthesis adds bc26aeb [ThinLTO] Use new GlobalValue::getGUID helper (NFC) adds 338aaed Test commit access adds 4fdd8ba regenerate checks adds 706afb2 Reformat a comment in InlineSimple.cpp. NFC adds 2029771 Make InlineSimple's one-arg constructor explicit. NFC adds 2bf1827 [SCEV] Use Operator::getOpcode instead of manual dispatch; NFC adds f504359 [SCEV] Extract out a MatchBinaryOp; NFCI adds 65a7ad2 [x86] add tests to show current memset codegen adds d9e9e2b Swift Calling Convention: add swiftself attribute. adds b65f550 Add MachineVerifier check for AllVRegsAllocated MachineFuncti [...] adds 54cc8d7 Add support for no-jump-tables adds 5826030 [asan] Make the global_metadata_darwin.ll test require El Cap [...] adds 4027520 [ThinLTO] Remove post-pass metadata linking support adds b957e26 Revert "[asan] Make the global_metadata_darwin.ll test requir [...] adds 0ee5788 IR: Add DbgInfoIntrinsic::getVariableLocation adds f27ef7a LiveVariables: Fix typo and shorten comment adds 1df6732 MachineVerifier: On dead-def live segments, check that corres [...] adds 499797f [SPARC] Use AtomicExpandPass to expand AtomicRMW instructions. adds ae7cf58 Fix some bugs in the posix output of llvm-nm. Which is docum [...] adds 68b4704 Clarifying some of the requirements for building with Visual [...] adds d239bc5 Add a print method to MachineFunctionProperties for better er [...] adds deb808c use FileCheck and auto-check-generation script for exact checking adds f8ccc7e Upgrade some wildly anachronistic debug info in testcases. adds d6dc9e0 [LoopDataPrefetch] Make more member functions private, NFC. adds 513c245 MachineSink: make shouldSink a TII target hook adds 5a417a1 ADCE: Remove debug info intrinsics in dead scopes adds 7544ffc [libFuzzer] more docs adds 8bb475f [libFuzzer] more trophies adds 0a20d99 [tsan] Do not instrument reads/writes to instruction profile [...] adds 515ab47 [LoopDataPrefetch] Centralize the tuning cl::opts under the pass adds 1e5a354 [PPC] Remove -ppc-loop-prefetch-distance in favor of -prefetc [...] adds f6d6e72 [Aarch64] Turn on the LoopDataPrefetch pass for Cyclone adds 2e682ed [MemorySSA] Change how the walker views/walks visited phis. adds 6be6cca [PGO] Handle invoke inst in IR based icall instrumentation adds 1f7adda [x86] Extract a helper function to compute the full addressin [...] adds ff01852 [MemorySSA] Make the visitor more careful with calls. adds dfdbebc BitcodeReader: Fix weird whitespace, NFC adds 540e0f5 IR: Constify LLVMContext::discardValueNames, NFC adds 8c5f0de [docs] Add gpucc publication and tutorial. adds 40e9bee [CodeGen] Mark EVT:getExtendedSizeInBits() as LLVM_READONLY. adds e56cb5f [x86] Fix a horrible bug in our lowering of x86 floating poin [...] adds cd30900 [VectorUtils] Don't try and truncate PHIs to a smaller bitwidth adds c079cbf [X86][SSE] Added tests for clearing upper bits of vector elements adds d9529c5 gold-plugin: Fixed typo in an error message. adds 4a03fa3 [NVPTX] Avoid temporary std::string and make single-use funct [...] adds b85e39b [X86][SSE] Test the legalization of vector comparison results adds a6e6ae2 [ThinLTO] Serialize the Module SourceFileName to/from LLVM assembly adds 5a4fec2 [X86][XOP] BITREVERSE lowering using VPPERM adds e1eb43b Revert "[ThinLTO] Serialize the Module SourceFileName to/from [...] adds e0d3b85 Remove HasFnAttribute guards to getFnAttribute calls adds 5254fb9 [SystemZ] Add nop and nopr InstAliases. adds d3adac5 AMDGPU/SI: Enable lanemask tracking in misched adds 7725fd8 AMDGPU/SI: Improve MachineSchedModel definition adds 34be7e6 [PGO] Use ArrayRef in annotateValueSite() adds f3ba4d1 [cmake] Allow EH usage with clang-cl adds db91435 [cmake] Add -fms-compatibility-version=19 when clang-cl gives [...] adds 21db7b7 [AArch64] Fix warnings pointed out by Hal. adds 2dec5fc Restore "[ThinLTO] Serialize the Module SourceFileName to/fro [...] adds 564787f [cmake] Instead of testing char16_t for MSVC compat, directly [...] adds 3744401 [PGO] PGOFuncName in LTO optimizations adds dfdada0 [LoopVectorize] Don't vectorize loops when everything will be [...] adds f5526fc Add a copy constructor to StringMap adds 18af505 test: Remove a test for a transform that hasn't existed in 5 years. adds 3daeed4 [PassManager] Make PassManagerBuilder::addExtension take an s [...] adds 6feb171 [NVPTX] Make NVVMReflect a function pass. adds 8f62cbe [X86][AVX] Ensure EltsFromConsecutiveLoads tests the entire v [...] adds 5fa9211 Add #include <functional> to PassManagerBuilder, now that it [...] adds 82ef54d [IndVarSimplify] Don't insert after a catchswitch adds 532e88a LegalizeDAG: Don't replace vector load with integer unless legal adds af539c4 LegalizeDAG: Don't replace vector store with integer if not legal adds 59a288b Silencing warnings from MSVC 2015 Update 2. All of these chan [...] adds c3260ca fix typos adds af289e0 Cloning: Reduce complexity of debug info cloning and fix corr [...] adds d47ed92 Use existing PrintEscapedString in AssemblyWriter adds f965621 AMDGPU: Constant folding for frexp_mant adds e8cd894 AMDGPU: Add frexp_exp intrinsic adds cc01455 Update copyright year to 2016. adds 8c3b4a5 Avoid unnecessary #include; NFC adds 137f4d9 CodeGen: Factor out code for tail call result compatibility c [...] adds b667d69 [X86] Enable call frame optimization ("mov to push") not only [...] adds d3f401b Add some more triples after r264966 adds de76568 Introduce a @llvm.experimental.guard intrinsic adds 0fb6150 Fix case confusion. adds dc6860f [PowerPC] Load two floats directly instead of using one 64-bi [...] adds a528f3f [DebugInfo] Subprograms should belong to a CU. adds 6c25a70 [X86] Use MVT instead of EVT in code called after legalization. adds bf8c7c9 [SCEV] NFC code motion to simplify later change adds e840b37 [SCEV] Track NoWrap properties using MatchBinaryOp, NFC adds 2b00aae Delete trailing whitespace adds 0d31c7f [InstCombine] Fix incorrect rule from rL236202 adds 0bfce38 Indentation fix in SystemZInstrInfo.cpp adds 12c0e3a Silence warnings in OCaml bindings adds 4e6485e [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instruction [...] adds 638cd03 [TTI] Let the cost model estimate ctpop costs based on legality adds 8cd0a25 [mips] Range check simm9 and fix a bug this revealed. adds 9daabae Prevent X86ISelLowering from merging volatile loads adds 2693fe3 [mips] Split mem_msa into range checked mem_simm10 and mem_si [...] adds 8fef4bc [AMDGPU] Disassembler: support for DPP adds dc022ba [IFUNC] Introduce GlobalIndirectSymbol as a base class for al [...] adds 15d116a [mips] Range check simm11 and mem_simm11. adds 2fcdb70 [mips] Range check simm16 adds ca50bf5 [PowerPC] Remove incorrect use of COPY_TO_REGCLASS in fast isel adds 7a8b700 [AArch64] Handle missing store pair opportunity adds 5a73f4b [PowerPC] Basic support for P9 atomic loads and stores adds 9bb23c0 [PowerPC] Correctly compute 64-bit offsets in fast isel adds 285cad0 Don't use potentially invalidated iterator adds d4a2e32 Minor code cleanup /NFC adds cbe8858 [PowerPC] Attempt to fix fast-isel-i64offset.ll failure adds fe4032c More checks in win32-seh-nested-finally.ll after comment on r264966 adds b098ec7 [AMDGPU] enable few disassembler tests that were mistakenly m [...] adds f98b9a5 [x86] use SSE/AVX ops for non-zero memsets (PR27100) adds 051ce12 [PGO] use emplace_back. NFC. adds 54993bc [PPC] basic support for Power 9 direct move instructions adds 1372b02 [lanai] isBrImm should accept any non-constant immediate. adds 30a91fe [lit][googletest] Handle upstream gtest output adds f864a32 Change eliminateCallFramePseudoInstr() to return an iterator adds 4d88edd [X86] Merge adjacent stack adjustments in eliminateCallFrameP [...] adds df69147 [ARM] Expand v1i64 and v2i64 ctpop. adds 9610a42 [CMake] Provide the ability to skip stripping when generating dSYMs adds b5a1802 Preserve extern_weak linkage in CloneModule. adds fad1a9a [X86][SSE] Some basic tests for variable shuffles adds b7cecba Revert r265039 "[X86] Merge adjacent stack adjustments in eli [...] adds e2d3b8c [PowerPC] Add a late MI-level pass for QPX load/splat simplification adds d8e8cf0 [x86] add memset tests to show another potential improvement adds 0733547 [PowerPC] Cleanup test/CodeGen/PowerPC/qpx-load-splat.ll adds 9bba5e5 Add disk_space() to llvm::fs adds 2581c8c [AArch64] Allow loads with imp-def to be handled in getMemOpB [...] adds 1efc1b6 Fixed signed/unsigned warning adds 2f955d5 fix typo; NFC adds c7e4223 Wdocumentation parameter fix adds 54136ef [NVPTX] Infer __nvvm_reflect as nounwind, readnone adds 7689004 Preserve blockaddress use edges in the module splitter. adds 99811fe Revert "Add disk_space() to llvm::fs" adds e6ec1e3 Fix PR26940 where compiles times regressed massively. adds 47094ef [AsmPrinter] Print aliases in topological order adds c62e7cc Object: Correctly read thin archives containing absolute paths. adds 6ddf7da Object: Add function for moving thin archive object buffer ve [...] adds 87cbc4f Move asm-printer-topological-order.ll to PowerPC backend adds f5e9ba6 Add disk_space() to llvm::fs adds 7f4c23b Create thin archive in GNU format to fix test on OS X. adds 44f51d9 lit: python3 compatibility fix adds 3ddee86 Use const ref instead of value for Twine in the disk_space() API adds ca1975c clang-format the large enum definitions in LLVMBitCodes.h adds ff85de8 Follow-up to r265036: I got these iterators mixed up adds 39bb84a Move the DebugEmissionKind enum from DIBuilder into DICompileUnit. adds 4964c02 Fix a captialization error in r265077. adds 120652a Revert "Add disk_space() to llvm::fs" adds 7876f64 testcase gardening: update the emissionKind enum to the new s [...] adds e744acb Add disk_space() to llvm::fs adds 5fe8a3c [LoopVectorize] Don't unconditionally print vectorization dia [...] adds eb9d3a8 Fix Windows build (typo in disk_space() implementation) adds 55dc0e4 [ifcnv] Add brief comment explaining what ifcnv is. adds 4d24c4a [NVPTX] Annotate some instructions as hasSideEffects = 0. adds 8c5dadb [NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect. adds 6f3ab0f [NVPTX] Add a truncate DAG node to some calls. adds 77d0bd5 Protect some assertions with NDEBUG rather than DEBUG(). adds 7effb55 Revert "Protect some assertions with NDEBUG rather than DEBUG()." adds 696fe52 Add support for computing SHA1 in LLVM adds 515396c Add a module Hash in the bitcode and the combined index, impl [...] adds 433ac20 Add missing test for the "Module hash in bitcode" added in r265095 adds 0835dfe Fix Sub-register Rewriting in Aggressive Anti-Dependence Breaker adds 4c1839f AArch64ISelLowering: Remove unused variables/arguments; NFC adds 3258a27 Don't use an i64 return type with webkit_jscc adds d36742f Don't insert lifetime end markers on deoptimizing returns adds 6584a7a47 Don't insert stackrestore on deoptimizing returns adds 1fc660f Revert "Add support for computing SHA1 in LLVM" adds cc2a78f3 Use range-based for loops. NFC. adds 3c31ac1 Improve CHECK-NOT robustness of dllexport tests adds 74c634c Add support for computing SHA1 in LLVM adds 167ce3f Const correctness in raw_sha1_ostream (NFC) adds 7c5d570 Fix S390 big endian detection adds d4b1021 Fix MSVC warning "comparison of integers of different signs" (NFC) adds d2f4701 Add a module Hash in the bitcode and the combined index, impl [...] adds ff2f27d [PPC64] Bug fix: when enabling sibling-call-opt and shrink-wr [...] adds 51f5548 Add a libLTO API to stop/restart ThinLTO between optimization [...] adds 145384c [OCaml] Reinstate data_layout adds f4430ca [OCaml] Use LLVMCreateMessage with constant strings when call [...] adds 03b2cf6 ThinLTO: move ObjCARCContractPass in the CodeGen pipeline adds 3cc1102 [AArch64] Better errors for out-of-range fixups adds b36a459 Fix for pr24346: arm asm label calculation error in sub adds b2ae363 [X86] Introduce Lakemont CPU. adds db555c9 [ThinLTO] Fix uninitialized flags. adds c950e91 [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA adds 36ce33d [X86][AVX512] Regenerated intrinsics tests adds b632c25 [x86] Remove redundant call to setTargetDAGCombine for BUILD_ [...] adds 7d11146 [AMDGPU] fix MADAK/MADMK instructions operand namings to matc [...] adds 9f0f7be [PGOProfile] Rename a test to make it more reusable, NFC adds c9fc333 [ADT] Make StringMap's tombstone aligned. adds fb73eb7 [x86] avoid intermediate splat for non-zero memsets (PR27100) adds a7f5174 [PGO] Refactor PGOFuncName meta data code to be used in clang adds 3f538b5 [SLPVectorizer] Don't insert an extractelement before a catchswitch adds 8f6f6d0 [InstCombine] Don't sink an instr after a catchswitch adds 4225a30 [AArch64] Fix a typo. NFC. adds 7966329 [x86] avoid intermediate splat for non-zero memsets (PR27100) adds 2a46435 [X86][SSE] Regenerated the vec_set tests. adds 08e2214 [X86][SSE] Regenerated vec_setcc tests. adds 208a8fc [x86] add an SSE1 run for these tests adds 1ec923a [sancov] save entry block from pruning (it is always full dominator) adds b258b0e [X86][SSE] Regenerated vector sdiv to shifts tests adds 059753c AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2} adds 22b6378 [X86][SSE] Regenerated vec_logical tests. adds 31624e42 [x86] add an SSE2 + fast-unaligned accesses run for memset no [...] adds 1bb3a19 [X86][SSE] Regenerated vec_partial tests. adds f4643f6 [libfuzzer] adding license headers to cpp files adds 3028829 LowerBitSets: Move declarations to separate namespace. adds 07284c3 Remove useless check for ThreadModel==Single in ARMISelLoweri [...] adds c9b8f68 [X86][SSE] Regenerated the vec_insert tests. adds ba623ac Fix buildbot lldb-amd64-ninja-netbsd7 failure adds 130ab6b Update owners to reflect recent changes adds 047f650 [X86][SSE] Regenerated the vec_extract tests. adds 68b3b2c [X86][SSE] Regenerated comparison mask and float immediate tests adds e4a9787 [X86][SSE] Vector i64 load tests adds 44e6fff [X86][SSE] Regenerated vector float tests - fabs / floor(etc. [...] adds 4bda882 Swift Calling Convention: add swifterror attribute. adds 03669a5 ThinLTO: special handling for LinkOnce functions adds fbce329 Add missing emissionKind flags to the DICompileUnits of sever [...] adds 6bde7e4 Make DIASession work if msdia*.dll isn't registered. adds 01dde41 AArch64: avoid clobbering SP for dead MOVimm pseudos. adds e7eaa87 [PGO] Use a helper function to find all indirect call-sites adds 88fbbb3 Fix -Wpedantic warning about extra semi-colon adds 22706dc Add Cache Pruning support adds 64a77d0 Rename Context::discardValueNames() to shouldDiscardValueName [...] adds b3cb9bc 80 lines column after renaming "shouldDiscardValueNames" (NFC) adds 4ac4b88 ThinLTO: add module caching handling. adds 5f76ad9 Create a typedef GlobalValue::GUID for uint64_t and RAUW (NFC) adds b659366 Revert "ThinLTO: add module caching handling." adds 3983416 constify GlobalValue::getGUID() and GlobalValue::getGlobalIde [...] adds f451000 wip adds 47f754a Fix "warning: variabl 'XX’ set but not used" in release build [...] adds c039993 Reverts r265219. adds c3ddf2d [X86][AVX] Added vector float truncation (double2float) tests adds bfce5b2 BitcodeReader: Check for unresolved function metadata adds 91ae239 BitcodeWriter: Further unify function metadata, NFC adds 40247d2 Fix doxygen comments from r265224, NFC adds be4ea76 Bitcode: Try to emit metadata in function blocks adds ec78cb0 Document end of anonymous namespaces, NFC adds eeb2c7e ValueMapper: Add support for seeding metadata with nullptr adds f9fa155 Linker: Remove IRMover::isMetadataUnneeded indirection; almost NFC adds 1cb8567 Rename FunctionIndex into GlobalValueIndex to reflect the rec [...] adds dcf3121 Linker: Avoid unnecessary work when moving named metadata adds 75949bd Remove redundant assertion after cast, NFC adds 715c242 Linker: Split mapUnneededSubprograms into two; almost NFC adds 3aae1a6 AArch64: support .cpu directive adds 6bf924b [X86][AVX512] Added AVX512 comparison tests adds 3021e42 [X86][SSE] Added 1024-bit vector comparison tests adds 3d20af9 [mips][microMIPS] Revert commits r264245 and r264248. Commit [...] adds 5a07bd0 [lanai] Fix for LanaiDelaySlotFiller and LanaiMCInstLower.cpp adds 4e5a97a [SimplifyLibCalls] Garbage collect dead code. adds 55991df AVX-512: Load and Extended Load for i1 vectors adds 8e620e7 Mark some FP intrinsics as safe to speculatively execute adds 1183866 [X86] Tidied up X86ISD instruction nodes. NFCI. adds 6a4952d [CodeGenPrepare] Avoid sinking soft-FP comparisons adds ad9ddc5 [CodeGenPrepare] Fix r265264. adds baf1e7a [X86][SSE] Support for MOVMSK signbit extraction instructions adds 8714037 [X86][SSE] Refreshed MOVMSK sign bit tests adds f92cbb9 ValueMapper: Introduce Mapper helper class, NFC adds 9786f33 ValueMapper: Split out mapSimpleMetadata, NFC adds 7ab7e0e [CodeGenPrepare] Fix r265264 (again). adds 47ee3e9 ValueMapper: Avoid recursion in mapSimplifiedMetadata, NFC adds d00e703 [X86] Removed duplicate code. adds eb8001a Work around MSVC failure from r265273 adds 23e4036 ValueMapper: Disallow metadata mapping recursion through mapValue adds 7527b8c Various style fix in Core.h/Core.cpp . NFC adds 1400947 IR: Make MDNode::Context private, NFC adds 0568c3d IR: Lazily create ReplaceableMetadataImpl on MDNode adds 5b62b45 [DebugInfo] Fix tests in Assembler/ adds d6f84f2 ValueMapper: Remove old FIXMEs; almost NFC adds bd28e70 AVX-512: Truncating store for i1 vectors Implemented truncsto [...] adds 6bb99d2 Fixup r265277 [-Wdocumentation] adds 972bf9c [SystemZ] Support llvm.frameaddress/llvm.returnaddress intrinsics adds 3b8a73e [SystemZ] Support ATOMIC_FENCE adds f000d19 [SystemZ] Add compare-and-branch instructions to MC adds 3b14df5 [mips] Range check simm32 and fold MIPS16's imm32 into simm32. adds d31cb9b Replace analyzeSiblingValues with new algorithm to fix its co [...] adds ccfc215 Fix unused var warning caused by r265309. adds 9b3da26 Add MachineFunctionProperty checks for AllVRegsAllocated for [...] adds 0a27f40 Document standard substitutions defined by lit. adds e19a68b Revert r265309 and r265312 because they caused some errors I [...] adds cfaa4e0 Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty adds 3188534 [DependenceAnalysis] Check if result of getConstantPart is null adds 3555f1f fix documentation comments; NFC adds 39af64d [ThinLTO] Augment FunctionImport dump with value name to GUID map adds 0a41a31 [ThinLTO] Add option to dump value name to GUID mapping adds bac1dd9 ARM, AArch64, X86: Check preserved registers for tail calls. adds d163758 [PGO] Avoid instrumenting direct callee's at value sites. adds f0a5829 Revert r263460: [SpillPlacement] Fix a quadratic behavior in [...] adds 1f756b1 Beef up some dllexport tests. adds 7e69f99 Fix bot errors from r265327, exact GUID which depends on path adds 06022d8 Enable unroll for constant bound loops when TripCount is not [...] adds 5ef7ab8 Re-commit r265039 "[X86] Merge adjacent stack adjustments in [...] adds 566a35a clang-format llvm-as.cpp (NFC) adds e393968 CodeGen: Remove dead code in TailDuplicate adds ee68481 Clean up calls to WriteBitcodeToFile (NFC) adds 7b7e713 test: Always treat .mir files as tests even outside of CodeGen/MIR adds bc77422 MachineScheduler: Ignore COPYs with undef/dead op in CopyCons [...] adds 52bd5a7 Revert "CodeGen: Remove dead code in TailDuplicate" adds 45cace0 Style update in Core.h/Core.cpp . NFC adds 952fa5f fix typos; NFC adds 2870284 use range loop; NFCI adds 3918651 Fix non-determinism in order of LLVM attributes adds e4b6431 Lanai: fix -Wpedantic warnings adds 2187312 Don't fold double constant to an integer if dest type not integral adds 3f3bbdb Lanai: fix -Wsign-compare warning adds f90bc5f Docs: dampen story time for atomics adds 3890d33 [ThinLTO] Refactor some common code into getGlobalValueInfo m [...] adds bf3b2ca [Support] Fix an invalid character escaping in string literal [...] adds 51a06a2 [IFUNC] Use GlobalIndirectSymbol when aliases and ifuncs have [...] adds f0a7cfd Add parentheses around `&&` within `||` to avoid compiler war [...] adds 2b45aff Set the thumb flag for thumb symbols coming from an ELF file adds 51dcabb Adds the ability to use an epilog remainder loop during loop [...] adds 515b870 [NVPTX] Handle ldg created from sign-/zero-extended load adds 521f98c [mips] MIPSR6 Compact jump support adds 2b8aed7 [llvm-c] Expose LLVM{Get,Set}ModuleIdentifier adds afa4f41 Don't delete empty preheaders in CodeGenPrepare if it would c [...] adds c5c3d28 Centralize the definition of a few types. NFC. adds 8d7c100 Add missing test for the "Don't delete empty preheaders" adde [...] adds 00d9a04 Use ArrayRef for contiguous areas in ELF. NFC. adds 7b0de349 [BlockPlacement] Remove an unnecessary continue adds e1d66f4 [AMDGPU] Emit linkonce and linkonce_odr symbols adds e0d1a47 [ARM] Cleanup of smul and smla instruction descriptions adds 148a26a [lanai] LanaiSetflagAluCombiner more conservative adds 89372a5 [TableGen] AsmMatcherEmitter.cpp: replace a sequence of "if" [...] adds 4d9b8c9 check or check-next the first line of the function too adds 01d8b6a WebAssembly: fix cfg-stackify test adds f87ded9 [x86] regenerate checks adds 503ff5b [InstCombine] regenerate checks adds 037ba97 llvm-dwp: Simplify hashing code a bit adds d8f98f3 add example usage and workflow to --help output adds cd3afd5 add tests to show missing optimization from D18230 adds 2bf0ebe Swift Calling Convention: swifterror target-independent change. adds 25f2ff1 fix documentation comments; NFC adds 8a1ae61 [Support] clang-format Error.h. adds 278bb5d [GlobalISel] Add the skeleton of the RegBankSelect pass. This [...] adds ec856b3 [AArch64][Test] Do not override the suffixes for test cases. adds ace0cc8 fix typo; NFC adds 3a27360 fixed to discard earlier advertising adds 9b71076 [GlobalISel] Add a class, RegisterBank, to represent register banks. adds c224d81 [Support] Add a checked flag to Expected<T>, require checks b [...] adds 90af9e70 [X86] Simplify early-exit check. NFC. adds a4e8222 [X86] Add tests for ATOMIC_LOAD_OP EFLAGS reuse. NFC. adds baea9b2 [GlobalISel] Add the RegisterBankInfo class for the handling [...] adds db4b54f [X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC. adds cb6a565 [llvm-rtdyld] Fix the return type on ErrorAndExit. adds fe34a37 llvm-dwp: Handle dwo files produced by GCC adds 9a7a3bc Fix Clang-tidy modernize-deprecated-headers warnings in remai [...] adds cdf87d0 [TargetRegisterClass] Improve the comment for how to use getS [...] adds 15121b5 ValueMapper: Rewrite Mapper::mapMetadata without recursion adds 46c3acf llvm-dwp: Handle GCC's use of multiple debug_types.dwo sectio [...] adds f45d327 Make constructors for final subclasses of Constant private, NFC adds 2707ee3 Revert "Fix Clang-tidy modernize-deprecated-headers warnings [...] adds aa40fb6 [RegisterBank] Provide a way to check if a register bank is v [...] adds ef94029 IR: Add missing assertion for ConstantVector::ConstantVector adds 062bf7c [RegisterBankInfo] Implement the methods to create register banks. adds 3444a40 Try to appease MSVC after r265456 adds d7773c0 IR: Introduce ConstantAggregate, NFC adds 7484230 Minor code cleanups. NFC. adds ccd741b [RegisterBankInfo] Make addRegBankCoverage more capable to ea [...] adds ea1a7b0 Try harder to appease MSVC after r265456 adds 6077d14 [RegisterBank] Add printable capabilities for future debugging. adds a8ddf55 [CFLAA] Fix PR27213; incorrect tagging of args/globals adds 1f2bf92 [RegisterBankInfo] Add debug print to check how the initializ [...] adds 2b1f046 [RegisterBank] Implement the verify method to check for the o [...] adds 1f7638e Swift Calling Convention: add swiftcc. adds 9c4431f Faster stack-protector for Android/AArch64. adds cf18232 Swift Calling Convention: swiftcc for ARM. adds ca7369a [Target] Add an accessor to the register bank information. adds 5a3e3ec [Target] Remove a deprecated comment. adds 0ed4be7 [RS4GC] Better codegen for deoptimize calls adds 8e366b3 [RS4GC] NFC cleanup of the DeferredReplacement class adds 6443af0 [RegisterBankInfo] Simplify the API for build a register bank [...] adds 9c7eb24 [AArch64] Initial implementation of the targeting of the regi [...] adds fe735e5 [DebugInfo] Fix tests so that each subprogram belongs to a CU. adds 7176018 [RegisterBankInfo] Add missing include for assert. adds c37faf2 [RegisterBankInfo] Include RegisterBank.h. We actually need t [...] adds 731666e [SLPVectorizer] Vectorize libcalls of sqrt adds 43e8875 AArch64CodeGen: Make AArch64RegisterBankInfo.cpp optional alo [...] adds 43f537f AMDGPU: Document address space mapping adds 6dd7334 Lower @llvm.experimental.deoptimize as a noreturn call adds 376f5ba [RS4GC] Add a comment adds c77546e [Power9] Implement copy-paste, msgsync, slb, and stop instructions adds ff2190e [Power9] Implement add-pc, multiply-add, modulo, extend-sign- [...] adds 4f461ca [ppc64] Enable sibling call optimization on ppc64 ELFv1/ELFv2 abi adds 13d5c58 AsmParser: Don't crash on unresolved !tbaa adds 1570984 ValueMapper: Fix delayed blockaddress handling after r265273 adds 1685c6f LivePhysRegs: Remove redundant check adds 72b4fa0 LivePhysRegs: removeReg() must remove aliased registers adds dc2f859 RegisterScavenger: Take a reference as enterBasicBlock() argument. adds 525c4ba AArch64: Fix compile error adds d797524 [IRVerifier] Avoid crashing on an invalid compile unit. adds ce42332 [IRVerifier] Don't crash on invalid DIFile inside DISubprogram. adds 100a00c Add parentheses to silence warning. adds f504f6f Revert "[IRVerifier] Don't crash on invalid DIFile inside DIS [...] adds e49dfa7 IRMover: Steal arguments when moving functions, NFC adds adb72b9 IR: Move MDStrings to a BumpPtrAllocator adds 8b680c2 [SLPVectorizer] Vectorizing the libm sqrt to llvm's sqrt intr [...] adds 6b74529 [ppc64] Temporary disable sibling call optimization on ppc64 [...] adds 864fed9 [AArch64][CodeGen] NFC refactor AArch64InstrInfo::optimizeCom [...] adds 39fbde6 [SCEV] Introduce a guarded backedge taken count and use it in [...] adds b0bab88 Simplify logic. NFC. adds d348963 [AMDGPU] AsmParser: disable DPP for unsupported instructions. [...] adds 89e8236 Revert r265535 until we know how we can fix the bots adds 1145b58 Recommit r265309 after fixed an invalid memory reference bug [...] adds bc6e963 [RegisterBankInfo] Inline the destructor to avoid link-time e [...] adds 505761b [AArch64] Use the default constructor of RegisterBankInfo whe [...] adds 496db86 [AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support. adds 374df65 Revert "Re-commit r265039 "[X86] Merge adjacent stack adjustm [...] adds 67f0225 [RegisterBankInfo] Add a couple of helper classes for the fut [...] adds 8950a8d Revert "[AMDGPU] llvm-objdump: Minimal HSA Code Object disass [...] adds 6f5e1e2 [RegisterBankInfo] Add a verify method for the PartialMapping [...] adds 560a956 [RegisterBankInfo] Implement the verify method for the ValueM [...] adds 93b7254 LoopUnroll: only allow non-modulo Partial unrolling when Runt [...] adds 327ecef Revert r265450 "[X86] Reuse EFLAGS and form LOCKed ops when o [...] adds a80c065 [MachineRegisterInfo] Document what is the expected metric fo [...] adds a4b0d0e Loop Unroll: add options and tweak to make Partial unrolling [...] adds e33ae02 [RegisterBankInfo] Implement the verify method of the Instruc [...] adds 12ea314 [RegisterBankInfo] Make the destructor public... that may be useful! adds 65e2c25 [AArch64] Teach the subtarget how to get to the RegisterBankInfo. adds acad7be [AArch64] Change the CMake to avoid to build GlobalISel relat [...] adds 1ebdc6b vim: add missing keyword adds 4bbf81a [RegisterBankInfo] Add methods to get the possible mapping of [...] adds b5dd9ac [RegisterBankInfo] Add a method to get the mapping RegClass - [...] adds 9148a0a IR: Stop explicitly clearing the MDStringCache adds a15c0e9 IR: Use DenseSet instead of DenseMap for ConstantUniqueMap; NFC adds 8c06939 [RegisterBankInfo] Add an helper function to get the size of [...] adds eb6436d [IRVerifier] Prefer dyn_cast<> over isa<> + cast<>. adds fe58f90 [RegisterBankInfo] Provide a default constructor for Instruct [...] adds d8c5d5c [gold] Save bitcode for module partitions (save-temps + split [...] adds d030a6c [RegisterBankInfo] Call the other constructor of InstructionM [...] adds 0fad13d [RegisterBankInfo] Get rid of the assert in the constructor o [...] adds fd0bc4e [IRVerifier] Don't crash on invalid DIFile inside DISubprogram. adds e098312 Revert "[RegisterBankInfo] Add methods to get the possible ma [...] adds ea7a0c04 AMDGPU: Add a shader calling convention adds 0cfb927 Put quotes around #error string. adds dd697e3 regenerate checks adds b2bc21b [PPC] Use VSX/FP Facility integer load when an integer load's [...] adds a154e6b [MBP] Remove an unused function parameter adds b36d1a8 NFC: make AtomicOrdering an enum class adds d50171b [RegisterBankInfo] Add methods to get the possible mapping of [...] adds 243a05e [LoopUnroll] Fix the way we update DT after complete unrolling. adds c6bf9be Thread Expected<...> up from createMachOObjectFile() to allow [...] adds 2a41371 [llvm-c] Add LLVMGetValueKind. adds 2bfe8f2 Fix the compare-clang diff error introduced by r265547. adds fb23bd1 ValueMapper: clang-format ValueMapper.h, NFC adds f593646 [sancov] enabling coverage edge pruning by default. adds 3026bc6 Fix a race condition in support library ThreadPool. adds 9edae32 [RegisterBankInfo] Add an helper function to get the size of [...] adds 1c74502 Re-commit r265039 "[X86] Merge adjacent stack adjustments in [...] adds c654f98 [RegisterBankInfo] Implement a target independent version of [...] adds 15c5800 Follow-up for r265605: don't mutate vector we're iterating. adds d04a20c [AArch64] Teach RegisterBankInfo about the mapping of registe [...] adds fff8357 IR: RF_IgnoreMissingValues => RF_IgnoreMissingLocals, NFC adds 7187317 [AArch64] Teach RegisterBankInfo about the CC register bank. [...] adds a103558 ValueMapper: Make LocalAsMetadata match function-local Values adds 5c7a97c ValueMapper: Allow RF_IgnoreMissingLocals and RF_NullMapMissi [...] adds 37a560f [X86] Refresh and tweak EFLAGS reuse tests. NFC. adds 8465c13 [X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC. adds fcdd17b Revert "ValueMapper: Make LocalAsMetadata match function-loca [...] adds 928c8da Revert "[BlockPlacement] Remove an unnecessary continue" and [...] adds e0762df Fix the sanitizer bootstrap error in r265547. adds e31b144 Do some refactoring in the LLVM C API echo test to remove dup [...] adds b178818 [MBP] Remove an unused function parameter adds 3b594ea [BlockPlacement] Remove an unnecessary continue adds 514b003 [AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support. adds 405e645 [X86][SSE] Add support for VZEXT constant folding adds e655757 [CMake] Check for sys/types.h in config-ix.cmake adds 393a60e fix r265645: target dependent printf formatting flags. adds 47d60da Make helper functions static. NFC. adds 719a4bd InlineSpiller.cpp: Escap @ in r265547. [-Wdocumentation] adds ba49223 [GCC] Attribute ifunc support in llvm adds bf5cff2 Fix test/Assembler/ifunc-asm.ll test on hexagon-elf bots adds 30c5dec [AMDGPU] fix readlane/readfirstlane src vgpr operand type. adds c2d9280 AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::in [...] adds 6ff814c [PPC] Enable transformations in PPCPassConfig::addIRPasses at O2 adds d04d5a9 [GVN] Fix handling of sub-byte types in big-endian mode adds fb9ead0 NFC: disallow comparison of AtomicOrdering adds ff889a6 [GVN] Address review comments for D18662 adds a2a5c79 [IR/Verifier] Merge two ifs into one. NFC. adds 05fbbee [SystemZ] Implement conditional returns adds d393432 [X86]: Fix for PR27251. Differential Revision: http://reviews [...] adds 78886ec [SystemZ] Fix build break from r265689 adds 8a6b9f2 [PPC] Added a note to release notes adds 8074e60 [RegisterBank] Rename RegisterBank::contains into RegisterBan [...] adds b928706 [MachineRegisterInfo] Track register bank for virtual registe [...] adds 594f22b [X86][SSE] Added bitmask pattern shuffle tests adds f77a6ec [RegisterBankInfo] Provide a default constructor for Instruct [...] adds 83fadc5 [RegisterBankInfo] Change the signature of getSizeInBits to f [...] adds f9b1311 [RegisterBankInfo] Provide a target independent helper functi [...] adds f1b763c [RegisterBankInfo] Add more details on the expectation of get [...] adds 13588d8 [RegBankSelect] Initial implementation for non-optimized outp [...] adds f313dae AMDGPU/SI: Add latency for export instructions adds 62aa62a AMDGPU/SI: Implement atomic load/store for i32 and i64 adds e8aba9b [GlobalISel] Add RegBankSelect hooks into the pass pipeline. [...] adds 4db7b50 [AArch64][CallLowering] Do not build the API if GlobalISel is [...] adds 4216f71 [AArch64] gcc does not like litteral without quotes even on p [...] adds cdc4605 [TargetRegisterInfo] Fix the comment of SuperRegClassIterator [...] adds a8e98eb [AArch64] Get rid of some GlobalISel ifdefs. adds a5bbcb5 Do not select EhPad BB in MachineBlockPlacement when there is [...] adds 7880f43 [RegBankSelect] Reuse RegisterBankInfo logic to get to the re [...] adds 33f3a04 Rename parameter I to Index for WriteCombinedGlobalValueSumma [...] adds 12c70ed [TargetRegisterInfo] Introduce a helper class, BitMaskClassIt [...] adds ca35826 Const correctness for BranchProbabilityInfo (NFC) adds 83d385d [RegisterBankInfo] Refactor the code to use BitMaskClassIterator. adds 4bb9de3 [TargetRegisterInfo] Refactor the code to use BitMaskClassIterator. adds 15fb12b [RegisterBankInfo] Introduce getRegBankFromConstraints as an [...] adds cea5230 [RegisterBankInfo] Add a way to record what register bank cov [...] adds 90905a0 [RegisterBankInfo] Strengthen getInstrMappingImpl. adds a7f5efb llvm-dwarfdump: Use deque rather than vector to preserve obje [...] adds 0751f7f [RegisterBankInfo] Change the semantic of recordRegBankForType. adds 05e517f [RegisterBankInfo] Escap @ in r265741. [-Wdocumentation] adds a64b049 [AArch64] Fix a typo in the register class to register bank mapping. adds 818c860 [MachineInstr] Teach the print method about RegisterBank. adds b80cd97 [RegisterBankInfo] Add print and dump method to the ValueMapp [...] adds 437de15 [RegisterBankInfo] Add print and dump method to the Instructi [...] adds 2a2fe8f [RegBankSelect] Add a few debug statements. adds a63892d [IR/Verifier] Fix (yet another) crash. adds 2fcbcea Fix formatting and wording of llvm-ranlib error message. NFC. adds 9178a0c [RegisterBankInfo] Make the debug output more compact. adds 0967580 Revert "[TargetRegisterInfo] Refactor the code to use BitMask [...] adds 698c0a7 ValueMapper: Treat LocalAsMetadata more like function-local Values adds 11a3cfb DwarfDebug: Support floating point constants in location lists. adds 86c8abf ValueMapper: Unduplicate RF_NoModuleLevelChanges check, NFC adds c9e3e3c Don't IPO over functions that can be de-refined adds 2e5f81f [TargetRegisterInfo] Fix BitMaskClassIterator::moveToNextID i [...] adds 6831b38 [TargetRegisterInfo] Re-apply r265734. adds 50c7f32 Revert "ValueMapper: Treat LocalAsMetadata more like function [...] adds 41e362d Reapply "ValueMapper: Treat LocalAsMetadata more like functio [...] adds d21358e [AMDGPU] Add some VI disassembler tests missing from previous [...] adds b34a81f [IFUNC] Fix ifunc-asm.ll test adds b033fbe Use std::fill to simplify some code. NFC adds bd8d19a [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* [...] adds 9640ae7 [llvm-c] Expose LLVMContextGetDiagnostic{Handler,Context} adds 72ffd54 [mips] Use range-based for loops. NFC. adds eb92f5a CXX_FAST_TLS calling convention: performance improvement for PPC64 adds 6166d4c [X86] Tidied up shuffle decode function doxygen descriptions adds d8cc816 Re-commit [SCEV] Introduce a guarded backedge taken count and [...] adds 1f3dc22 [X86][SSE] Added 32-bit tests for vector lzcnt/tzcnt tests adds d8b70fb Revert r265547 "Recommit r265309 after fixed an invalid memor [...] adds 13757e5 [ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection adds b246969 [MIR] Teach the mir printer how to print the register bank. adds 7500ba0 [MachineVerifier] Teach how to check some of the properties o [...] adds 951ea8b [LoopVectorize] Register cloned assumptions adds 479e694 [InstCombine] Add a peephole for redundant assumes adds 3dc8933 [MIR] Teach the parser how to deal with register banks. adds 6128bae Fix missing include on OpenBSD adds 0874850 [RegBankSelect] Improve debug output. adds 2e91216 [InstCombine] Fix miscompile in FoldSPFofSPF adds c5fadc3 [RegisterBankInfo] Change the implementation for the default [...] adds 4a83779 [AArch64] Add a test case for the default mapping of RegBankSelect. adds 30e9942 [RegBankSelect] Use reverse post order traversal. adds 0b5334d [SystemZ] Support conditional sibling calls via BRCL adds 62e3955 [Object] Report an error if .alt_entry is used with ELF or COFF. adds c49723b [llvm-objdump] Printing hex instead of dec by default adds df06a07 Revert r265817 adds 8731336 Propagate Undef in llvm.cos Intrinsic adds ae29a03 ValueMapper: Stop memoizing MDStrings adds 8136165 ValueMapper: Don't memoize metadata when RF_NoModuleLevelChanges adds 9920608 [X86] Fix PR23155 by turning on X86FixupBWInsts by default. D [...] adds 6900b64 Linker: Always pass RF_IgnoreMissingLocals; NFC adds 6ead166 ValueMapper: Roll RemapInstruction into Mapper, NFC adds 16395b1 ValueMapper: Always use Mapper::mapValue from remapInstruction, NFCI adds 287cd84 ValueMapper: Extract llvm::RemapFunction from IRMover.cpp, NFC adds 53a6bdc Fix Load Control Dependence in MemCpy Generation adds 23084e8 Add trailing colons to labels in a test. adds f9a07e7 test commit adds d419844 [x86] regenerate checks for BMI tests adds 31fe4c9 Codegen: Factor tail duplication into a utility class. NFC adds 7752b4e Remove some redundant variables from X86TargetLowering::Lower [...] adds 5451c70 Rangeify a loop. NFC. adds c2571ee [x86] show missed opportunities to use andn adds 1a7750e [SSP] Remove llvm.stackprotectorcheck. adds 8a0abe7 Refactor Threshold computation. NFC. adds 7f8082c fix documentation comments; NFC adds 48bb8b4 Support the Nodebug emission kind for DICompileUnits. adds 908d3d5 [CMake] Make llvm_ExternalProject always call the build action adds 5bb9d06 [libfuzzer] defensive assert adds 5ff00d9 Maintain calling convention when inling calls to llvm.deoptimize adds 799c5e4 [X86] Remove calls to setOperationAction that set CTLZ_ZERO_U [...] adds a70c9d2 [X86] Use for loops over types to reduce code for setting up [...] adds c710179 [X86][XOP] Support for VPPERM 2-input shuffle mask decoding adds b58a4e2 [x86] use BMI 'andn' for logic + compare ops adds 030f43a Drop debug info for DISubprograms that are not referenced by [...] adds 0b0b58f is_integral_or_enum ❥ enum class ⇒ hashable enum class adds d28179e Fix hash_integer_value adds 7c0a10f [MC] support TLSDESC and TLSCALL / GNU2 tls dialect adds c15a907 [CodeGen] Don't assume that fixed stack objects are aligned i [...] adds 72c4075 Clean up test case adds 6aa584f [PGO] Fix deserialize bug adds 5cc3ce7 Fix asan test failure adds efe8e44 [X86] Remove unnecessary setOperationAction for SRA v2i64/v4i [...] adds e6319e7 [X86] Use for loops over types to reduce code for setting up [...] adds 8280149 [OCaml] Expose the LLVM diagnostic handler adds 4470d9b [X86][AVX512] Regenerated mask op tests adds a6346264 [ThinLTO] Remove unused parameter (NFC) adds 9f62954 Loop vectorization with uniform load adds 51c5e3d [X86][AVX512BW] Add support for v64i8 multiplies adds aef113a [X86][AVX512] Add vector integer division by constant tests adds 2187597 Plumb the option to emit the `ModuleHash` in the bitcode thro [...] adds 97ad447 [SCEV] See through op.with.overflow intrinsics adds 0a4c402 [IndVars] Eliminate op.with.overflow when possible adds 26a9873 [X86] Restrict max long nop length for Lakemont. adds 6e01efb [X86] Added widening tests for and/xor/or bit operations adds 46e6ec4 [X86] Regenerated sdglue test checks adds c1307b1 [X86] Added extra widening tests for and/xor/or bit operations adds 942c2d3 [X86] Added extra widening tests for and/xor/or bit operations adds 65ca168 [SystemZ] Remove incorrect CC use for C*BReturn instructions adds 8b66c0a [SystemZ] Support conditional indirect sibling calls via BCR adds db3389c [ARM] Avoid switching ARM/Thumb mode on .arch/.cpu directive adds 7ca333b [ThinLTO] Move summary computation from BitcodeWriter to new pass adds 4901036 [SystemZ] Add SVC instruction adds db55668 [SystemZ] README: remove an implemented idea, add some new ones adds c456a36 [ThinLTO] BitcodeWriter still requires Analysis library adds 0e3df21 [InstCombine] replace test that no longer works as intended adds e085c90 [mips] Trivial corrections to range checked immediates. adds d2c18d6 [mips] Make Static a default relocation model for MIPS codegen adds 5e07ce6 This reverts commit r265913 and r265912 adds 98198fc [InstCombine] add helper function for shift-shift optimizatio [...] adds 08abc19 More upgrading of old- and very-old-style debug info in testcases. adds 5d2dd71 [InstCombine] rename variables in shifted-shift helper functi [...] adds 94eb1d9 TargetRegisterInfo: Add getRegAsmName() adds 5740d62 [InstCombine] don't try to shift an illegal amount (PR26760) adds a265a6e Update discriminator testcases to use proper NoDebug CUs inst [...] adds 96f2e57 Make the distinct DISubprogram in this testcase really distinct. adds 09a3a21 [InstCombine] use canEvaluateShiftedShift() to handle the lsh [...] adds 6a7ae27 Add code comment/NFC adds 14dddbf [llvm-readobj] Add ELF hash histogram printing adds 38d4f53 variable names start with a capital letter; NFC adds c19ec77 add an assert for safety; NFC adds a05380c add FIXME comment; NFC adds 67e7463 Combine redundant stack realignment booleans in MachineFrameInfo adds 41e5af8 Use member initializers for all scalar fields of MachineFrame [...] adds 013403c [InstCombine] consolidate tests for related bugs adds 5362126 Fix missing DICompileUnits in testcases adds 90ae214 [Object] Make .alt_entry directive parsing MachO specific. adds 0fd07ef Test commit. adds e09329d [DebugInfo] Fix even more tests to include DICompileunit. adds 09e9ded [LoopUtils, LV] Fix PR27246 (first-order recurrences) adds 77e5760 MCParser: diagnose missing directional labels more clearly. adds f3fc3d1 use range-loops; NFCI adds 683020d Fix a couple of redundant conditional expressions (PR27283, PR28282) adds f721b99 Remove redundant .c_str(), as suggested by PR25633 adds 9884687 Fix broken assert, PR24624 adds ea91af8 Fix repeated conditional expression (PR20711) adds 62063a8 Revert "AMDGPU/SI: Do not generate s_waitcnt after ds_permute [...] adds 21c1304 Fix some display bugs in llvm-pdbdump. adds 29b4ba0 Add missing DICompileUnit to this testcase adds 2f1dacc Revert accidentally committed change adds b99afeb Swift Calling Convention: swifterror target support. adds 1f4a500 [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bit [...] adds d63fcee [DebugInfo/Test] Add CU as required. adds 53d36f5 swifterror: fix up a testing case. adds 36720c5 Add __atomic_* lowering to AtomicExpandPass. adds 47cbd52 ARM: use r7 as the frame-pointer on all MachO targets. adds 00cd59a [safestack] Add canary to unsafe stack frames adds eb5d561 NFC: keep comment up to date adds b4aa9bf CodeGen: Fix a use-after-free in TailDuplication adds 076e8df Fix compile with GCC after r266002 (Add __atomic_* lowering t [...] adds 382ee0e AtomicExpandPass: mark assert variable as used adds f53db33 Legalize the debug info in this testcase in anticipation of f [...] adds 18a65be ThinLTO renaming: use module hash instead of position in the summary adds 5ed848e Add a missing DICompileUnit to testcase. adds 40e099b Replace MachineRegisterInfo::TracksLiveness with a MachineFun [...] adds bf9de3a [AArch64] Test that RegBankSelect inserts the proper copies t [...] adds 9701ed8 MergeFunctions: test alloca better adds 4307705 [MachineIRBuilder] Expose the insertion point in the public API. adds be78bfb [RegBankSelect] Teach how to repair definitions. adds 73ec6f7 [AArch64] Add a test case for the repairing of definitions. adds edae2f1 [RegisterBankInfo] Do not provide a default mapping for non-r [...] adds 08f81ce [AArch64] Add a test case for the propagation of register ban [...] adds 1a11591 [RegBankSelect] Teach the repairing code how to handle physic [...] adds c13dfaa [AArch64] Add test cases for the repairing of physical registers. adds 274105b Add the allocsize attribute to LLVM. adds 9aead67 Attempt to make buildbot happier with r266032. adds 07f075c AArch64: Drive-by cleanup adds b78b825 TargetLowering: Add missing doxygen group end. adds 3cc0d8f [PPC64] Use mfocrf in prologue when we only need to save 1 no [...] adds 18569e8 [PPC64] Mark CR0 Live if PPCInstrInfo::optimizeCompareInstr C [...] adds dcd4d74 Minor code cleanup. NFC. adds 861c3f6 Use StringSet instead of StringMap where it makes sense to in [...] adds a6f1831 Refactor the Internalize stage of libLTO in a separate file (NFC) adds 03c9cc7 Avoid GCC -fpermissive error about llvm::Mangler hidden by me [...] adds b3bccda [mips] MIPSR6 Compact branch aliases adds ef1a3d2 [SystemZ] Use LDE32 instead of LE, when Offset is small. adds 2b9d31a Revert "[mips] MIPSR6 Compact branch aliases" adds 586f018 This reverts commit r266002, r266011 and r266016. adds 9040cf9 [X86] Regenerated avx512 calling convention test checks adds b26a693 AMDGPU: Add volatile to test loads and stores adds 9bb64b9 AMDGPU: Remove trailing whitespace adds bc0aee5 AMDGPU: Add atomic_inc + atomic_dec intrinsics adds d8f221e AMDGPU: Implement i64 global atomics adds e6c6eef LangRef: Update example syntax for atomic load instruction adds e331509 Moving llvm-test-depends and test-depends into the Tests fold [...] adds 7655423 [mips] add assembler support for .set arch=octeon adds a58cdd3 Test commit, NFC. adds 3c28f60 [ScheduleDAGInstrs] Handle instructions with multiple MMOs adds fc57f09 [Bitcode] Fix + regenerate old test so that it includes a DIC [...] adds 80ce670 Support arbitrary addrspace pointers in masked load/store intrinsics adds 4bd7005 AMDGPU/SI: Fix a mis-compilation of multi-level breaks adds 7fa1223 fix indentation; NFC adds 0802f71 Introduce an GCRelocateInst class [NFC] adds 5e99fa6 Check alloca's special state adds fa51c2f [CodeGen] Remove constant-folding dead code. NFC. adds 1dca546 APInt: Add overload of isMask adds 361311d [IR/Verifier] Each DISubprogram with isDefinition: true must [...] adds 87f6133 AMDGPU: Eliminate half of i64 or if one operand is zero_exten [...] adds cb6c943 AMDGPU/SI: Insert wait states required after v_readfirstlane on SI adds 4734513 Delete mergefunctions.clang.svn.patch adds 83c1c10 [WebAssembly] Fix debug info in reg-stackify.ll test adds 238d819 Add __atomic_* lowering to AtomicExpandPass. adds 991afcd NFC: MergeFunctions update more comments adds a439f48 [ThinLTO] Only compute imports for current module in Function [...] adds 756309c AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics adds 7d33ff0 NFC: MergeFunctions return early adds f704722 X86: Avoid accessing SDValues after they've been RAUW'd adds e58bfc9 Move summary creation out of llvm-as into opt adds 28b3311 Add a pass to name anonymous/nameless function adds e6f98f0 [DebugInfo] Add error message to test. adds dc03eb6 Fixed a few typos and formatting problems. NFCI. adds 23d0579 [MC/ELFObjectWriter] Fix indentation of class body. adds 69f961c Update psabi link for x86-64. Add link to linux gabi supplement. adds 2a29a67 Pre-fill LibcallRoutineNames with nullptr. adds 899eb5f [AArch64] Fuse AES{D,E}/AESMC for Exynos M1. (NFC) adds 9078f55 [x86, InstCombine] fix masked load pass-through operand to be [...] adds 8f400cc Add space between words in verify-scev-maps option help message adds ae7cc5f CodeGen: Clear the MFI's save and restore point after PrologE [...] adds 5f8681a Fix mismatch on returned type between header and implementati [...] adds 90d8769 AMDGPU/SI: Fix spilling of 96-bit registers adds 323ca5c LTOInternalize: Fix member type, should be a reference and no [...] adds d5a8ffb AMDGPU: Remove leftover ShaderType attributes in tests adds f294b09 AMDGPU: Add test for m0 initialization in basic loop adds f4dc383 Fix FunctionImport export list computation: need to take a re [...] adds 815b02e Recommit r265547, and r265610,r265639,r265657 on top of it, p [...] adds a98cfea Refactor Internalization pass to use as a callback instead of [...] adds 8fbafc9 Refactor the InternalizePass into a helper class, and expose [...] adds 42ab0ff Modernize Internalizer with for-range loop (NFC) adds f81e2fb Really return whether Internalize did change the Module or not. adds d9b590e Move "ExternalSymbols" out of LTOInternalize (NFC) adds fd6b04c [mips][microMIPS] Fix for "Cannot copy registers" assertion D [...] adds 63809dd LTOInternalize: Use a StringSet instead of a sorted vector an [...] adds 06bf569 Minor cleanup in Internalize, hide helper class using anonymo [...] adds 31ce1f6 Simplify LTOInternalize into UpdateLLVMCompilerUsed adds 1559762 [InstCombine] We folded an fcmp to an i1 instead of a vector of i1 adds 2cc36cb [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MOD [...] adds 2908602 Don't use misc-unused-parameters check on LLVM. adds 5654752 Added missing autogeneration note adds 396d592 Calculate __builtin_object_size when pointer depends on a condition adds 11615f4 [X86][SSE] Regenerated vector integer absolute tests adds 3592381 Simplify strlen to a subtraction for certain cases. adds 21bbc49 [mips] Sign-extend i32 values truncated from previously zero- [...] adds d61f2a5 [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointer [...] adds 075abcb [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..1 [...] adds 31cadd7 AArch64: don't create instructions that write to xzr/wzr twice. adds 7739723 Revert inadvertently modified comment in r266131 adds e618ec9 Make aliases explicit in the summary adds 387bdb4 Revert "Make aliases explicit in the summary" adds bd3bdfc Sanity check `opt` options compatibility: can't have module-s [...] adds 100a6be Cleanup Store Merging in UseAA case adds c7e68af [IR/DebugInfoMetadata] Simplify array length calculation by u [...] adds 4a1c79f Revert "[IR/Verifier] Each DISubprogram with isDefinition: tr [...] adds 891346a [AArch64] Disable LDP/STP for quads adds 7b4c09a llvm-dwp: Add assert text adds b935913 [PowerPC] Basic support for P9 byte comparison and count trai [...] adds 5a486ec [PGO] Remove redundant VP instrumentation adds 9e81c60 LibDriver: Silently do nothing when provided no inputs. adds f001eb5 Test case for r265852. adds 6d56779 AsmParser: record "# line file" context to calculate location [...] adds 0149731 [DebugInfo] Optimize memory layout of DISubprogram. adds f301f27 [x86] add tests to show potential BMI optimization adds a092aac AMDGPU/SI: Add support for spilling VGPRs without having to s [...] adds 92d32ce NFC mergefunc: const correctness adds 6324751 Start to add real error messages for malformed Mach-O files. [...] adds f9ce506 Return immediately from analyzeCall if analyzeBlock returns false. adds f8df4a0 [llvm-lto] clang-format before working on this file. adds 9f620df AArch64: Use a callee save registers for swiftself parameters adds cd45ee9 X86: Use a callee save register for the swiftself parameter. adds 3df4c84 ARM: Use a callee save register for the swiftself parameter. adds a6ab261 [llvm-lto] Uniform error handling. NFC. adds 55e47a6 [IR] Optimize memory usage of Metadata on MSVC adds 2af3e8f Add LLVMGetAttrKindIDInContext in the C API in order to facil [...] adds 4cd20e7e ValueMapper: Resolve cycles on the new nodes adds 609cf3b Revert "Add LLVMGetAttrKindIDInContext in the C API in order [...] adds 5a4800a ARM: override cost function to re-enable ConstantHoisting (& [...] adds 788bace [ppc] add tests to show potential andc optimization adds ea89695 [CFLAA] Fix up code style a bit. NFC. adds f8b5f15 TargetLowering: Factor out common code for tail call eligibil [...] adds f5cccc3 AMDGPU: Implement canonicalize adds c1f6e31 Do not use getGlobalContext()... ever. adds 1f0cfcc [CodeGen] Teach LLVM how to lower @llvm.{min,max}num to {MIN,MAX}NAN adds d7e55dc ThinLTO: linkonce compile-time optimization, do not bother wh [...] adds cf0a711 Revert "Support arbitrary addrspace pointers in masked load/s [...] adds 78732b7 [Coverage] Avoid unnecessary copying of std::vector adds d83fa0e [mips] Remove duplicate tests and add missing prefixes for *- [...] adds 77eb420 [Coverage] Update testing methods to support more than two files adds 51d2103 Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0 [...] adds 5cb657f [SCEV][LAA] Add tests for SCEV expression transformations per [...] adds d14f0db [PGO] Do not attach VP metadata if value count at site is 0 [NFC] adds d5f7d71 AMDGPU/SI: Use the correct scratch wave offset register for shaders. adds 510a2b9 AMDGPU: allow specifying a workgroup size that needs to fit i [...] adds a3b03dc [lanai] Add areMemAccessesTriviallyDisjoint, getMemOpBaseRegI [...] adds a54275f AArch64: expand cmpxchg after regalloc at -O0. adds b4b70a0 [GlobalISel] Coding style and whitespace fixes adds 31914b9 AMDGPU: change a redundant if () to an assert(). NFC adds d073405 AMDGPU: Remove SIFixSGPRLiveRanges pass adds 44aa353 [StructurizeCFG] Annotate branches that were treated as uniform adds a16ecd43 [DivergenceAnalysis] Treat PHI with incoming undef as constant adds bd13728 [GlobalISel] Move GISelAccessor class into public headers adds 26f23b1 [lanai] Add custom lowering for SRL_PARTS i32. adds 1252a8c [ValueMapper] Range-loopify to improve readability. NFC. adds 13fb5a3 Sink DI metadata usage out of MachineInstr.h and MachineInstr [...] adds 407de62 Update discriminator assignment algorithm to handle nested ca [...] adds 65b5541 AMDGPU: Add skeleton GlobalIsel implementation adds 755d4ed Fix null pointer access for discriminator assignment. adds fc164bf [InstCombine] remove constant by inverting compare + logic (PR27105) adds a447ca5 [ARM] Adding IEEE-754 SIMD detection to loop vectorizer adds 1a49060 [ScheduleDAGInstrs] Re-factor for based on review feedback. NFC. adds 38b2257 AMDGPU: Fold bitcasts of scalar constants to vectors adds 5009212 AMDGPU: Directly emit m0 initialization with s_mov_b32 adds 6d955a1 AMDGPU: Run SIFoldOperands after PeepholeOptimizer adds 8be7707 Remove every uses of getGlobalContext() in LLVM (but the C API) adds 41b016e Nuke getGlobalContext() from LLVM (but the C API) adds f66aab6 [AliasSetTracker] Correctly handle changing the size of an entry adds 09c4262 AMDGPU: Include LDS size in printed comment adds 176a9b27 AMDGPU: Remove custom load/store scalarization adds 891e9f4 [test] Require 'asserts' for a test which uses -debug-only adds 8885fcd [LTO] Add a new splitCodeGen() API which takes a TargetMachin [...] adds 486e8bb OptionParsingTest.cpp: reorder EXPECT_EQs to put expectation [...] adds 9f34fd5 Option parser: class for consuming a joined arg in addition t [...] adds 2ef07c5 [ParallelCG] Attempt to placate MSVC. adds 41f2abf [Speculation] Add a SpeculativeExecution mode where the pass [...] adds c904368 [PM] Add a SpeculativeExecution pass for targets with diverge [...] adds b3c92d3 Move divergent-target test into CodeGen/NVPTX because it requ [...] adds ddeb008 [ifcnv] Don't duplicate blocks that contain convergent instructions. adds dbebf40 [TTI] Add getInliningThresholdMultiplier. adds 9ac6818 [NVPTX] Set NVPTXTTI::getInliningThresholdMultiplier to 5. adds 0e3b20f Revert "[LTO] Add a new splitCodeGen() API which takes a Targ [...] adds 1249dda [X86] Combine an if and else block that had the same set of c [...] adds 8d5bfc6 [X86] AND, OR, and XOR of vectors are always legal no need to [...] adds cf94389 Add a setOperationPromotedToType convenience method that sets [...] adds cc9f5cb Use MVT instead of EVT to remove a bunch of unnecessary calls [...] adds 4c4aae4 AMDGPU/SI: Fix regression with no-return atomics adds e5d4119 [Coverage] Add support for making test data for more than one [...] adds b6d5c28 [SimplifyCFG] add metadata to show failure to propagate (PR27344) adds cfdf5c2 [Coverage] Prevent detection of false instantiations in case [...] adds 232aafc [MachineScheduler]Add support for store clustering adds fb9467a Fix typing on generated LXV2DX/STXV2DX instructions adds 82ae298 [AArch64] Add MMOs to callee-save load/store instructions. adds ee837d0 lli.cpp: Appease some builders. There might be ownership issu [...] adds 82e3cfc [SimplifyCFG] propagate branch metadata when creating select [...] adds fa0d0a5 llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll requires +Asserts. adds 4eeaa0d [PR27284] Reverse the ownership between DICompileUnit and DIS [...] adds 2593b55 Fix test to require Asserts since it uses debug output. adds a3f79ea [InstCombine] Don't transform compares of calls to functions [...] adds ce5b591 [SystemZ] Fix large tests broken by conditional returns. adds db52b36 [ParallelCG] Add a new splitCodeGen() API which takes a Targe [...] adds 665e18d Revert "[Coverage] Prevent detection of false instantiations [...] adds 2867041 [AArch64] Add load/store pair instructions to getMemOpBaseReg [...] adds 1da7db0 ARM: don't try to hoist constant RHS out of a division. adds 4479a5c [codeview] Dump char16_t and char32_t simple types adds 2fee4f2 Update testcase to new debug metadata format. adds 8f148cd Let the DISubprogram in this test point to the right compile unit. adds 0f50588 [SystemZ] Call tryAddingSymbolicOperand in the disassembler adds e4eb0de [mips] Use range-based for loops and simplify slightly the co [...] adds f402ab3 [mips] More range-based for loops. NFC. adds c4caccc [libFuzzer] menion the git mirror in the docs adds b87a1e6 Replace the use of MaxFunctionCount module flag adds 3301aed SelectionDAGISel: rangeify a loop adds a82c87c Switch lowering: don't add incoming PHI values from skipped b [...] adds ac6d266 [libFuzzer] add a better warning for command line flags with [...] adds 422c22e Convert this sample-based-profiling testcase to use a NoDebug CU. adds a138550 [cfi] Support explicit sections for functions in cfi-icall. adds a4f4792 Add ProfileData to required_libraries adds 1f5a2c3 Don't skip splitSeparateComponents in eliminateDeadDefs for H [...] adds 5e3b7ae ValueMapper: Hide Mapper::VM behind an accessor, NFC adds b337fbb Make this header include the header it depends on, rather tha [...] adds fef9f1f Linker: Remove an unnecessary local variable in for loop, NFC adds d1d05a8 Add some missing #includes, found by C++ modules selfhost. adds 43ef70d Update and fix LLVM_ENABLE_MODULES: adds d83a5e8 ValueMapper: Eliminate cross-file co-recursion, NFC adds 90cac21 ValueMapper: Use API from r266503 in unit tests, NFC adds 992b34c AMDGPU: Use s_addk_i32 / s_mulk_i32 adds 86a7a5a Revert "ValueMapper: Eliminate cross-file co-recursion, NFC" adds d245507 AMDGPU: Enable LocalStackSlotAllocation pass adds b5fd6b3 [DebugInfo] Reduce size of DILocalVariable from 40 to 32 bytes. adds 1f03619 Reapply "ValueMapper: Eliminate cross-file co-recursion, NFC" adds 30f743e [DebugInfo] Correct the assertion introduced in r266509 + upd [...] adds 0b11282 ValueMapper: Stop memoizing ConstantAsMetadata adds d7628da Do not modify a cl::opt programmatically, global mutable stat [...] adds b677706 Replace hardcoded comment at 'lit.site.cfg.in' adds eb79e6e ThinLTO: Make aliases explicit in the summary adds 29d66c4 ThinLTO: Move the ODR resolution to be based purely on the summary. adds 3ab0c4f Add SVN version to libLLVMLTO adds 492acdd Remove some unneeded headers and replace some headers with fo [...] adds db4fbb6 ValueMapper: Fix unused var warning. NFC adds 66fb8aa [X86][XOP] More VPPERM shuffle mask decode tests adds bf62fd9 Add missing #include to fix build adds 0ba66e5 [X86][XOP] Added VPPERM constant mask decoding and target shu [...] adds 3333cc9 [X86] Use ternary operator to reduce code slightly. NFC adds 3083694 [X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP adds 5b389c0 ValueMapper: Only put cyclic nodes into CyclicNodes, NFCI adds fcbd2d6 ValueMapper: Separate mapping of distinct and uniqued nodes (again) adds 9c9a101 LTO: Use a common LibLTOCodeGenerator::init, NFC adds d25d6b7 IR: Remove extra blank line, NFC adds 2c71d39 LangRef: Fix some bugs in debug info descriptions adds 3126dd7 use range loop, try to make comments more meaningful; NFCI adds 44387cf IR: Add a configuration point for MDNodeInfo::isEqual, NFC adds 36d852b Linker: Clarify test/Linker/type-unique-odr-a.ll, NFC adds 4460c98 LangRef: Removed some outdated text about DIDerivedType adds bf8d6bc [Target] Fix an assertion that should have been updated when [...] adds 664e2c8 [Target] Remove checks for Simple VTs before calling routines [...] adds 9e15d9a [Target] Reduce size of the LoadExtActions array in TargetLow [...] adds 12a8b14 IR: Use ODR to unique DICompositeType members adds 9bb5d5d IR: Use an explicit map for debug info type uniquing adds 499c2d4 Revert "use range loop, try to make comments more meaningful; NFCI" adds 0fd5dc0 Fix a typo in rL265762 adds 2b7fe3c IR: Use getRawScope() when verifying adds d9827ce IR: Fix type-refs in testcase from r266548 adds 6b892ee [AVX512] ISD::MUL v2i64/v4i64 should only be legal if DQI and [...] adds 74bdb66 [X86] Remove unneeded variables adds 68566f9 [X86] Added TODO comment for target shuffle mask decoding of [...] adds 2cd2d0a [X86][SSE] Added 16i8 -> 8i64 sext test adds ca89139 Declare MVT::SimpleValueType as an int8_t sized enum. This re [...] adds 3a804b2 IRMover: Remove dead code, NFC adds ec86ae2 Keep only the splitCodegen version that takes a factory. adds f1f1181 ValueMapper: Don't allow explicit null mappings of Values, NFC adds 3aba53b Fix a use after move. adds 60d75fe Transforms: Fix bootstrap after r266565 adds 8bef6e2 [ParallelCG] SmallVector<char> -> SmallString. adds 31d315e Linker: Don't double-schedule appending variables adds 6b8e359 Transforms: Try harder to fix bootstrap after r266565 adds ab6ed64 When building with LLVM_ENABLE_MODULES, put the module cache [...] adds 537951f NFC: unify clang / LLVM atomic ordering adds d6634d6 Revert "NFC: unify clang / LLVM atomic ordering" adds 6a6cda1 [X86] Be explicit about calls to setOperationAction for AVX2 [...] adds 034f0ee Linker: Share a single Metadata map for the lifetime of IRMover adds bd1968a [ORC] Generalize the ORC RPC utils to support RPC function re [...] adds 35f771e BitcodeWriter: WorkList => Worklist, NFC adds 8149973 [Orc] Tweak some of the new RPC code to silence a warning (ex [...] adds f6071e1 [NFC] Header cleanup adds 895fbaa [PowerPC] add comment to test adds b144c8f [mips][ias] Stream macro expansions to output instead of buff [...] adds d30dbb6 [ARM] AArch32 v8 NEON is still not IEEE-754 compliant adds e87a43e Include SmallVector.h header in lib/Target/WebAssembly/InstPr [...] adds 9251559 [mips][ias] Prevent double-filling of delay slots by generati [...] adds a3a95e8 Unbreak building llvm-pdbdump on Windows after r266595. adds 2e7ff2c Unbreak building LLVMTarget on Windows after r266595. adds 5504404 Unbreak building unit tests on Windows after r266595. adds 1806169 Revert 266581 (and follow-up 266588), it doesn't build on Windows. adds 4ebefaf Silence some "initialized but unused" warnings from MSVC -- t [...] adds ae5612e [AMDGPU][llvm-mc] s_setreg* - Fix order of operands adds dcefe31 Revert "Replace the use of MaxFunctionCount module flag" adds 66a92f3 Reapply "[Coverage] Prevent detection of false instantiations [...] adds 6f9e8d8 [X86][AVX] Renamed vperm2f128 tests to make it quicker to review adds 7d71f38 [X86][AVX] Renamed vperm2f128 test to make it quicker to review adds 5d42fba [AMDGPU] Add insert nops pass based on subtarget features ins [...] adds c6f7492 Lanai: fix debug build adds e9b1c6e Revert r266488. adds ed7bef5 [X86][AVX] Added zero+blend vs vperm2f128 optsize tests cases [...] adds 6be977a Port InstrProfiling pass to the new pass manager adds cc76a0c Add missing new file for r266637 adds 1b711b2 NFC: unify clang / LLVM atomic ordering adds d8fa185 [libFuzzer] add fresh openssl trophies adds 14e4008 lli: avoid global variables, use a local unique_ptr instead adds 7f8cd41 [BPI] Consider deoptimize calls as "unreachable" adds 31068d5 Fix shared build of LLVMPasses. adds 093fece [ValueTracking] Correct lit test comments. NFC. adds dc8be91 try to make comments more meaningful; NFC adds 9fac7e29 [X86][AVX] Added extra memory folding tests for D19228 adds 6320b78 [Orc] Re-commit r266581 with fixes for MSVC, and format cleanups. adds a6af357 [Orc] Explicitly delete RPC::SequenceNumberManager's copy-con [...] adds 0162d62 [X86][SSE] Test case for PR2585 adds 37e715d [libFuzzer] warn if the corpus is empty adds 97c0826 ARM: use a pseudo-instruction for cmpxchg at -O0. adds a2ea8f5 CachePruning: fix typo, we accumulate file size here, not time adds 0224d5c Add debugging to the cache pruning adds 4917541 Remove old DIBuilder::createFunction overload used only by dr [...] adds 2bb2fc9 [DWARF] Force a linkage_name on an inlined subprogram's abstr [...] adds d3f038d [libFuzzer] try to print correct time in seconds when reporti [...] adds d5d6cc9 Add missing header, found by modules selfhost. adds 19c0ba5 Add missing #include, found by modules selfhost. adds 3445cc7 Port DemandedBits to the new pass manager. adds c3a95b9 Increase SmallVector size for ConstantUniqueMap::getHashValue [...] adds 1fe6695 [lanai] Set boolean contentss to ZeroOrOneBooleanContent. adds decc22f vim: add swiftcc keyword adds 1372f53 BitcodeWriter: Break recursion when enumerating Metadata, almost NFC adds ffdeef4 [Orc] Tidy up some of the RPC primitives, add a unit-test for [...] adds 4576e07 [ORC] Whitespace. adds 2663f35 IR: Rename API for enabling ODR uniquing of DITypes, NFC adds 1513285 Introduce a "patchable-function" function attribute adds 3bf6fb9 [Orc] Disable RPC callST unit test until the S390 failures en [...] adds 4c8f9b3 Correct IDF calculator for ReverseIDF adds 07f6d80 Disable the PatchableFunction pass for NVPTX & Wasm adds a1ff4a6 Add a description for the PatchableFunction pass; NFC adds 82f54f8 Minor improvement to debug output for Function Importer (NFC) adds 580e952 [X86][AVX2] Prefer VPERMQ/VPERMPD over VINSERTI128/VINSERTF12 [...] adds 153162f [InstCombine][X86] Regenerate SSE combine tests as part of se [...] adds ee5f5d9 [InstCombine][X86] Added extra tests introduced for D17490 adds ef55fa5 IR: Require DICompositeType for ODR uniquing type map adds 511eb03 IR: getOrInsertODRUniquedType => DICompositeType::getODRType, NFC adds 9507885 Enable ODR uniquing of DITypes in more places adds 75cc051 IR: Use Optional instead of unique_ptr for debug info ODR typ [...] adds 5c025fc ModuleLinker: Do not import linkonce/weak as "external_weak" adds 64d3314 IR: Use Optional instead of unique_ptr for Metadata map in Va [...] adds 12cc10f Fix Gold test after r266750 (ModuleLinker: Do not import link [...] adds 4455a13 [DependenceAnalysis] Refactor uses of getConstantPart. NFC. adds 001edd0 Linker: Avoid constructing ValueMap::MDMapT adds d72293f IR: LLVMContextTest => DebugTypeODRUniquingTest, NFC adds 18d3f58 [Orc] Add pthread dependence to the RPCUtilsTest unit test. adds 2974be9 [ValueTracking] Improve isImpliedCondition for conditions wit [...] adds 80e5a57 [Orc] Add move ops to RPC to satisfy MSVC. adds 67622ea [llvm-pdbdump] Print a better error message when PDB loading fails. adds 8fe60de Linker: Simplify test/Linker/dicompositetype-unique.ll, NFC adds 46f6a88 Preliminary changes for fixing PR27241. Generalized/restructu [...] adds d33fbe4 IR: Enable debug info type ODR uniquing for forward decls adds 1c960f5 [Hexagon] Implement branch relaxation adds ffd20497 [X86MCInstLower] Clean up EmitNops; NFC adds 13e21eb [X86] Simplify StackMapShadowTracker; NFC adds 7f0d15f [ValueTracking, VectorUtils] Refactor getIntrinsicIDForCall adds 5ea3f52 [lanai] Add lowering for SETCCE i32. adds 1f32c5f [Orc] Fix missing return in RPC move assignment operator. adds 3993a48 [Orc] Add explicit move ops to OrcRemoteTargetRPCAPI for MSVC. adds e7221e6 [SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to [...] adds ac94d4b [PPC, SSP] Support PowerPC Linux stack protection. adds 2d71534 [Hexagon] Fix printing the address operand of S2_storerinewabs adds 11f1b93 [Orc] Add move ops for OrcRemoteTargetClient and OrcRemoteTar [...] adds 9ebfa4d [AArch64] [ARM] Make a target-independent llvm.thread.pointer [...] adds 414bb96 [Hexagon] Fix operand swapping in HexagonPeephole adds 4db32f4 Remove duplicated header contents, NFC adds 39980d6 [TableGen] Make an error message slightly more informative adds 4b52862 AMDGPU/SI: SGPR accounting in getSIProgramInfo must ignore ex [...] adds fea41fb AMDGPU: Guard VOPC instructions against incorrect commute adds 318d6a2 Add IntrWrite[Arg]Mem intrinsic property adds 8dffe5b ARM: fix assertion failure on -O0 cmpxchg. adds 50620d6 [libFuzzer] more trophies adds d780712 [Mips] [MSan] VarArgMIPS64Helper: Use target's endian, not host's. adds 2599294 [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. adds 995d863 IR: Use std::vector instead of SmallPtrSet for distinct nodes, NFC adds 7ecb582 ScoreboardHazardRecognizer: unbreak TSAN by moving a static m [...] adds a0a13e0 [libFuzzer] added -detect_leaks flag (0 by default for now). [...] adds 11034da IR: Use HANDLE_METADATA_LEAF to define MetadataKind enum, NFC adds 2c43473 MipsAsmParser::loadImmediate(): Prune an obsolete \param in r [...] adds 7b1322c Add LLVMGetAttrKindID in the C API in order to facilitate mig [...] adds ac5701a [SystemZ] Add support for llvm.thread.pointer intrinsic. adds 50c1579 ThinLTO: Move alias importing decision on the summary adds 63d7d49 llvm-lto: run the module verifier when doing IR level work adds b2027b2 [X86] Don't set vector FADD,FSUB,FMUL,FDIV,FNEG,FSQRT to Expa [...] adds f3e0fc9 [X86] Merge the two different SSE2 blocks in the X86TargetLow [...] adds 218b284 [X86] Don't mark vector loads and shifts Expand in advance. L [...] adds 5d50032 [X86] Mark some floating point operations that are always exp [...] adds 7e57deb FunctionImport: make sure we always select the right callee i [...] adds 83dc7b6 ThinLTO: never promote as external weak adds f3303c9 [AVX512] Add popcount support for v32i16 and v64i8. adds f60b9d3 [AVX512] Update vector-tzcnt-512 test to show how bad v32i16 [...] adds 6990d61 [AVX512] Add avx512cd+vl runs to vector-tzcnt-128/256 tests t [...] adds 6ae2468 [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions D [...] adds ec050f4 [X86] enable PIE for functions adds 53fd688 AMDGPU/SI: Assembler: improvements to support trap handlers. adds 2dca566 [gold-plugin] Disable name for values other than GlobalValue adds 12607ab Revert "[gold-plugin] Disable name for values other than Glob [...] adds c5d3b5c [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC an [...] adds dc458b4 [RDF] Consider register as live if any alias is live adds 89c5c63 [ThinLTO] Prevent importing of "llvm.used" values adds b1010ed Re-enable "[gold-plugin] Disable name for values other than G [...] adds 4a0bd4e [Hexagon] Fix handling of lcomm directive adds 692062d IR: Use default member initialization in Verifier, NFC adds 6e87fc1 IR: Don't use raw_null_ostream in Verifier adds 4ca56a6 IR: Use a single ModuleSlotTracker in the Verifier adds 9887f4e ModuleLinker: only import what is in GlobalsToImport, regarle [...] adds e2fbd0e LTO: Verify the input even if optimize() isn't called adds 1fa5ffc [MC] EmitNop: Make an assertion more useful. adds 8f2afa6 Verifier: Prefer early continue over if-nesting, NFC adds f38ea34 [lanai] Add subword scheduling itineraries. adds 68a7a2f Verifier: Add ModuleSlotTracker to printAsOperand call adds 19c2c53 [MC] Silence warning due to unused variable in !Debug builds. adds 1487a2e IR: Avoid mallocs in constructor of ModuleSlotTracker adds d5de81e Replace a loop with a for-each loop. No behavior change. adds dd01bef [ValueTracking] Make isImpliedCondition return an Optional<bo [...] adds 3421c1b Typo. adds 923c75e Rename asan-check-lifetime into asan-stack-use-after-scope adds 7c73f3f IR: Stop copying vectors of TrackingMDRef in DIBuilder adds b398943 IR: Use SmallVector instead of std::vector of TrackingMDRef adds de21c29 [Hexagon] Add -mv.. options to override CPU selection adds 813e0cf Thread Expected<...> up from libObject’s getName() for symbol [...] adds d7f2f9e [test/PGOProfile] Make tests independent of the raw profile v [...] adds 9de3901 Fix compilation error in r266919. adds 288715b Fix another compilation error from r266919 for clang-atom-d52 [...] adds faa949c Refine instruction weight annotation algorithm for sample profiler. adds 32ea396 Add optimization for 'icmp slt (or A, B), A' and some related [...] adds d396215 MachineSched: Cleanup; NFC adds e33a1a5 BitcodeWriter: Emit metadata in post-order (again) adds 0e60374 ThinLTO/ModuleLinker: add a flag to not always pull-in linkon [...] adds bb1a6fc ValueMapper: Map uniqued nodes in post-order adds 0562d50 [AVX512] Add support for popcount of v8i64 and v16i32 with an [...] adds 3655b0c [SelectionDAG] Teach LegalizeVectorOps to directly Expand CTT [...] adds fe59ac8 [X86] Remove unnecessary setting of CTTZ_ZERO_UNDEF to Custom [...] adds 84a84a1 [SimplifyCFG] Fold `llvm.guard(false)` to unreachable adds 5d79e77 ThinLTO: Resolve linkonce_odr aliases just like functions adds 19293aa ThinLTO: add module caching handling. adds 803d96c [X86] Remove old leftover MMX code that sets various 64-bit v [...] adds 28de30a [X86] Remove some operations from the default Expand all vect [...] adds ccd4d20 [X86] Remove redundant calls to setOperationAction for EXTRAC [...] adds 56e5e84 [AVX512] Add support for lowering CTTZ v64i8 and v32i16 with [...] adds 01d402f ThinLTO: initialize variables adds 2a866db CachePruning: early exit if no path supplied adds 1c6fe69 Fix test command line to explicitly disable CDI instructions [...] adds 33683f1 [X86] Fix vector-tzcnt-512 test to disable CDI while enabling [...] adds 0e2baf6 [AVX512] Add CTTZ support for v8i64 and v16i32 vectors. adds 5a1084c [AArch64][CodeGen] Fix of PR27158: incorrect peephole optimiz [...] adds 02f5473 Updated a test not to produce an empty s-file. adds b6b7c48 [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SY [...] adds d591d40 [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instr [...] adds b18e50c Add a CachedHash structure. adds 02026c0 [AMDGPU] Assembler: prevent parseDPPCtrlOps from eating inval [...] adds ddc5048 [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocation adds 88419b2 Refactor implied condition logic from ValueTracking directly [...] adds 161372b [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocation adds 42fa984 [mips][microMIPS] Implement ldpc instruction adds 8b7f416 Fix recursive -only-needed. adds dbd967b Minor comment cleanup [NFC] adds 615a6cf Address Philip's post-commit feedback for r266987. NFC. adds 6159d86 [unordered] Add tests and conservative handling in support of [...] adds 1268621 Fixed Dwarf debug info emission to skip DILexicalBlockFile en [...] adds 58cd23c [instcombine][unordered] Implement *-load forwarding for unor [...] adds 94253c1 [LoopUtils] Rename {check->find}StringMetadata{Into->For}Loop. NFC adds b4a76b3 [LoopUtils] Move def of findStringMetadataForLoop to LoopUtil [...] adds 07c1653 [LoopUtils] Add asserts to findStringMetadataForLoop. NFC adds e69bdcf [LoopUtils] Fix typo in comment adds 8ac661c [PowerPC] [SSP] Fix stack guard load for 32-bit. adds 343a611 [unordered] unordered loads from null are still unreachable adds a7af0d6 Split IntrReadArgMem into IntrReadMem and IntrArgMemOnly adds c852398 Initial implementation of optimization bisect support. adds 43a1464 [instcombine][unordered] Extend load(select) transform to han [...] adds 88c88b2 DAGCombiner: Reduce 64-bit BFE pattern to pattern on 32-bit c [...] adds 99b0ca4 [RegisterBankInfo] Change the representation of the partial m [...] adds 193934b LegalizeDAG: Move unaligned load/store expansion to TLI adds 4ec85d0 AMDGPU: Fix debug name of pass to better match adds 0e156ed [RegisterBankInfo] Change the API for the verify methods. adds c552ed7 [Hexagon] Expand handling of the small-data/bss section adds 80fd5b2 Folding compares with unescaped allocations adds 372b2d6 NFC: fix nonsensical comment adds 13eabc3 Fix crash in llvm-objdump with -macho -objc-meta-data that wa [...] adds ad7d56b [Hexagon] Properly recognize register alt names adds 8f964ad NFC: fix copy / paste comment adds 484ff8d [RuntimeDyld] Fix conservative over-allocation of memory for [...] adds 7c699fb Zero-initialize members of the CpuHashInfoTy structure for AsmParser adds c7e7d32 hange the variable name big_size to BigSize. Caught by Rafael [...] adds e4d168d [MachineBasicBlock] Refactor SplitCriticalEdge to expose a qu [...] adds ec47429 Refactor raw pdb dumper into library adds 6efffd3 Add natvis visualizers for endian types. adds d993f1c use FileCheck; add test for disguised fabs adds f2cd157 [MachineBasicBlock] Make the pass argument truly mandatory wh [...] adds bf8e161 add tests for disguised fabs/fneg adds 089f755 [ProfileData] Report errors from InstrProfSymtab::create adds 11646329 Fix a typo in an error message. Caught by Sean Silva! adds b505275 Add utility function to manipulate attributes on CallSite. NFC adds 3494767 [esan] EfficiencySanitizer instrumentation pass adds 48c9c5b Remove various warnings. NFC adds de4d323 Fixed flag description adds d192551 Fix for case sensitive filename failure. adds 9c2e16e Fix pdbdump-headers.test after guid format change. adds 46d5ec0 Fix -Wreturn-type warning with HAVE_DIA_SDK is false. adds cfbb8a7 Remove dead code. NFC adds 4913b3f Improve error message reporting for MachineFunctionProperties adds a1d19be Fix PDB warnings and test adds a0a870f [Support] Fix Wcast-qual warning adds 12098d3 Fix some -Wunused-variable warnings in non-asserts builds. adds 361618e MachO: enable .data_region directives everywhere adds 259641d Fix more -Wunused-variable in non-asserts build. adds aa72481 [sancov] using normalized filenames for blacklist checks. adds 197563e ARM: restrict register class for WIN__DBZCHK adds e0dd87a [WebAssembly] Limit alignment hints to natural alignment. adds 817fdeb ARM: fix test for Windows division adds b725c76 Try to fix UNRESOLVED: LLVM :: CodeGen/AArch64/arm64-regress- [...] adds 14eb0b5 Untabify. adds acfba51 [ThinLTO] Remove unused/incomplete lazy summary reading suppo [...] adds 7c23aa2 [MachineCombiner] Support for floating-point FMA on ARM64 adds 5ab1a4f ValueMapper/Enumerator: Clean up code in post-order traversals, NFC adds 758524f [AVX512] Teach lowering to use vplzcntd/q to implement 128/25 [...] adds 3441786 AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic adds 90c7bb0 Refactor IRObjectFile, extract a static CollectAsmUndefinedRe [...] adds 12a3bb4 Use std::move on the enum to insert it into the pair to please MSVC adds bfce19c IRObjectFile, clang-format fixup for r267104 adds 4302c2c Clean the API for CollectAsmUndefinedRefs, taking a Triple an [...] adds b23f14f [Lanai] Remove unused methods declarations. NFC adds f1102ba [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead [...] adds da09533 [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand inst [...] adds fdc9ad7 [SCEV] Extract out a `isSCEVExprNeverPoison` helper; NFCI adds 91e5e85 [EarlyCSE] Take the intersection of flags on instructions adds fd026c3 Fix some spelling mistakes adds 582e856 [GVN] Respect fast-math-flags on fcmps adds 6a025fe [mips][microMIPS] Implement DVP, EVP and JALRC.HB instruction [...] adds 8866d94 Revert "Initial implementation of optimization bisect support." adds 82da5a1 The following code would not work before this patch, due to t [...] adds 4572b68 [Sparc] This provides support for itineraries on Sparc. adds 91d7ac0 [X86]: Changing cost for “TRUNCATE v16i32 to v16i8” in SSE4.1 mode. adds c4f4f71 Revert r267098 - [MachineCombiner] Support for floating-point [...] adds 2321e60 Fix -Wunused-variable in non-asserts build. adds c1499f8 [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocation adds fed867f [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS3 [...] adds 883a09c [InstCombine] Preserve fast math flags when combining PHIs adds c42b2f3 AMDGPU/SI: Add test missed in rL266865 adds cd2984f Revert r267049, r26706[16789], r267071 - Refactor raw pdb dum [...] adds e86221b [mips] Fix a small typo that would leave BLTZC out of getAnal [...] adds 47534d9 Document source_filename in LangRef. adds ad461d6 [mips] Fix select patterns for MIPS64 adds 3211e2d Emit code16 in assembly in 16-bit mode adds a796450 [EarlyCSE] Don't add the overflow flags to the hash adds fbbc621 CodeGen: Add a stand-alone hazard recognizer pass adds 1defd69 [MemorySSA] Fix bug in CachingMemorySSAWalker::invalidateInfo adds bfad27b PostRAHazardRecocgnizer: Fix unused-private-field warning adds 58d0f74 [Hexagon] Add definitions for trap/pause instructions adds db55335 [Hexagon] Teach mux expansion how to deal with undef predicates adds 762ad97 [mips][microMIPS] Revert commit r266861. Commit r266861 was t [...] adds 1a459df [AMDGPU] Insert nop pass: take care of outstanding feedback adds 41b3dd1 [SimplifyCFG] Simplify code review by temporarily removing th [...] adds 14f36d7 [SimplifyCFG] Add missing implications to isImpliedTrueByMatc [...] adds 491fbf6 PM: Remove some redundant name() methods adds d12b345 [Hexagon] Properly close live range in HexagonBlockRanges adds d57e2db [Hexagon] Properly close live range in HexagonBlockRanges --- [...] adds c8ce43d Have isKnownNotFullPoison be smarter around control flow adds 0e44a1e Point link to CODE_OWNERS.txt to klaus instead of viewvc. adds 6d282e5 [SimplifyCFG] Add final missing implications to isImpliedTrue [...] adds 37cfc23 [Hexagon] Use common Pat classes for selecting code for intrinsics adds f9b535e test: split test into two runs adds a9389fc [AArch64][AdvSIMDScalar] Update the kill flags correctly. adds bc86912 [LoopVersioningLICM] Add test coverage for llvm.loop.licm_ver [...] adds b5898a2 [AArch64] When creating MRS instruction, make sure the destin [...] adds c6ee1a0 [EarlyCSE/CVP] Add stats for CVPs and make sure to account fo [...] adds 14c1739 MachineScheduler: Limit the size of the ready list. adds 702039b [LoopUtils] Extend findStringMetadataForLoop to return the va [...] adds bc2216c MachineScheduler: Move code to initialize a Candidate out of [...] adds 04d2814 PM: Port DCE to the new pass manager adds 950aa30 [DeadStoreElimination] Shorten beginning of memset overwritte [...] adds e6cf9dc PM: Reorder the functions used for SinkingPass. NFC adds 9d0b7e9 PM: Port SinkingPass to the new pass manager adds 57d47e7 [AArch64] Fix optimizeCondBranch logic. adds 6252915 DAGCombiner: Relax alignment restriction when changing load type adds a436337 [unordered] Extend load/store type canonicalization to handle [...] adds 5011913 CodeGen: Use PLT relocations for relative references to unnam [...] adds b0a8b9c Fold compares for distinct allocations adds 45045e9 [unordered] sink unordered stores at end of blocks adds efee6b3 [PGO] change the interface for createPGOFuncNameMetadata() adds 87d1190 DAGCombiner: Relax alignment restriction when changing store type adds 6217a62 TLI: Only iterate over integer vector types adds 74eabdd Introduce llvm.load.relative intrinsic. adds f8d640b AMDGPU: Fix crash when dumping unknown opcode adds 1e4609e Update discriminator assignment algorithm in clang assembler. adds 4fc8e6f llvm-symbolizer: prefer .dwo contents over fission-gmlt-like- [...] adds 2057e74 Differential Revision: http://reviews.llvm.org/D19040 adds 1e455c5 Re-commit optimization bisect support (r267022) without new p [...] adds 50cc811 Revert r267210, it makes clang assert (PR27490). adds 8a1d408 Removing unused function. adds dcbc34e Fix comment about Intr*Mem properties adds 9ef1010 Add some release notes about the fix for PR26774 adds 6c8569f AMDGPU: Re-visit nodes in performAndCombine adds 644f4f6 llvm-symbolizer: Avoid infinite recursion walking dwos where [...] adds 0983344 Fix llvm/test/CodeGen/ARM/Windows/dbzchk.ll not to check mixe [...] adds 4bfa27a AMDGPU: sext_inreg (srl x, K), vt -> bfe x, K, vt.Size adds d52a244 MachO: remove weird ARM/Thumb interface from MachOObjectFile adds c991701 llvm-objdump: deal with invalid ARM encodings slightly better. adds eeabfb0 Style fix in Core.h / Core.cpp. NFC adds bd49c65 [WebAssembly] Set ctlz_zero_undef/cttz_zero_undef to Expand s [...] adds 56f2b77 [NVPTX] Set ctlz_zero_undef to Expand so LegalizeDAG will con [...] adds 85f08cc [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so Le [...] adds c49984d BitcodeReader: Use getMD/getMDOrNull helpers consistently, al [...] adds e416819 BitcodeReader: Consistently use IsDistinct, NFC adds bb8cd12 Tag the end of an anonymous namespace, NFC adds 20c4466 BitcodeReader: Avoid referencing unresolved nodes from distinct ones adds 436d289 ValueEnumerator: Use std::find_if, NFC adds f217c8f Avoid ternery statement to please g++ after r267270, NFC adds 6eed779 Refactor bitcode writer into classes (NFC) adds 26f6676 Address comments. adds bcf5d1f Add #ifndef NDEBUG markers around EXPECT_DEATH after r267270 adds e7a2c97 BitcodeWriter: Emit distinct nodes before uniqued nodes adds f2d5595 Avoid MSVC failure with default arguments in lambdas from r267270 adds 29fa04d BitcodeWriter: Emit uniqued subgraphs after all distinct nodes adds a51154f [gold] Gate value name discarding under save-temps adds 1886c8e [CodeGen] When promoting CTTZ operations to larger type, don' [...] adds 1e3097a Use %T instead of cd'ing to Output directly. adds 91155b6 [X86][XOP] Added VPPERM -> BLEND-WITH-ZERO Test adds e524aca improve documentation comments; NFC adds 72b52a4 Revert "[AArch64] Fix optimizeCondBranch logic." adds 7ceecf0 replace duplicated static functions for profile metadata acce [...] adds de74840 DebugInfo: Remove MDString-based type references adds e66594f BitcodeReader: Avoid non-moving std::piecewise_construct from [...] adds 6e9c743 BitcodeReader: Avoid std::vector with non-movable types from r267296 adds c24d780 [MC/ELF] Pass Fixup to getRelocType64. adds 1e7e2b2 DebugInfo: Change DIBuilder to make distinct DIGlobalVariables adds aa73713 Always traverse GlobalVariable initializer when computing the [...] adds 9ab3b37 Store and emit original name in combined index adds fed32f4 Fix test stability (was sensitive to the path) adds 678f885 Relax test using CHECK-DAG instead of CHECK-NEXT adds 3cabbfe [MC/ELF] Implement support for GOTPCRELX/REX_GOTPCRELX. adds e37fa30 [MC/ELF] Make the relaxation test more interesting. adds b50e1f0 [RuntimeDyldELF] Handle GOTPCRELX/REX_GOTPCRELX. adds 51bf4a5 [X86] Fix patterns that turn cmove/cmovne+ctlz/cttz into lzcn [...] adds 2ea0a37 Fix a couple assertions that can never fire because they just [...] adds bbf2e44 Add an internalization step to the ThinLTOCodeGenerator adds 3f53abc Add a version field in the bitcode for the summary adds 65562d6 Reorganize GlobalValueSummary with a "Flags" bitfield. adds 522b700 Verifier: Verify that each inlinable callsite of a debug-info [...] adds 08290fd Revert "Verifier: Verify that each inlinable callsite of a de [...] adds e5dc889 Fix an assertion that can never fire because the condition AN [...] adds c0f92c9 [CodeGen] Teach DAG combine to fold select_cc seteq X, 0, siz [...] adds f5542f6 [X86] Remove isel patterns for selecting tzcnt/lzcnt from cmo [...] adds 3f71db1 [MachineCombiner] Support for floating-point FMA on ARM64 (re [...] adds 822155b Add "hasSection" flag in the Summary adds 5a6c34b [X86] Node need to check if AVX512 is supported when lowering [...] adds c8d2e3b [X86] Merge LowerCTLZ and LowerCTLZ_ZERO_UNDEF into a single [...] adds a61a99b BitcodeReader: Fix some holes in upgrade from r267296 adds 028b451 llvm/test/tools/gold/X86/thinlto.ll: Possible fix correspondi [...] adds 67d9484 Declare GlobalValue::LinkageTypes based on unsigned. adds 37c06ef Silence two C4806 warnings ('|': unsafe operation: no value o [...] adds ff70139 [X86][SSE] Demonstrate issue with decoding shuffle masks that [...] adds 534be04 [SystemZ] [SSP] Add support for LOAD_STACK_GUARD. adds 879fccd Revert "Declare GlobalValue::LinkageTypes based on unsigned." adds 311d89d ModuleSummaryIndex: Avoid enum bitfields for MSVC portability adds 76e2027 [X86][SSE] Improved support for decoding target shuffle masks [...] adds ff1d728 [ThinLTO] Remove GlobalValueInfo class from index adds f8838c9 BitcodeReader: Delay metadata parsing until reading a function body adds 3f1ed3f [X86][XOP] Fixed VPPERM permute op decoding (PR27472). adds 8b9bfa9 [X86][SSE] Added SSSE3/AVX/AVX2 BITREVERSE tests adds 67c79eb [Lanai] Use EVT::getEVTString() to print a type as a string i [...] adds 3b640cc [X86][SSE] Use range loop. NFCI. adds 2bfa472 [X86][SSE] getTargetShuffleMaskIndices - dropped (unused) UND [...] adds a3ce491 [X86][InstCombine] Tidyup PSHUFB -> shufflevector conversion [...] adds c4d2c7c [X86][InstCombine] Tidyup VPERMILVAR -> shufflevector convers [...] adds 7be7739 Remove emacs mode markers from .cpp files. NFC adds a061370 Fix typo in comment. NFC adds db74d7c [InstCombine] Avoid updating argument demanded elements in se [...] adds 0a660a2 [InstCombine][SSE] Demanded vector elements for scalar intrin [...] adds 6efee72 [InstCombine][SSE] Demanded vector elements for scalar intrin [...] adds a07a9db [InstCombine][SSE] Reduce DIVSS/DIVSD to FDIV if only first e [...] adds fe70286 Tweak comments to make it clear that these combines are for S [...] adds 43355ac ARM: fix __chkstk Frame Setup on WoA adds ff7d156 [X86][AVX] Added PR24935 test case adds 5a63926 Add a test for how we handle protected visibility. adds 4c6a765 Also check the IR. adds c5cc3f2 Verifier: Verify that each inlinable callsite of a debug-info [...] adds 85a7d56 [X86] Add a complete set of tests for all operand sizes of ct [...] adds 5aea4d1 Minor code cleanups. NFC. adds 4bc7520 [X86] Replace a SmallVector used to pass 2 values to an Array [...] adds 50e602f [Support/ELFRelocs] Add R_386_GOT32X. adds 72cd593 Fixing wrong mask size error. From __mmask8 to __mmask16. Was [...] adds 485b34b fix comments related to Differential Revision: http://reviews [...] adds 7d2a815 ThinLTO: Move createNameAnonFunctionPass insertion in PassMan [...] adds 3f9946e Run GlobalOpt before emitting the bitcode for ThinLTO adds c627cc3 [PowerPC] [PR27387] Disallow r0 for ADD8TLS. adds 5a39727 [SCEV] Improve the run-time checking of the NoWrap predicate adds 3c7ad33 [Coverage] Restore the correct count value after processing a [...] adds c8f01da [GlobalOpt] Allow constant globals to be SRA'd adds 8a38a60 [Hexagon] Correctly set "Flags" in ELF header adds 4d87cf6 Typo. NFC. adds 2eaeff8 Test commit: modified comment. NFC adds 2bc6d42 [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax. adds a1ebe98 [ARM] Add support for the X asm constraint adds e7edf2d [WinEH] Update SplitAnalysis::computeLastSplitPoint to cope w [...] adds 3f30242 Fix incorrect redundant expression in target AMDGPU. adds 6cf0df3 [x86] auto-generate checks for cmov tests adds 0b9fb1e [mips][microMIPS] Revert commit r266977 Commit r266977 was re [...] adds 0f2c518 [mips][microMIPS] Revert commit r267137 adds e7311dc [PR27390] [CodeGen] Reject indexed loads in CombinerDAG. adds be88b88 [lanai] Expand findClosestSuitableAluInstr check to consider [...] adds 16c04d1 add tests for potential CGP transform (PR27344) adds cbea336 dsymutil: Only warn about clang module DWO id mismatches in v [...] adds 17bbea1 [ELFRelocs] Other architectures do not have *_NUM reloc. adds e1a7791 [gold-plugin] Remove dead assignment. NFC. adds 3ac68db [ValueTracking] Improve isImpliedCondition when the dominatin [...] adds 8ba06b5 Resubmit "Refactor raw pdb dumper into library" adds cf9b63d [ValueTracking] Add an additional test case for r266767 where [...] adds f104001 [Hexagon] Register save/restore functions do not follow regul [...] adds 2cbb474 [Hexagon] Use llvm-mc instead of llc in an MC testcase adds 4eb3510 [Hexagon] Use llvm-mc instead of llc in an MC testcase adds 82f582e Fix typo from r267432. adds c650ff5 [gold] Fix linkInModule and extend common.ll test. adds 5fad6b4 [LVI] Split solveBlockValueConstantRange into two [NFC] adds acf15d1 [LVI] Clarify comments describing the lattice values adds 30e83b4 [Support] Fix latent bugs in Expected and ExitOnError that we [...] adds 189276d AMDGPU: Add DAG to debug dump adds fda5a0d Add useful helpers to AddrSpaceCastInst adds 51b6e0b AMDGPU: Add queue ptr intrinsic adds f9fe6599 AMDGPU: Implement addrspacecast adds cb05ff9 [libFuzzer] remove dead code adds 3a1034d AMDGPU/SI: Optimize adjacent s_nop instructions adds 1ddbb0f [ORC] Thread Error/Expected through the RPC library. adds 68aaa74 Cleanup redundant expression in InstCombineAndOrXor. adds 3f7fbf7 Re-apply r267206 with a fix for the encoding problem: when th [...] adds 844a2e9 [Hexagon] Few fixes for exception handling adds 4668002 [ThinLTO] Introduce typedef for commonly-used map type (NFC) adds 02e4498 ARM: put extern __thread stubs in a special section. adds 3869f2a [ORC] clang-format code that was touched in r267457. NFC. adds c7ec15c Add accidentally deleted "break" adds aabda75 Add optimization bisect opt-in calls for AArch64 passes adds 78e2fb2 Add optimization bisect opt-in calls for ARM passes adds 185caef [LVI] Make a precondition explicit rather than handling a cas [...] adds 1ca1fca Optimize store of "bitcast" from vector to aggregate. adds 217903d Comment formating. NFC adds 3c50cf9 Reformat LLVMConstPointerNull. NFC adds c7ca130 Add optimization bisect opt-in calls for AMDGPU passes adds f304c12 Fix build warning adds 426203a ARM: put correct symbol index on indirect pointers in __thread_ptr. adds 90cc544 [Sparc] Fix double-float fabs and fneg on little endian CPUs. adds 8070b45 [CMake] If set we should pass LLVM_VERSION_INFO into config.h adds d08220a Add check for "branch_weights" with prof metadata adds 02b4c05 GlobalOpt: Convert a bunch of tests from grep to FileCheck adds 58f1271 [X86] Use LivePhysRegs in X86FixupBWInsts. adds 183519d PM: Convert the logic for GlobalOpt into static functions. NFC adds 1a9ed30 PM: Port GlobalOpt to the new pass manager adds e0e3aca Remove MinLatency in SchedMachineModel. NFC. adds e591202 [CodeGenPrepare] don't convert an unpredictable select into c [...] adds 9dd084a Reverting Thumb2SizeReduction opt bisect change to fix failin [...] adds 562c999 [SROA] Don't falsely report that changes have occured adds aa58a64 [ORC] Try to work around a GCC 4.7 bug triggered by r267457. adds 1a09f22 [WebAssembly] Account for implicit operands when computing op [...] adds b9d01c8 [lli] Fix a sign-compare warning. adds 681428e [LoopVectorize] Don't consider conditional-load dereferenceab [...] adds 1ccb72c [SimplifyCFG] Preserve !llvm.mem.parallel_loop_access when merging adds 8ee4913 [powerpc] mark JIT tests as XFAIL on powerpc64 big endian adds 9c80655 Pass the test file in through stdin instead of by filename. adds edae2f4 [powerpc] mark JIT tests as UNSUPPORTED on powerpc64 big endian adds 0002560 Tune basic block annotation algorithm. adds da46b1d [ARM] Expand v1i64 and v2i64 ctlz. adds 98e886b [ARM] Expand vector ctlz_zero_undef so it becomes ctlz. adds 4234d81 [AArch64] Expand v1i64 and v2i64 ctlz. adds 6588d8d Symbolize operand bundle blocks for bcanalyzer adds 9ad5da1 Align case statements (whitespace-only cleanup) adds 9585d89 [ppc64] Reenable sibling call optimization on ppc64 since fix [...] adds 2f533ed Revert "ARM: put correct symbol index on indirect pointers in [...] adds e1abe9d ThinLTOCodeGenerator: preserve linkonce when in "MustPreserved" set adds 79b1c77 [SPARC] Add support for llvm.thread.pointer. adds eb83c9c [SPARC] [SSP] Add support for LOAD_STACK_GUARD. adds adc800c [PowerPC] Add support for llvm.thread.pointer adds 314a1b6 [Sparc] Fix build error introduced by rL267545. adds 8ddb8b4 [X86] PR27502: Fix the LEA optimization pass. adds 3ca62aa [AMDGPU] Assembler: basic support for SDWA instructions adds 87b2f2a Use gcc's rules for parsing gcc-style response files adds d714ad3 [AMDGPU] Reserve VGPRs for trap handler usage if instructed adds 5571fd8 Refactor some more PDB reading code into DebugInfoPDB. adds c81ec9b Fix build broken due to order of initialization problem. adds 6f5aa79 [CodeGenPrepare] use branch weight metadata to decide if a se [...] adds 5027779 [AMDGPU] Move reserved vgpr count for trap handler usage to S [...] adds 6568fd1 test: remove some bleeding whitespace adds d632f47 tests: tweak MIR for ARM tests to correct MI issues adds a80d09e Swift Calling Convention: use %RAX for sret. adds 783db05 [SimplifyLibCalls] sprintf doesn't copy null bytes adds a536c7f Internalize: More consistent file header and include guards. NFC adds 3005d0c Reapply: "ARM: put correct symbol index on indirect pointers [...] adds 87d4b8c [Tail duplication] Handle source registers with subregisters adds 3784bf8 Parse and dump PDB DBI Stream Header Information adds cff4949 Fix warnings and -Werror build on clang. adds 650fa7d Add optimization bisect opt-in calls for Hexagon passes adds 1330a1c [llvm-pdbdump] Fix version reading on big endian systems. adds c3ce5d9 PM: Port Internalize to the new pass manager adds b7f92d0 Masked Store in Loop Vectorizer - bugfix adds 460e256 Remove more unused variables. adds 45ba8e9 Try to get ResponseFile.ll passing on Windows after r267556. adds de19e3a Revert "[SimplifyLibCalls] sprintf doesn't copy null bytes" adds fb52dfa [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI. adds a5c0577 Optimization bisect support in X86-specific passes adds 7f3fd5d [LVI] Infer local facts from unary expressions adds 7fd37fa Reassociate: Simplify using lambdas. NFC adds d926422 [LowerExpectIntrinsic] make default likely/unlikely ratio bigger adds 1f6f783 [LVI] Speculative fix for assertion seen in clang bots adds 171bf70 [LVI] A better fix for the assertion error introduced by 267609 adds ab87c34 [NVPTX] Fix some usages of CodeGenOpt::None. adds 5fcdfef [LVI] Apply transfer rule for overdefine inputs for binary operators adds b62e247 [MachineInstrBundle] Improvement the recognition of dead defi [...] adds 1b369e4 [MachineBasicBlock] Take advantage of the partially dead info [...] adds 316e8d9 [X86] Teach the expansion of copy instructions how to do prop [...] adds b4a90e6 [SimplifyCFG] propagate branch metadata when creating select adds aa06cc1 [LVI] Cut short search if we know we can't return a useful result adds b7e0749 Reassociate: Convert another functor into a lambda. NFC adds 573cbb5 [X86] Replace -mcpu with -mattr in several tests Differential [...] adds c943cfa PM: Port Reassociate to the new pass manager adds ba357d2 [X86] Make sure it is safe to clobber EFLAGS, if need be, whe [...] adds 347552a Add optimization bisect opt-in calls for NVPTX passes adds 5225ed2 Add optimization bisect opt-in calls for SystemZ passes adds 820df98 [MachineInstrBundle] Update the comment for PhysRegInfo::DeadDef. adds 7ec26d4 [MachineInstrBundle] Actually set the PartialDeadDef flag onl [...] adds 82d78c2 [LVI] Reduce compile time by lazily scanning blocks if needed adds 7f794cf [LoopDist] Split main class. NFC adds e69ab0b LTOCodeGenerator: turns linkonce(_odr) into weak_(odr) when p [...] adds 3082da8 SLSR: Use UnknownAddressSpace instead of 0 for pure arithmetic. adds 3b7741b ThinLTO: do not promote GlobalVariable that have a specific section. adds 9f23dcd [Docs] Try to clarify the concept of domains for noalias scope adds 6d1c855 [LVI] Add a comment explaining a subtle piece of code adds 283390a Detects the SAD pattern on X86 so that much better code will [...] adds 74e636a [X86] Re-enable MMX i32 extractelt combine. adds 4f19679 [X86] Don't assume that MMX extractelts are from index 0. adds 23165ee Fix typo in comment; NFC adds 65bb806 Support "preserving" the summary information when using setMo [...] adds 1ceaa07 Add a test for r267655: Support "preserving" the summary info [...] adds 35f5834 Fix the test from r267656: Support "preserving" the summary i [...] adds 30fc212 [X86] Set AddPristinesAndCSRs to FixupBW LivePhysRegs. NFC. adds 4bbf2a9 [ppc64] fix bug in prologue that mfocrf's cr operand should b [...] adds ee11486 [LVI] Delete stale and misleading comment. adds a27504e The patch fixes PR27392. Summary: It is incorrect to compare [...] adds 0808a65 Revert "Support "preserving" the summary information when usi [...] adds 25a9be2 Support "preserving" the summary information when using setMo [...] adds cb59f17 [Support][X86] Add a couple more Broadwell CPU models numbers [...] adds 666f60a Revert "Support "preserving" the summary information when usi [...] adds cfb5e68 [Support][X86] Change the case values in the Intel family 6 c [...] adds c95e6f9 [Support][X86] Add a few more Intel model numbers to getHostC [...] adds bd93c15 [Cloning] cloneLoopWithPreheader(): add assert to ensure no s [...] adds 8d171c8 [LoopDist] Add llvm.loop.distribute.enable loop metadata adds a47271f Fixed sphinx warning from r267672 adds c81188d [InstCombine][SSE] Added DemandedBits tests for MOVMSK instructions adds 5f2b68d Use DL preferred alignment for alloca in Value::getPointerAlignment adds aeb3be1 isSafeToLoadUnconditionally support queries without a context adds 80ebcca [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, [...] adds 8c34bb0 [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, [...] adds e8bbab4 [InstCombine][SSE] Regenerated vector shift tests adds 25f648c NFC. Introduce Value::getPointerDerferecnceableBytes adds 8777897 [ThinLTO] Use valueid instead of bitcode offsets in combined [...] adds 40978a4 [ThinLTO] Refine fix to avoid renaming of uses in inline assembly. adds 5007064 Remove size 1 from check as that isn't part of what the test [...] adds f519b2d Revert r267649, it caused PR27539. adds d94d7fa [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names o [...] adds d022987 [TTI] Add hook for vector extract with extension adds 0493c73 AMDGPU/SI: Add llvm.amdgcn.s.waitcnt.all intrinsic adds 8a9e8e9 [PDB] Fix function names for private symbols in PDBs adds 7daa491 [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclus [...] adds b4a38c6 Add parentheses to silence buildbot warning adds 3651806 Silence a -Wdangling-else adds 5744c58 [InstCombine] Sharpended test case in pr21210.ll adds 45c07d1 [Mips] Add support for llvm.thread.pointer intrinsic. adds 69bf036 [DAGCombiner] Follow coding convention for function name (NFC) adds 9841605 [SLPVectorizer] Refactor where MinVecRegSize and MaxVecRegSize live. adds facf17c [LV] Reallow positive-stride interleaved load groups with gaps adds 8d96053 Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M [...] adds 09aedbd Clean up to avoid compiler warnings for casting away const qu [...] new fb9b062 Updating branches/google/testing to r267754

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .clang-tidy | 2 +- CMakeLists.txt | 1 + CODE_OWNERS.TXT | 2 +- LICENSE.TXT | 2 +- bindings/ocaml/analysis/analysis_ocaml.c | 1 + bindings/ocaml/bitreader/bitreader_ocaml.c | 5 +- .../ocaml/executionengine/executionengine_ocaml.c | 1 + bindings/ocaml/linker/linker_ocaml.c | 3 +- bindings/ocaml/llvm/llvm.ml | 22 + bindings/ocaml/llvm/llvm.mli | 30 +- bindings/ocaml/llvm/llvm_ocaml.c | 45 + bindings/ocaml/target/llvm_target.ml | 5 +- bindings/ocaml/target/llvm_target.mli | 9 +- bindings/ocaml/target/target_ocaml.c | 14 +- cmake/config-ix.cmake | 1 + cmake/modules/AddLLVM.cmake | 15 +- cmake/modules/GenerateVersionFromCVS.cmake | 39 + cmake/modules/HandleLLVMOptions.cmake | 18 +- cmake/modules/LLVMExternalProjectUtils.cmake | 26 +- cmake/modules/VersionFromVCS.cmake | 24 +- docs/AMDGPUUsage.rst | 23 + docs/Atomics.rst | 186 +- docs/BitCodeFormat.rst | 1 + docs/CommandGuide/lit.rst | 29 + docs/CompileCudaWithLLVM.rst | 20 +- docs/CompilerWriterInfo.rst | 14 +- docs/DeveloperPolicy.rst | 2 +- docs/GettingStartedVS.rst | 6 +- docs/LangRef.rst | 318 +- docs/LibFuzzer.rst | 61 +- docs/NVPTXUsage.rst | 2 +- docs/ProgrammersManual.rst | 5 - docs/ReleaseNotes.rst | 39 +- docs/SourceLevelDebugging.rst | 4 +- docs/tutorial/LangImpl3.rst | 12 +- docs/tutorial/LangImpl4.rst | 3 +- docs/tutorial/LangImpl5.rst | 22 +- docs/tutorial/LangImpl6.rst | 4 +- docs/tutorial/LangImpl7.rst | 4 +- examples/BrainF/BrainFDriver.cpp | 2 +- examples/ExceptionDemo/ExceptionDemo.cpp | 6 +- examples/Kaleidoscope/Chapter3/toy.cpp | 17 +- examples/Kaleidoscope/Chapter4/toy.cpp | 17 +- examples/Kaleidoscope/Chapter5/toy.cpp | 44 +- examples/Kaleidoscope/Chapter6/toy.cpp | 44 +- examples/Kaleidoscope/Chapter7/toy.cpp | 44 +- examples/Kaleidoscope/Chapter8/toy.cpp | 44 +- examples/Kaleidoscope/MCJIT/cached/toy-jit.cpp | 66 +- examples/Kaleidoscope/MCJIT/cached/toy.cpp | 54 +- examples/Kaleidoscope/MCJIT/complete/toy.cpp | 52 +- examples/Kaleidoscope/MCJIT/initial/toy.cpp | 52 +- examples/Kaleidoscope/MCJIT/lazy/toy-jit.cpp | 64 +- examples/Kaleidoscope/MCJIT/lazy/toy.cpp | 52 +- examples/Kaleidoscope/Orc/fully_lazy/toy.cpp | 42 +- examples/Kaleidoscope/Orc/initial/toy.cpp | 42 +- examples/Kaleidoscope/Orc/lazy_codegen/toy.cpp | 42 +- examples/Kaleidoscope/Orc/lazy_irgen/toy.cpp | 42 +- include/llvm-c/Core.h | 101 +- include/llvm-c/OrcBindings.h | 34 +- include/llvm-c/lto.h | 20 +- include/llvm/ADT/APFloat.h | 2 + include/llvm/ADT/APInt.h | 9 +- include/llvm/ADT/DenseMapInfo.h | 30 + include/llvm/ADT/DenseSet.h | 15 + include/llvm/ADT/FoldingSet.h | 3 +- include/llvm/ADT/Hashing.h | 4 +- include/llvm/ADT/STLExtras.h | 12 +- include/llvm/ADT/SmallBitVector.h | 1 - include/llvm/ADT/StringExtras.h | 16 + include/llvm/ADT/StringMap.h | 44 +- include/llvm/Analysis/AliasAnalysis.h | 3 +- include/llvm/Analysis/AliasAnalysisEvaluator.h | 2 - include/llvm/Analysis/AliasSetTracker.h | 16 +- include/llvm/Analysis/AssumptionCache.h | 2 - include/llvm/Analysis/BranchProbabilityInfo.h | 32 +- include/llvm/Analysis/CallGraphSCCPass.h | 10 +- include/llvm/Analysis/ConstantFolding.h | 13 +- include/llvm/Analysis/DemandedBits.h | 74 +- include/llvm/Analysis/DependenceAnalysis.h | 2 +- include/llvm/Analysis/IteratedDominanceFrontier.h | 6 +- include/llvm/Analysis/Loads.h | 6 +- include/llvm/Analysis/LoopPass.h | 7 +- include/llvm/Analysis/MemoryBuiltins.h | 14 +- include/llvm/Analysis/MemoryLocation.h | 2 +- include/llvm/Analysis/ModuleSummaryAnalysis.h | 86 + include/llvm/Analysis/RegionInfoImpl.h | 1 - include/llvm/Analysis/ScalarEvolution.h | 274 +- include/llvm/Analysis/TargetLibraryInfo.def | 5 + include/llvm/Analysis/TargetLibraryInfo.h | 64 +- include/llvm/Analysis/TargetTransformInfo.h | 65 +- include/llvm/Analysis/TargetTransformInfoImpl.h | 13 +- include/llvm/Analysis/ValueTracking.h | 48 +- include/llvm/Analysis/VectorUtils.h | 29 +- include/llvm/Bitcode/BitcodeWriterPass.h | 16 +- include/llvm/Bitcode/BitstreamReader.h | 2 + include/llvm/Bitcode/LLVMBitCodes.h | 908 +- include/llvm/Bitcode/ReaderWriter.h | 22 +- include/llvm/CodeGen/AsmPrinter.h | 4 + include/llvm/CodeGen/BasicTTIImpl.h | 123 +- include/llvm/CodeGen/CallingConvLower.h | 8 + include/llvm/CodeGen/DIE.h | 1 - include/llvm/CodeGen/FastISel.h | 8 +- include/llvm/CodeGen/FaultMaps.h | 1 - include/llvm/CodeGen/FunctionLoweringInfo.h | 31 + include/llvm/CodeGen/GlobalISel/CallLowering.h | 6 +- include/llvm/CodeGen/GlobalISel/GISelAccessor.h | 33 + include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 6 +- include/llvm/CodeGen/GlobalISel/RegBankSelect.h | 168 + include/llvm/CodeGen/GlobalISel/RegisterBank.h | 101 + include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 445 + include/llvm/CodeGen/GlobalISel/Types.h | 1 - include/llvm/CodeGen/ISDOpcodes.h | 3 + include/llvm/CodeGen/LiveIntervalAnalysis.h | 1 - include/llvm/CodeGen/LivePhysRegs.h | 8 +- include/llvm/CodeGen/LiveRangeEdit.h | 39 +- include/llvm/CodeGen/MIRParser/MIRParser.h | 2 +- include/llvm/CodeGen/MachineBasicBlock.h | 12 +- include/llvm/CodeGen/MachineCombinerPattern.h | 35 +- include/llvm/CodeGen/MachineFrameInfo.h | 98 +- include/llvm/CodeGen/MachineFunction.h | 19 +- include/llvm/CodeGen/MachineInstr.h | 21 +- include/llvm/CodeGen/MachineInstrBuilder.h | 46 +- include/llvm/CodeGen/MachineInstrBundle.h | 10 +- include/llvm/CodeGen/MachineLoopInfo.h | 54 +- include/llvm/CodeGen/MachineModuleInfoImpls.h | 13 + include/llvm/CodeGen/MachineRegisterInfo.h | 104 +- include/llvm/CodeGen/MachineSSAUpdater.h | 1 - include/llvm/CodeGen/MachineScheduler.h | 8 +- include/llvm/CodeGen/MachineValueType.h | 18 +- include/llvm/CodeGen/PBQP/Graph.h | 5 - include/llvm/CodeGen/ParallelCG.h | 22 +- include/llvm/CodeGen/Passes.h | 21 + include/llvm/CodeGen/RegAllocPBQP.h | 1 + include/llvm/CodeGen/RegisterScavenging.h | 4 +- include/llvm/CodeGen/RuntimeLibcalls.h | 71 +- include/llvm/CodeGen/ScheduleDAGInstrs.h | 9 +- include/llvm/CodeGen/ScheduleHazardRecognizer.h | 11 + include/llvm/CodeGen/ScoreboardHazardRecognizer.h | 6 +- include/llvm/CodeGen/SelectionDAG.h | 42 +- include/llvm/CodeGen/SelectionDAGNodes.h | 11 +- include/llvm/CodeGen/SelectionDAGTargetInfo.h | 6 + include/llvm/CodeGen/StackMaps.h | 2 - include/llvm/CodeGen/StackProtector.h | 10 + include/llvm/CodeGen/TailDuplicator.h | 93 + .../llvm/CodeGen/TargetLoweringObjectFileImpl.h | 11 +- include/llvm/CodeGen/ValueTypes.h | 2 +- include/llvm/CodeGen/ValueTypes.td | 16 +- include/llvm/Config/config.h.cmake | 3 + include/llvm/DebugInfo/CodeView/TypeIndex.h | 2 + .../llvm/DebugInfo/CodeView/TypeSymbolEmitter.h | 3 +- include/llvm/DebugInfo/CodeView/TypeTableBuilder.h | 4 +- include/llvm/DebugInfo/DIContext.h | 1 - include/llvm/DebugInfo/DWARF/DWARFCompileUnit.h | 6 +- include/llvm/DebugInfo/DWARF/DWARFContext.h | 7 +- include/llvm/DebugInfo/DWARF/DWARFDebugAbbrev.h | 1 - include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h | 1 - include/llvm/DebugInfo/DWARF/DWARFFormValue.h | 2 +- include/llvm/DebugInfo/DWARF/DWARFTypeUnit.h | 6 +- include/llvm/DebugInfo/DWARF/DWARFUnit.h | 16 +- include/llvm/DebugInfo/PDB/DIA/DIASession.h | 3 +- include/llvm/DebugInfo/PDB/IPDBSession.h | 1 + include/llvm/DebugInfo/PDB/PDBExtras.h | 1 + include/llvm/DebugInfo/PDB/PDBSymbol.h | 3 +- include/llvm/DebugInfo/PDB/PDBSymbolAnnotation.h | 1 - include/llvm/DebugInfo/PDB/PDBSymbolBlock.h | 1 - include/llvm/DebugInfo/PDB/PDBSymbolExe.h | 1 - include/llvm/DebugInfo/PDB/PDBSymbolThunk.h | 1 - include/llvm/DebugInfo/PDB/PDBTypes.h | 37 +- include/llvm/DebugInfo/PDB/Raw/PDBDbiStream.h | 52 + include/llvm/DebugInfo/PDB/Raw/PDBFile.h | 69 + include/llvm/DebugInfo/PDB/Raw/PDBInfoStream.h | 64 + include/llvm/DebugInfo/PDB/Raw/PDBNameMap.h | 34 + include/llvm/DebugInfo/PDB/Raw/PDBRawConstants.h | 39 + include/llvm/DebugInfo/PDB/Raw/PDBStream.h | 46 + include/llvm/DebugInfo/PDB/Raw/RawSession.h | 72 + .../llvm/DebugInfo/Symbolize/SymbolizableModule.h | 2 - include/llvm/ExecutionEngine/GenericValue.h | 1 + include/llvm/ExecutionEngine/Orc/CompileUtils.h | 5 +- include/llvm/ExecutionEngine/Orc/IRCompileLayer.h | 7 +- .../llvm/ExecutionEngine/Orc/IndirectionUtils.h | 112 +- include/llvm/ExecutionEngine/Orc/LambdaResolver.h | 1 - .../llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h | 6 +- .../ExecutionEngine/Orc/OrcArchitectureSupport.h | 22 +- include/llvm/ExecutionEngine/Orc/OrcError.h | 6 +- .../ExecutionEngine/Orc/OrcRemoteTargetClient.h | 507 +- .../ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h | 181 +- .../ExecutionEngine/Orc/OrcRemoteTargetServer.h | 199 +- include/llvm/ExecutionEngine/Orc/RPCChannel.h | 166 +- include/llvm/ExecutionEngine/Orc/RPCUtils.h | 610 +- include/llvm/ExecutionEngine/RTDyldMemoryManager.h | 1 - include/llvm/ExecutionEngine/RuntimeDyld.h | 5 +- include/llvm/ExecutionEngine/RuntimeDyldChecker.h | 2 +- include/llvm/IR/Argument.h | 6 + include/llvm/IR/Attributes.h | 37 +- include/llvm/IR/Attributes.td | 12 + include/llvm/IR/CallSite.h | 16 + include/llvm/IR/CallingConv.h | 12 + include/llvm/IR/Comdat.h | 4 +- include/llvm/IR/Constants.h | 114 +- include/llvm/IR/DIBuilder.h | 40 +- include/llvm/IR/DataLayout.h | 3 - include/llvm/IR/DebugInfo.h | 16 +- include/llvm/IR/DebugInfoMetadata.h | 286 +- include/llvm/IR/DiagnosticInfo.h | 8 +- include/llvm/IR/Dominators.h | 12 +- include/llvm/IR/Function.h | 11 +- include/llvm/IR/GVMaterializer.h | 10 - include/llvm/IR/GlobalAlias.h | 29 +- include/llvm/IR/GlobalIFunc.h | 76 + include/llvm/IR/GlobalIndirectSymbol.h | 68 + include/llvm/IR/GlobalObject.h | 1 - include/llvm/IR/GlobalValue.h | 124 +- include/llvm/IR/GlobalVariable.h | 6 +- include/llvm/IR/IRBuilder.h | 2 +- include/llvm/IR/InstrTypes.h | 49 +- include/llvm/IR/Instruction.h | 34 + include/llvm/IR/Instructions.h | 121 +- include/llvm/IR/IntrinsicInst.h | 11 +- include/llvm/IR/Intrinsics.h | 1 + include/llvm/IR/Intrinsics.td | 76 +- include/llvm/IR/IntrinsicsAArch64.td | 31 +- include/llvm/IR/IntrinsicsAMDGPU.td | 40 +- include/llvm/IR/IntrinsicsARM.td | 31 +- include/llvm/IR/IntrinsicsHexagon.td | 22 +- include/llvm/IR/IntrinsicsMips.td | 22 +- include/llvm/IR/IntrinsicsNVVM.td | 6 +- include/llvm/IR/IntrinsicsPowerPC.td | 36 +- include/llvm/IR/IntrinsicsSystemZ.td | 8 +- include/llvm/IR/IntrinsicsX86.td | 500 +- include/llvm/IR/LLVMContext.h | 20 +- include/llvm/IR/LegacyPassManagers.h | 15 +- include/llvm/IR/Mangler.h | 2 +- include/llvm/IR/Metadata.def | 1 + include/llvm/IR/Metadata.h | 151 +- include/llvm/IR/Module.h | 105 +- include/llvm/IR/ModuleSlotTracker.h | 6 +- include/llvm/IR/ModuleSummaryIndex.h | 374 +- include/llvm/IR/Operator.h | 4 +- include/llvm/IR/OptBisect.h | 81 + include/llvm/IR/PassManager.h | 6 - include/llvm/IR/PatternMatch.h | 37 + include/llvm/IR/Statepoint.h | 45 +- include/llvm/IR/SymbolTableListTraits.h | 2 + include/llvm/IR/TrackingMDRef.h | 1 - include/llvm/IR/Type.h | 1 + include/llvm/IR/Use.h | 2 - include/llvm/IR/UseListOrder.h | 2 - include/llvm/IR/User.h | 4 +- include/llvm/IR/Value.def | 5 + include/llvm/IR/Value.h | 35 +- include/llvm/IR/ValueMap.h | 25 +- include/llvm/IR/ValueSymbolTable.h | 3 +- include/llvm/IR/Verifier.h | 2 - include/llvm/IRReader/IRReader.h | 5 +- include/llvm/InitializePasses.h | 23 +- include/llvm/LTO/LTOCodeGenerator.h | 33 +- include/llvm/LTO/ThinLTOCodeGenerator.h | 26 +- include/llvm/LibDriver/LibDriver.h | 6 +- include/llvm/LinkAllIR.h | 5 +- include/llvm/LinkAllPasses.h | 3 +- include/llvm/Linker/IRMover.h | 11 +- include/llvm/Linker/Linker.h | 17 +- include/llvm/MC/MCAsmBackend.h | 8 +- include/llvm/MC/MCAsmInfo.h | 6 + include/llvm/MC/MCDisassembler/MCDisassembler.h | 2 +- include/llvm/MC/MCDwarf.h | 6 +- include/llvm/MC/MCELFStreamer.h | 1 - include/llvm/MC/MCInstPrinter.h | 2 +- include/llvm/MC/MCMachObjectWriter.h | 1 - include/llvm/MC/MCObjectFileInfo.h | 4 + include/llvm/MC/MCParser/MCAsmLexer.h | 2 + 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| 23 +- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 18 +- lib/Target/ARM/ARMCallingConv.td | 39 + lib/Target/ARM/ARMConstantIslandPass.cpp | 11 +- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 277 +- lib/Target/ARM/ARMFastISel.cpp | 41 +- lib/Target/ARM/ARMFrameLowering.cpp | 47 +- lib/Target/ARM/ARMFrameLowering.h | 2 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 172 +- lib/Target/ARM/ARMISelLowering.cpp | 230 +- lib/Target/ARM/ARMISelLowering.h | 6 + lib/Target/ARM/ARMInstrInfo.td | 65 +- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 11 +- lib/Target/ARM/ARMMachineFunctionInfo.h | 1 - lib/Target/ARM/ARMOptimizeBarriersPass.cpp | 8 + lib/Target/ARM/ARMScheduleA8.td | 1 - lib/Target/ARM/ARMTargetMachine.cpp | 1 - lib/Target/ARM/ARMTargetObjectFile.h | 8 +- lib/Target/ARM/ARMTargetTransformInfo.cpp | 25 +- lib/Target/ARM/ARMTargetTransformInfo.h | 9 + lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 30 + lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 11 + lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h | 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.../Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp | 1 + lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h | 1 - .../Hexagon/MCTargetDesc/HexagonMCChecker.cpp | 1 - lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h | 5 +- .../Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp | 19 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 54 +- lib/Target/Hexagon/RDFGraph.h | 1 - lib/Target/Hexagon/RDFLiveness.cpp | 4 +- lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp | 23 +- lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp | 179 +- lib/Target/Lanai/LanaiDelaySlotFiller.cpp | 12 + lib/Target/Lanai/LanaiFrameLowering.cpp | 4 +- lib/Target/Lanai/LanaiFrameLowering.h | 2 +- lib/Target/Lanai/LanaiISelLowering.cpp | 96 +- lib/Target/Lanai/LanaiISelLowering.h | 16 +- lib/Target/Lanai/LanaiInstrInfo.cpp | 94 +- lib/Target/Lanai/LanaiInstrInfo.h | 11 + lib/Target/Lanai/LanaiInstrInfo.td | 77 +- lib/Target/Lanai/LanaiMCInstLower.cpp | 5 +- lib/Target/Lanai/LanaiMemAluCombiner.cpp | 16 +- lib/Target/Lanai/LanaiSchedule.td | 36 +- lib/Target/Lanai/LanaiSetflagAluCombiner.cpp | 19 +- lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h | 1 - lib/Target/MSP430/MSP430BranchSelector.cpp | 5 + lib/Target/MSP430/MSP430FrameLowering.cpp | 9 +- lib/Target/MSP430/MSP430FrameLowering.h | 6 +- lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 1 - lib/Target/MSP430/MSP430ISelLowering.cpp | 2 +- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 737 +- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 114 +- lib/Target/Mips/MCTargetDesc/MipsABIInfo.h | 2 +- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 30 + .../Mips/MCTargetDesc/MipsELFObjectWriter.cpp | 7 +- lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h | 9 + lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 75 +- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h | 1 + lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 7 +- .../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 20 +- lib/Target/Mips/MicroMips32r6InstrFormats.td | 66 +- lib/Target/Mips/MicroMips32r6InstrInfo.td | 188 +- lib/Target/Mips/MicroMips64r6InstrFormats.td | 41 + lib/Target/Mips/MicroMips64r6InstrInfo.td | 142 + lib/Target/Mips/MicroMipsInstrFPU.td | 4 +- lib/Target/Mips/MicroMipsInstrInfo.td | 43 +- lib/Target/Mips/Mips16FrameLowering.cpp | 1 - lib/Target/Mips/Mips16ISelLowering.cpp | 2 - lib/Target/Mips/Mips16InstrInfo.cpp | 4 +- lib/Target/Mips/Mips16InstrInfo.td | 12 +- lib/Target/Mips/Mips16RegisterInfo.cpp | 2 - lib/Target/Mips/Mips32r6InstrInfo.td | 28 +- lib/Target/Mips/Mips64InstrInfo.td | 183 +- lib/Target/Mips/Mips64r6InstrInfo.td | 24 +- lib/Target/Mips/MipsAsmPrinter.cpp | 7 +- lib/Target/Mips/MipsConstantIslandPass.cpp | 8 +- lib/Target/Mips/MipsDelaySlotFiller.cpp | 54 +- lib/Target/Mips/MipsEVAInstrInfo.td | 4 +- lib/Target/Mips/MipsFrameLowering.cpp | 5 +- lib/Target/Mips/MipsFrameLowering.h | 2 +- lib/Target/Mips/MipsHazardSchedule.cpp | 8 +- lib/Target/Mips/MipsISelLowering.cpp | 51 +- lib/Target/Mips/MipsInstrFPU.td | 16 +- lib/Target/Mips/MipsInstrInfo.cpp | 109 +- lib/Target/Mips/MipsInstrInfo.td | 293 +- lib/Target/Mips/MipsLongBranch.cpp | 9 +- lib/Target/Mips/MipsMCInstLower.h | 1 - lib/Target/Mips/MipsMSAInstrInfo.td | 20 +- lib/Target/Mips/MipsMachineFunction.h | 3 - lib/Target/Mips/MipsOs16.cpp | 26 +- lib/Target/Mips/MipsRegisterInfo.cpp | 11 +- lib/Target/Mips/MipsSEFrameLowering.cpp | 9 +- lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 22 +- lib/Target/Mips/MipsSEISelLowering.cpp | 24 +- lib/Target/Mips/MipsSEInstrInfo.cpp | 5 +- lib/Target/Mips/MipsSERegisterInfo.cpp | 2 - lib/Target/Mips/MipsTargetStreamer.h | 9 +- lib/Target/NVPTX/NVPTX.h | 6 +- lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 3 +- lib/Target/NVPTX/NVPTXAsmPrinter.h | 2 - .../NVPTX/NVPTXFavorNonGenericAddrSpaces.cpp | 2 +- lib/Target/NVPTX/NVPTXFrameLowering.cpp | 5 +- lib/Target/NVPTX/NVPTXFrameLowering.h | 2 +- lib/Target/NVPTX/NVPTXGenericToNVVM.cpp | 3 +- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 85 +- lib/Target/NVPTX/NVPTXISelLowering.cpp | 31 +- lib/Target/NVPTX/NVPTXImageOptimizer.cpp | 3 + lib/Target/NVPTX/NVPTXInferAddressSpaces.cpp | 4 +- lib/Target/NVPTX/NVPTXInstrInfo.td | 247 +- lib/Target/NVPTX/NVPTXIntrinsics.td | 87 +- lib/Target/NVPTX/NVPTXLowerAlloca.cpp | 3 + lib/Target/NVPTX/NVPTXPeephole.cpp | 3 + lib/Target/NVPTX/NVPTXSection.h | 1 - lib/Target/NVPTX/NVPTXTargetMachine.cpp | 15 +- lib/Target/NVPTX/NVPTXTargetObjectFile.h | 1 - lib/Target/NVPTX/NVPTXTargetTransformInfo.h | 4 + lib/Target/NVPTX/NVVMReflect.cpp | 175 +- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 47 +- lib/Target/PowerPC/CMakeLists.txt | 1 + .../PowerPC/Disassembler/PPCDisassembler.cpp | 6 + lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp | 11 - .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 5 - lib/Target/PowerPC/PPC.h | 2 +- lib/Target/PowerPC/PPC.td | 38 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 - lib/Target/PowerPC/PPCBranchSelector.cpp | 6 +- lib/Target/PowerPC/PPCCTRLoops.cpp | 3 - lib/Target/PowerPC/PPCCallingConv.td | 11 + lib/Target/PowerPC/PPCEarlyReturn.cpp | 11 +- lib/Target/PowerPC/PPCFastISel.cpp | 21 +- lib/Target/PowerPC/PPCFrameLowering.cpp | 121 +- lib/Target/PowerPC/PPCFrameLowering.h | 13 +- lib/Target/PowerPC/PPCISelLowering.cpp | 500 +- lib/Target/PowerPC/PPCISelLowering.h | 26 + lib/Target/PowerPC/PPCInstr64Bit.td | 114 +- lib/Target/PowerPC/PPCInstrFormats.td | 136 + lib/Target/PowerPC/PPCInstrInfo.cpp | 20 + lib/Target/PowerPC/PPCInstrInfo.h | 3 + lib/Target/PowerPC/PPCInstrInfo.td | 70 + lib/Target/PowerPC/PPCInstrVSX.td | 19 +- lib/Target/PowerPC/PPCMachineFunctionInfo.h | 10 +- lib/Target/PowerPC/PPCQPXLoadSplat.cpp | 156 + lib/Target/PowerPC/PPCRegisterInfo.cpp | 28 + lib/Target/PowerPC/PPCRegisterInfo.h | 1 + lib/Target/PowerPC/PPCRegisterInfo.td | 20 + lib/Target/PowerPC/PPCSchedule.td | 7 + lib/Target/PowerPC/PPCSchedule440.td | 1 - lib/Target/PowerPC/PPCScheduleA2.td | 5 +- lib/Target/PowerPC/PPCScheduleE500mc.td | 13 +- lib/Target/PowerPC/PPCScheduleE5500.td | 17 +- lib/Target/PowerPC/PPCScheduleG5.td | 15 +- lib/Target/PowerPC/PPCScheduleP7.td | 1 - lib/Target/PowerPC/PPCScheduleP8.td | 1 - lib/Target/PowerPC/PPCSubtarget.cpp | 5 +- lib/Target/PowerPC/PPCSubtarget.h | 18 +- lib/Target/PowerPC/PPCTOCRegDeps.cpp | 5 +- lib/Target/PowerPC/PPCTargetMachine.cpp | 18 +- lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 17 +- lib/Target/PowerPC/PPCVSXCopy.cpp | 5 +- lib/Target/PowerPC/README_P9.txt | 112 + lib/Target/Sparc/DelaySlotFiller.cpp | 7 +- lib/Target/Sparc/Sparc.td | 41 + lib/Target/Sparc/SparcAsmPrinter.cpp | 1 - lib/Target/Sparc/SparcFrameLowering.cpp | 4 +- lib/Target/Sparc/SparcFrameLowering.h | 2 +- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 1 - lib/Target/Sparc/SparcISelLowering.cpp | 234 +- lib/Target/Sparc/SparcISelLowering.h | 8 + lib/Target/Sparc/SparcInstr64Bit.td | 33 - lib/Target/Sparc/SparcInstrFormats.td | 122 +- lib/Target/Sparc/SparcInstrInfo.cpp | 16 + lib/Target/Sparc/SparcInstrInfo.h | 3 + lib/Target/Sparc/SparcInstrInfo.td | 290 +- lib/Target/Sparc/SparcMCInstLower.cpp | 1 - lib/Target/Sparc/SparcSchedule.td | 121 + lib/Target/Sparc/SparcSubtarget.cpp | 2 +- lib/Target/Sparc/SparcSubtarget.h | 5 + .../SystemZ/Disassembler/SystemZDisassembler.cpp | 55 +- lib/Target/SystemZ/README.txt | 18 +- lib/Target/SystemZ/SystemZAsmPrinter.cpp | 170 + lib/Target/SystemZ/SystemZElimCompare.cpp | 71 +- lib/Target/SystemZ/SystemZFrameLowering.cpp | 4 +- lib/Target/SystemZ/SystemZFrameLowering.h | 7 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 129 +- lib/Target/SystemZ/SystemZISelLowering.h | 14 + lib/Target/SystemZ/SystemZInstrFormats.td | 48 + lib/Target/SystemZ/SystemZInstrInfo.cpp | 177 +- lib/Target/SystemZ/SystemZInstrInfo.h | 17 + lib/Target/SystemZ/SystemZInstrInfo.td | 152 +- lib/Target/SystemZ/SystemZLDCleanup.cpp | 3 + lib/Target/SystemZ/SystemZLongBranch.cpp | 5 +- lib/Target/SystemZ/SystemZMachineFunctionInfo.h | 9 +- lib/Target/SystemZ/SystemZOperands.td | 8 +- lib/Target/SystemZ/SystemZOperators.td | 2 + lib/Target/SystemZ/SystemZRegisterInfo.cpp | 8 +- lib/Target/SystemZ/SystemZRegisterInfo.h | 9 + lib/Target/SystemZ/SystemZShortenInst.cpp | 7 + lib/Target/SystemZ/SystemZTargetMachine.cpp | 3 +- lib/Target/Target.cpp | 7 +- lib/Target/TargetMachine.cpp | 3 +- lib/Target/TargetRecip.cpp | 5 +- lib/Target/TargetSubtargetInfo.cpp | 2 - .../InstPrinter/WebAssemblyInstPrinter.h | 1 + .../MCTargetDesc/WebAssemblyMCAsmInfo.cpp | 1 - .../MCTargetDesc/WebAssemblyTargetStreamer.cpp | 1 - .../WebAssemblyFixIrreducibleControlFlow.cpp | 2 +- .../WebAssembly/WebAssemblyFrameLowering.cpp | 5 +- lib/Target/WebAssembly/WebAssemblyFrameLowering.h | 2 +- lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 3 +- lib/Target/WebAssembly/WebAssemblyInstrInteger.td | 6 - lib/Target/WebAssembly/WebAssemblyPEI.cpp | 17 +- .../WebAssembly/WebAssemblySetP2AlignOperands.cpp | 12 +- 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