[gcc] branch master updated (9175741f0df -> 8dba9c7ec97) - Tcwg-commits

9 May 2025


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unknown user pushed a change to branch master
in repository gcc.
from  9175741f0df Daily bump.
       new  b81e970de6f RISC-V: Separate the test running of rvv vx_vf
       new  cd694ab6c75 RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
       new  5ee51001ec0 RISC-V: Add testcases for vec_duplicate + vadd.vv combine c [...]
       new  6a718d401d3 RISC-V: Add testcases for vec_duplicate + vadd.vv combine c [...]
       new  8dba9c7ec97 RISC-V: Add testcases for vec_duplicate + vadd.vv combine c [...]
The 5 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
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Summary of changes:
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 62 ++++++++++++++++++----
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c         |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c         |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c         |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c         |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c         |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c        |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c         |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c         |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c         |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c         |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c         |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c         |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c        |  9 ++++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c        |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c         |  8 +++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c    |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c    |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c    |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c     |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c    |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c    |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c    |  4 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c     |  4 +-
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp         | 15 ++++++
 58 files changed, 301 insertions(+), 49 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c
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