[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allyesconfig updated (1a2d2b492a3 -> 54c52242034) - Tcwg-commits

26 Dec 2019


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allyesconfig
in repository toolchain/ci/llvm-project.
from  1a2d2b492a3 [llvm-readobj] - Merge `gnu-symbols.test` to `symbols.test` [...]
      adds  80c45e49c33 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
      adds  aff6c9db9a9 [compiler-rt] [netbsd] Correct the fallback definition of P [...]
      adds  ba1cdba4c48 [llvm-nm] Display STT_GNU_IFUNC as 'i'
      adds  2498d882598 [X86] Merge together some common code in LowerFP_TO_INT now [...]
      adds  caf460d979a [lldb][NFC] Use StringRef in ClangASTContext::GetBuiltinTyp [...]
      adds  4af5b23db30 [X86FixupSetCC] Remember the preceding eflags defining inst [...]
      adds  c5b4a2386b5 [X86] Use zero vector to extend to 512-bits for strict_fp_t [...]
      adds  f9c3c5da19a [OpenMP][IR-Builder] Introduce the finalization stack
      adds  2e6c15d1e7a Make lazyload_metadata.ll resilient to the addition of new  [...]
      adds  e4add9727b4 [OpenMP][IR-Builder] Introduce "pragma omp parallel" code g [...]
      adds  cb6e84fe368 test commit
      adds  b082a2952f6 Revert "test commit"
      adds  472bded3eda [X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend
      adds  6cf6f7dc96d Revert "Make lazyload_metadata.ll resilient to the addition [...]
      adds  6d88b7d6e71 [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
      adds  d1f41b2ca99 [NFC][LoopFusion] Fix printing of the guard branch. Reviewe [...]
      adds  e973783916d [NFC][PowerPC] Add a function tryAndWithMask to handle all  [...]
      adds  6599d004679 [Bitstream] Delete skipAbbreviatedField which duplicates re [...]
      adds  1b57749a533 [PowerPC] stop folding if result rlwinm mask is wrap while  [...]
      adds  d2a8e14177f Fix the MLIR Vim syntax file: the keyword group was missing
      adds  073cdb23904 [clang][test] Minor fixes in testcase absolute-paths-symlinks.c
      adds  b036f557cee [lldb] Remove some calls to GetASTContext
      adds  54c52242034 [compiler-rt] Disable QSORT interception on watchOS and tvOS.
No new revisions were added by this update.
Summary of changes:
 clang/lib/CodeGen/CGOpenMPRuntime.cpp              |   66 +-
 clang/test/Frontend/absolute-paths-symlinks.c      |    8 +-
 .../sanitizer_platform_interceptors.h              |   15 +-
 .../sanitizer_platform_limits_netbsd.cpp           |    4 +-
 lld/test/ELF/ppc64-ifunc.s                         |    4 +-
 lldb/include/lldb/Symbol/ClangASTContext.h         |    6 +-
 .../Clang/ClangExpressionDeclMap.cpp               |   25 +-
 .../SymbolFile/DWARF/DWARFASTParserClang.cpp       |    4 +-
 .../source/Plugins/SymbolFile/PDB/PDBASTParser.cpp |   21 +-
 lldb/source/Symbol/ClangASTContext.cpp             |   93 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst                |  163 +--
 llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst                 |   15 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst                 |   15 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst                 |   19 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst               |   58 +
 llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst               |   58 +
 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst               |   93 ++
 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst               |  165 +++
 ...x9_mad_type_dev.rst => gfx900_mad_type_dev.rst} |    2 +-
 ...ad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} |    9 +-
 llvm/docs/AMDGPU/gfx900_src32_0.rst                |   17 +
 llvm/docs/AMDGPU/gfx900_src32_1.rst                |   17 +
 .../{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} |   10 +-
 ...x9_mad_type_dev.rst => gfx904_mad_type_dev.rst} |    2 +-
 ...ad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} |    9 +-
 llvm/docs/AMDGPU/gfx904_src32_0.rst                |   17 +
 llvm/docs/AMDGPU/gfx904_src32_1.rst                |   17 +
 .../{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} |   10 +-
 ...x9_mad_type_dev.rst => gfx906_mad_type_dev.rst} |    2 +-
 ...ype_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} |    9 +-
 ...9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} |    9 +-
 ...ad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} |    9 +-
 llvm/docs/AMDGPU/gfx906_src32_0.rst                |   17 +
 llvm/docs/AMDGPU/gfx906_src32_1.rst                |   17 +
 llvm/docs/AMDGPU/gfx906_src32_2.rst                |   17 +
 .../{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} |    9 +-
 .../{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} |   10 +-
 .../{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} |   10 +-
 llvm/docs/AMDGPU/gfx908_addr_buf.rst               |   22 +
 ...gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} |   10 +-
 ...{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} |   10 +-
 .../{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} |   10 +-
 ...{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} |   10 +-
 ...gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} |   10 +-
 ...{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} |   10 +-
 .../{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} |   10 +-
 ...{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} |   10 +-
 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst      |   21 +
 ...d_type_dev.rst => gfx908_dst_flat_atomic32.rst} |   12 +-
 ...x9_mad_type_dev.rst => gfx908_mad_type_dev.rst} |    2 +-
 ...ype_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} |    9 +-
 ...9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} |    9 +-
 ...ad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} |    9 +-
 llvm/docs/AMDGPU/gfx908_offset_buf.rst             |   17 +
 .../{gfx9_mad_type_dev.rst => gfx908_opt.rst}      |    9 +-
 .../{gfx9_mad_type_dev.rst => gfx908_ret.rst}      |    9 +-
 .../{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} |   10 +-
 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst      |   19 +
 llvm/docs/AMDGPU/gfx908_src32_0.rst                |   17 +
 llvm/docs/AMDGPU/gfx908_src32_1.rst                |   17 +
 llvm/docs/AMDGPU/gfx908_src32_2.rst                |   17 +
 .../{gfx9_mad_type_dev.rst => gfx908_src32_3.rst}  |   10 +-
 .../{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} |    9 +-
 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst      |   22 +
 ...{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} |   10 +-
 ...{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} |   10 +-
 ...{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} |   10 +-
 .../{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} |   10 +-
 .../{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} |   10 +-
 llvm/docs/AMDGPUModifierSyntax.rst                 |   55 +-
 llvm/docs/AMDGPUOperandSyntax.rst                  |   60 +
 llvm/docs/AMDGPUUsage.rst                          |   38 +-
 llvm/include/llvm/Frontend/OpenMP/OMPConstants.h   |   18 +-
 llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h   |  106 +-
 llvm/include/llvm/Frontend/OpenMP/OMPKinds.def     |   28 +
 llvm/lib/Bitstream/Reader/BitstreamReader.cpp      |   38 +-
 .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp |   15 +-
 llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp          |  336 ++++-
 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp        |  231 ++--
 llvm/lib/Target/PowerPC/PPCInstr64Bit.td           |    2 +
 llvm/lib/Target/PowerPC/PPCInstrInfo.td            |    2 +
 llvm/lib/Target/PowerPC/PPCMIPeephole.cpp          |    8 +-
 llvm/lib/Target/X86/X86FixupSetCC.cpp              |   32 +-
 llvm/lib/Target/X86/X86ISelLowering.cpp            |  171 ++-
 llvm/lib/Target/X86/X86ISelLowering.h              |    1 +
 llvm/lib/Target/X86/X86InstrAVX512.td              |   30 +-
 llvm/lib/Target/X86/X86InstrFragmentsSIMD.td       |    9 +
 llvm/lib/Target/X86/X86InstrSSE.td                 |   12 +-
 llvm/lib/Transforms/Scalar/LoopFuse.cpp            |    7 +-
 llvm/test/CodeGen/PowerPC/CSR-fit.ll               |    8 +-
 .../CodeGen/PowerPC/MCSE-caller-preserved-reg.ll   |    2 +-
 llvm/test/CodeGen/PowerPC/csr-split.ll             |    6 +-
 llvm/test/CodeGen/PowerPC/fold-rlwinm.mir          |   15 +
 llvm/test/CodeGen/PowerPC/machine-pre.ll           |    2 +-
 .../test/CodeGen/PowerPC/not-fixed-frame-object.ll |    2 +-
 .../PowerPC/ppcf128-constrained-fp-intrinsics.ll   |    8 +-
 llvm/test/CodeGen/PowerPC/pr43527.ll               |    2 +-
 llvm/test/CodeGen/PowerPC/pr44183.ll               |    2 +-
 llvm/test/CodeGen/PowerPC/sjlj.ll                  |    2 +-
 llvm/test/CodeGen/PowerPC/sms-phi-1.ll             |    2 +-
 llvm/test/CodeGen/PowerPC/sms-phi-3.ll             |    2 +-
 llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll     |    2 +-
 .../PowerPC/vector-constrained-fp-intrinsics.ll    |   64 +-
 llvm/test/CodeGen/X86/fp-intrinsics.ll             |   40 +-
 llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll  | 1305 ++++++++++++++++++++
 llvm/test/CodeGen/X86/fp80-strict-scalar.ll        |  270 ++++
 llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll    |    3 +-
 llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll    |   86 +-
 llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll    |  646 ++++++++++
 llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll    |  421 +++++++
 llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll    |  390 ++++++
 .../X86/vector-constrained-fp-intrinsics.ll        |  342 +++--
 llvm/test/LTO/Resolution/X86/ifunc.ll              |    2 +-
 llvm/test/tools/llvm-nm/ifunc.test                 |   27 +
 llvm/tools/llvm-nm/llvm-nm.cpp                     |   13 +-
 llvm/unittests/Frontend/CMakeLists.txt             |    1 +
 llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp    |  324 ++++-
 mlir/utils/vim/syntax/mlir.vim                     |    6 +-
 118 files changed, 5649 insertions(+), 966 deletions(-)
 create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst
 create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst
 create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst
 create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mad_type_dev.rst} (94%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mad_type_dev.rst} (94%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mad_type_dev.rst} (94%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx908_addr_buf.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_dst_flat_atomic32.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mad_type_dev.rst} (94%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx908_offset_buf.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_opt.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_ret.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst
 create mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} (52%)
 create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} (52%)
 copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} (52%)
 rename llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} (52%)
 create mode 100644 llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
 create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
 create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
 create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
 create mode 100644 llvm/test/tools/llvm-nm/ifunc.test
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