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from e767da23de1 AVX512FP16: Fix masm=intel output for vfc?(madd|mul)csh [PR [...] new 5177634148a RISC-V: Implement misc macro for vector extensions.

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 16 +++---- gcc/config/riscv/riscv-c.cc | 18 +++++++ gcc/config/riscv/riscv-opts.h | 25 ++++++++-- gcc/config/riscv/riscv.opt | 2 +- gcc/testsuite/gcc.target/riscv/arch-13.c | 5 ++ gcc/testsuite/gcc.target/riscv/arch-14.c | 5 ++ gcc/testsuite/gcc.target/riscv/arch-15.c | 5 ++ .../gcc.target/riscv/{predef-15.c => predef-18.c} | 51 +++++++++----------- .../gcc.target/riscv/{predef-16.c => predef-19.c} | 55 ++++++++++------------ .../gcc.target/riscv/{predef-15.c => predef-20.c} | 51 +++++++++----------- 10 files changed, 133 insertions(+), 100 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-15.c copy gcc/testsuite/gcc.target/riscv/{predef-15.c => predef-18.c} (55%) copy gcc/testsuite/gcc.target/riscv/{predef-16.c => predef-19.c} (54%) copy gcc/testsuite/gcc.target/riscv/{predef-15.c => predef-20.c} (55%)