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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap in repository toolchain/ci/gcc.

from e767da23de1 AVX512FP16: Fix masm=intel output for vfc?(madd|mul)csh [PR [...] adds 5177634148a RISC-V: Implement misc macro for vector extensions.

No new revisions were added by this update.

Summary of changes: gcc/common/config/riscv/riscv-common.cc | 16 +++--- gcc/config/riscv/riscv-c.cc | 18 ++++++ gcc/config/riscv/riscv-opts.h | 25 +++++++-- gcc/config/riscv/riscv.opt | 2 +- gcc/testsuite/gcc.target/riscv/arch-13.c | 5 ++ gcc/testsuite/gcc.target/riscv/arch-14.c | 5 ++ gcc/testsuite/gcc.target/riscv/arch-15.c | 5 ++ gcc/testsuite/gcc.target/riscv/predef-18.c | 84 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-19.c | 88 ++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-20.c | 84 ++++++++++++++++++++++++++++ 10 files changed, 319 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-20.c