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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-Oz in repository toolchain/ci/llvm-project.

from e72381990e5 [git-llvm] Only use --force-interactive when supported adds b68566aec32 [runtime] Use --strip-all rather than --strip-sections adds 1a872f2b151 Recommit r355224 "[TableGen][SelectionDAG][X86] Add specifi [...] adds a2b144fc740 [TableGen] Make CheckImmAllOnesVMatcher and CheckImmAllZero [...] adds 369a011cee0 [lldb] [test] Make 2lwp_process_SIGSEGV test more portable adds bfec0d610cb [AArch64] Add tests for saddsat/ssubsat; NFC adds 0dc8c52d4e9 [X86] Remove dead code from the handler for INTR_TYPE_SCALA [...] adds 93e15dfacce [X86] Make lowering of intrinsics with rounding mode strict [...] adds 66c9690ad6e [X86] Remove unused variable. NFC adds 7d8260feb60 [CGP] fix comments; NFC adds 26e06e859e2 [x86] add x86-specific opcodes to extractelement scalarizat [...] adds 0affb5822f1 Quiet command regex instructions during batch execution adds a135fd5562d Remove redundant extractBooleanFlip argument. NFC new 4cf8cdc51d1 [X86] Remove VCVTSI2SDZrrb_Int as it shouldn't exist. new d8ebbe4a763 [X86] Remove unneeded isel patterns from VCVTSI2SDZ and VCV [...] new a5820cbd20f Add test case for add to sub post legalization. NFC new 428dcd5c3f2 [PowerPC] Remove the override of isMachineVerifierClean() t [...]

The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: lldb/include/lldb/Core/IOHandler.h | 2 +- lldb/include/lldb/Expression/REPL.h | 2 +- lldb/lit/Commands/command-regex-delete.test | 2 +- lldb/lit/Commands/command-regex-unalias.test | 2 +- .../netbsd-core/2lwp_process_SIGSEGV.amd64 | Bin 15816 -> 16344 bytes .../netbsd-core/2lwp_process_SIGSEGV.amd64.core | Bin 121208 -> 121216 bytes .../postmortem/netbsd-core/2lwp_process_SIGSEGV.c | 7 +- .../postmortem/netbsd-core/TestNetBSDCore.py | 6 +- .../Commands/CommandObjectBreakpointCommand.cpp | 4 +- lldb/source/Commands/CommandObjectCommands.cpp | 10 +- lldb/source/Commands/CommandObjectTarget.cpp | 4 +- lldb/source/Commands/CommandObjectType.cpp | 8 +- .../Commands/CommandObjectWatchpointCommand.cpp | 4 +- lldb/source/Core/IOHandler.cpp | 2 +- lldb/source/Expression/REPL.cpp | 2 +- .../Python/ScriptInterpreterPython.cpp | 4 +- .../Python/ScriptInterpreterPython.h | 2 +- llvm/include/llvm/CodeGen/SelectionDAGISel.h | 2 + llvm/include/llvm/Target/TargetSelectionDAG.td | 13 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 + llvm/lib/Target/PowerPC/PPCTargetMachine.h | 4 - llvm/lib/Target/SystemZ/SystemZOperators.td | 20 +- llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 126 +-- llvm/lib/Target/X86/X86InstrAVX512.td | 94 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 1 - llvm/lib/Target/X86/X86InstrSSE.td | 2 +- llvm/lib/Target/X86/X86InstrVecCompiler.td | 2 +- llvm/runtimes/llvm-strip-link.in | 2 +- llvm/test/CodeGen/AArch64/sadd_sat.ll | 73 ++ llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 923 ++++++++++++++++++++ llvm/test/CodeGen/AArch64/ssub_sat.ll | 74 ++ llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 965 +++++++++++++++++++++ llvm/test/CodeGen/X86/addcarry.ll | 26 + .../CodeGen/X86/avx512-fma-intrinsics-upgrade.ll | 48 +- llvm/test/CodeGen/X86/avx512-fma-intrinsics.ll | 48 +- .../CodeGen/X86/avx512-intrinsics-fast-isel.ll | 40 +- llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 144 +-- llvm/test/CodeGen/X86/avx512-intrinsics-x86_64.ll | 24 +- llvm/test/CodeGen/X86/avx512-intrinsics.ll | 228 ++--- .../CodeGen/X86/avx512dq-intrinsics-upgrade.ll | 8 +- llvm/test/CodeGen/X86/avx512dq-intrinsics.ll | 24 +- llvm/test/CodeGen/X86/extractelement-fp.ll | 14 +- llvm/test/CodeGen/X86/fma-fneg-combine.ll | 12 +- llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll | 66 +- llvm/test/CodeGen/X86/vector-reduce-fmax.ll | 66 +- llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll | 66 +- llvm/test/CodeGen/X86/vector-reduce-fmin.ll | 66 +- llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 16 +- llvm/utils/TableGen/DAGISelMatcher.cpp | 23 + llvm/utils/TableGen/DAGISelMatcher.h | 36 + llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 10 + llvm/utils/TableGen/DAGISelMatcherGen.cpp | 21 + 55 files changed, 2760 insertions(+), 609 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sadd_sat.ll create mode 100644 llvm/test/CodeGen/AArch64/sadd_sat_vec.ll create mode 100644 llvm/test/CodeGen/AArch64/ssub_sat.ll create mode 100644 llvm/test/CodeGen/AArch64/ssub_sat_vec.ll