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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project.

from 7fef551cb12 Revert "Revert "[FPEnv] Teach the IRBuilder about invoke's [...] adds fc7b7fc0669 [RISCV] Add intrinsics for vmv.v.v, vmv.v.x, and vmv.x.i adds a74941da716 Revert "[BasicAA] Handle two unknown sizes for GEPs" adds d551e40f1cf [AIX] Change the code based on https://lists.llvm.org/piper [...] adds 5e5ef535974 [clang-format][NFC] Expand BreakBeforeBraces examples adds 5f75dcf5719 [DebugInfo] Support Fortran 'use <external module>' statement. adds 9b183a1452c [NFC][InstSimplify] Add miscompiled testcase from D87188/D87197 adds e9289dc25f7 [InstSimplify] Don't miscompile `X == 0 ? abs(X) : -abs(X) [...] adds 897c985e1e2 [InstCombine] Canonicalize SPF to abs intrinsic adds 5ac37725df3 [GVNHoist] Remove successorDominate (NFC) adds 86d282baede [RISCV] Add intrinsics for vmv.x.s and vmv.s.x adds 0e94ba9d40d [NFC][InstCombine] Fixup check lines for prof md in select_ [...] adds 46a40c4bc10 [RISCV] Add intrinsics for vfmv.f.s and vfmv.s.f adds cd3e8118648 Revert "[RISCV] Add intrinsics for vfmv.f.s and vfmv.s.f" adds 1c3a6671c25 Recommit "[RISCV] Add intrinsics for vfmv.f.s and vfmv.s.f" adds 1f1145006b3 [DSE] Use correct memory location for read clobber check adds 09468a91482 [RISCV] Sign extend constant arguments to V intrinsics when [...] adds 2af2f58ec09 [InstCombine] Regenerate test checks (NFC) adds 9c978dd6e12 [TableGen] Fix D90844 introduced non-determinism due to ite [...] adds 69c8d121f7f [RISCV] Add intrinsics for vsetvli instruction adds 08c4b4054b3 Rename files with same (case insensitive) name adds d4ed253d0b8 [RISCV] Assume no-op addrspacecasts by default adds b4c63ef6dd9 [c++20] Mark class type NTTPs as done and start defining th [...] adds 939ba0b501b Add tests for the absence of feature test macros for featur [...] adds 72d8f79f0c3 [c++2b] Add tests for feature test macros. adds ed13d8c6678 Fix memory leak complicated non-type template arguments. adds 37d0dda739a [SLP] fix typo; NFC adds 7948cd11d17 [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. adds f5cef870d11 [www] Remove '$Date$' marker from cxx_dr_status. adds adc55b5a5ae [X86] Avoid generating invalid R_X86_64_GOTPCRELX relocations adds b0615642f64 [clangd] Make our printing policies for Hover more consiste [...] adds af83b74dc2e [VE] Support copy of vector mask registers adds ffd982f7db5 [ObjC][ARC] Fix a bug where the inline-asm retain/claim RV [...] adds 2fced5a07b4 [clangd] Don't cancel requests based on "updates" with same [...] adds 1ab4db0f847 [HotColdSplit] Reflect full cost of parameters in split penalty adds 2b62e623288 [clangd] Fix windows path handling in .clang-tidy parsing adds 44f399ccc12 [FileCheck] Add a literal check directive modifier adds bf0870d8640 [flang] Fix bug in IMPLICIT NONE(EXTERNAL) adds a913a583f00 [lldb] Simplify the is_finalized logic in process and make [...] adds 805d59593f5 [Analysis, CodeGen, IR] Use contains (NFC) adds 195f44278c4 [ARM] Implement harden-sls-retbr for ARM mode adds c061cb521b9 [gn build] Port 195f44278c4 adds 320fd3314e3 [ARM] Implement harden-sls-retbr for Thumb mode adds a4c1f5160e6 [ARM] Harden indirect calls against SLS adds df8ed392837 [ARM] harden-sls-blr: avoid r12 and lr in indirect calls. adds 9c895aea118 [ARM] Add clang command line support for -mharden-sls= adds 9cf3b1b6665 [RISCV] Define vlxe/vsxe/vsuxe intrinsics. adds 5740f96d8ee [NFC][libc++] Fixes swapped comments. adds 1e785e92624 apply update_test_checks.py to a few files in llvm/test/Tra [...]

No new revisions were added by this update.

Summary of changes: clang-tools-extra/clangd/Hover.cpp | 107 +- clang-tools-extra/clangd/TUScheduler.cpp | 63 +- clang-tools-extra/clangd/TidyProvider.cpp | 11 +- clang-tools-extra/clangd/unittests/HoverTests.cpp | 12 +- .../clangd/unittests/TUSchedulerTests.cpp | 32 + clang/docs/ClangFormatStyleOptions.rst | 446 +- clang/include/clang/AST/ASTContext.h | 4 +- clang/include/clang/Basic/DiagnosticDriverKinds.td | 2 + clang/include/clang/Format/Format.h | 446 +- clang/lib/AST/TemplateBase.cpp | 1 + clang/lib/Driver/ToolChains/Arch/ARM.cpp | 45 + clang/lib/Driver/ToolChains/Arch/ARM.h | 1 + clang/lib/Frontend/InitPreprocessor.cpp | 2 +- clang/test/CodeGen/builtins-wasm.c | 18 +- clang/test/Driver/aarch64-sls-hardening-options.c | 45 - clang/test/Driver/sls-hardening-options.c | 97 + clang/test/Lexer/cxx-features.cpp | 170 +- clang/www/cxx_dr_status.html | 1 - clang/www/cxx_status.html | 2 +- clang/www/make_cxx_dr_status | 1 - flang/lib/Semantics/resolve-names.cpp | 19 +- flang/test/Semantics/implicit07.f90 | 3 + .../libcxx/iterators/trivial_iterators.pass.cpp | 4 +- lld/test/ELF/x86-64-gotpc-relax-nopic.s | 4 +- lldb/include/lldb/Target/Process.h | 13 +- lldb/source/Target/Process.cpp | 21 +- llvm/docs/CommandGuide/FileCheck.rst | 24 + llvm/include/llvm/FileCheck/FileCheck.h | 25 +- llvm/include/llvm/IR/DIBuilder.h | 12 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 26 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 87 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 20 +- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 3 +- llvm/lib/Analysis/DivergenceAnalysis.cpp | 6 +- llvm/lib/Analysis/IRSimilarityIdentifier.cpp | 10 +- llvm/lib/Analysis/InstructionSimplify.cpp | 9 +- llvm/lib/AsmParser/LLParser.cpp | 7 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 9 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 + llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 2 + .../CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 2 +- llvm/lib/FileCheck/FileCheck.cpp | 118 +- llvm/lib/IR/AsmWriter.cpp | 1 + llvm/lib/IR/DIBuilder.cpp | 5 +- llvm/lib/IR/DebugInfoMetadata.cpp | 6 +- llvm/lib/IR/LLVMContextImpl.h | 11 +- llvm/lib/IR/ModuleSummaryIndex.cpp | 2 +- llvm/lib/Target/ARM/ARM.h | 3 + llvm/lib/Target/ARM/ARM.td | 14 + llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 42 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 51 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 65 + llvm/lib/Target/ARM/ARMCallLowering.cpp | 9 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 11 + llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 5 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 14 +- llvm/lib/Target/ARM/ARMFeatures.h | 1 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 35 +- llvm/lib/Target/ARM/ARMInstrThumb.td | 13 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 9 + llvm/lib/Target/ARM/ARMPredicates.td | 3 + llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 12 +- llvm/lib/Target/ARM/ARMRegisterInfo.td | 17 + llvm/lib/Target/ARM/ARMSLSHardening.cpp | 416 ++ llvm/lib/Target/ARM/ARMSubtarget.h | 10 + llvm/lib/Target/ARM/ARMTargetMachine.cpp | 4 + llvm/lib/Target/ARM/CMakeLists.txt | 1 + llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 65 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 69 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 5 + llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 10 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 348 ++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 21 +- llvm/lib/Target/RISCV/RISCVTargetMachine.h | 5 +- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 2 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 3 +- llvm/lib/Target/VE/VEInstrInfo.cpp | 15 + .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 13 +- llvm/lib/Transforms/IPO/HotColdSplitting.cpp | 61 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 79 +- llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp | 2 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 79 +- llvm/lib/Transforms/Scalar/GVNHoist.cpp | 9 - llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +- llvm/test/Analysis/BasicAA/phi-aa.ll | 3 +- llvm/test/Analysis/BasicAA/recphi.ll | 3 +- llvm/test/Assembler/dimodule.ll | 7 +- .../Bitcode/DIModule-fortran-external-module.ll | 59 + llvm/test/CodeGen/ARM/O3-pipeline.ll | 4 + llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 246 + llvm/test/CodeGen/RISCV/addrspacecast.ll | 49 + .../CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll | 33 + .../CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll | 51 + llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll | 44 +- llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll | 76 +- llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll | 204 + llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll | 203 + llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll | 203 + llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll | 3281 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll | 5361 +++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll | 44 +- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll | 236 + llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll | 288 + llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll | 505 ++ llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll | 617 +++ llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll | 505 ++ llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll | 617 +++ llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll | 236 + llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll | 288 + llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll | 72 +- llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll | 3445 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll | 5629 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll | 3445 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll | 5629 ++++++++++++++++++++ llvm/test/CodeGen/VE/Vector/fastcc_callee.ll | 17 + .../DebugInfo/X86/dimodule-external-fortran.ll | 91 + llvm/test/FileCheck/check-literal.txt | 62 + llvm/test/MC/ELF/got-relaxed-rex.s | 36 - llvm/test/MC/X86/gotpcrelx.s | 65 + .../Transforms/CodeExtractor/extract-assume.ll | 2 +- .../MSSA/multiblock-memintrinsics.ll | 4 +- .../MSSA/out-of-bounds-stores.ll | 2 + .../DeadStoreElimination/MSSA/overlap.ll | 6 +- .../DeadStoreElimination/MSSA/scoped-noalias.ll | 4 +- .../HotColdSplit/apply-penalty-for-inputs.ll | 21 +- .../HotColdSplit/apply-penalty-for-outputs.ll | 8 +- .../HotColdSplit/apply-successor-penalty.ll | 13 +- .../HotColdSplit/assumption-cache-invalidation.ll | 7 +- llvm/test/Transforms/InstCombine/CPP_min_max.ll | 54 +- llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll | 18 +- llvm/test/Transforms/InstCombine/abs-1.ll | 232 +- llvm/test/Transforms/InstCombine/abs_abs.ll | 496 +- llvm/test/Transforms/InstCombine/bitcast.ll | 12 +- llvm/test/Transforms/InstCombine/call-callconv.ll | 12 +- .../test/Transforms/InstCombine/clamp-to-minmax.ll | 102 +- llvm/test/Transforms/InstCombine/cttz-abs.ll | 11 +- llvm/test/Transforms/InstCombine/icmp.ll | 18 +- .../Transforms/InstCombine/insert-const-shuf.ll | 20 +- llvm/test/Transforms/InstCombine/max-of-nots.ll | 10 +- llvm/test/Transforms/InstCombine/minmax-fp.ll | 68 +- llvm/test/Transforms/InstCombine/pr21199.ll | 19 +- .../Transforms/InstCombine/preserve-sminmax.ll | 24 +- llvm/test/Transforms/InstCombine/select_meta.ll | 102 +- llvm/test/Transforms/InstCombine/smax-icmp.ll | 48 +- llvm/test/Transforms/InstCombine/smin-icmp.ll | 48 +- .../Transforms/InstCombine/sub-of-negatible.ll | 8 +- llvm/test/Transforms/InstCombine/umax-icmp.ll | 48 +- llvm/test/Transforms/InstCombine/umin-icmp.ll | 48 +- llvm/test/Transforms/InstSimplify/abs_intrinsic.ll | 32 + .../Transforms/LoopVectorize/ARM/pointer_iv.ll | 59 +- .../exit-block-dominates-rt-check-block.ll | 6 +- llvm/test/Transforms/ObjCARC/contract-marker.ll | 20 + .../PhaseOrdering/X86/vector-reductions.ll | 8 +- .../Transforms/PhaseOrdering/min-max-abs-cse.ll | 11 +- llvm/unittests/IR/MetadataTest.cpp | 22 +- llvm/utils/TableGen/CodeGenSchedule.cpp | 3 + llvm/utils/TableGen/CodeGenSchedule.h | 2 +- .../gn/secondary/llvm/lib/Target/ARM/BUILD.gn | 1 + 163 files changed, 35080 insertions(+), 1798 deletions(-) delete mode 100644 clang/test/Driver/aarch64-sls-hardening-options.c create mode 100644 clang/test/Driver/sls-hardening-options.c create mode 100644 llvm/lib/Target/ARM/ARMSLSHardening.cpp create mode 100644 llvm/test/Bitcode/DIModule-fortran-external-module.ll create mode 100644 llvm/test/CodeGen/ARM/speculation-hardening-sls.ll create mode 100644 llvm/test/CodeGen/RISCV/addrspacecast.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll create mode 100644 llvm/test/DebugInfo/X86/dimodule-external-fortran.ll create mode 100644 llvm/test/FileCheck/check-literal.txt delete mode 100644 llvm/test/MC/ELF/got-relaxed-rex.s