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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allmodconfig in repository toolchain/ci/binutils-gdb.

from 4d56d64a85 gdb/testsuite: fix comment in gdb.threads/non-ldr-exit.exp adds 0ae4576980 Add missing ChangeLog entry. adds 539d71e89a PowerPC remove 512 bytes region limit if 2nd DAWR is avaliable. adds 0a6155a072 gdb/testsuite: use foreach_with_prefix in gdb.threads/non-ld [...] adds f55a9a37d8 gdb/testsuite: fix indentation in gdb.threads/non-ldr-exc-1.exp adds e89b3d5293 Automatic date update in version.in adds 77bf7e9911 Use new+delete for struct expression adds 2bf3b79d05 Search for DWZ files in debug-file-directories as well adds 12bf652539 Sync .gitignore with gcc adds 7ddfb1a891 Add gnu global outputs to .gitignore adds e450204220 gdb/riscv: place unknown csrs into the correct register groups adds 533b2ae07d gdb/riscv: remove csr aliases created with DECLARE_CSR_ALIAS adds 2542804022 gdb/riscv: rewrite target description validation, add rv32e support

No new revisions were added by this update.

Summary of changes: .gitignore | 10 + ChangeLog | 8 + bfd/version.h | 2 +- gdb/ChangeLog | 90 +++ gdb/arch/riscv.c | 15 +- gdb/arch/riscv.h | 9 +- gdb/dwarf2/read.c | 107 ++- gdb/expression.h | 23 +- gdb/features/Makefile | 1 + gdb/features/riscv/{32bit-cpu.c => rv32e-xregs.c} | 20 +- .../riscv/{32bit-cpu.xml => rv32e-xregs.xml} | 16 - gdb/parse.c | 49 +- gdb/ppc-linux-nat.c | 26 +- gdb/riscv-tdep.c | 755 ++++++++++++--------- gdb/riscv-tdep.h | 5 + gdb/testsuite/ChangeLog | 24 + gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp | 41 +- gdb/testsuite/gdb.threads/non-ldr-exc-1.exp | 61 +- gdb/testsuite/gdb.threads/non-ldr-exc-2.exp | 67 +- gdb/testsuite/gdb.threads/non-ldr-exc-3.exp | 61 +- gdb/testsuite/gdb.threads/non-ldr-exc-4.exp | 61 +- 21 files changed, 897 insertions(+), 554 deletions(-) copy gdb/features/riscv/{32bit-cpu.c => rv32e-xregs.c} (54%) copy gdb/features/riscv/{32bit-cpu.xml => rv32e-xregs.xml} (65%)