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from f896fc0f2b Correct timespec implementation [BZ #26232] new 34f0d01d5e AArch64: Align ENTRY to a cacheline new 4a733bf375 AArch64: Add optimized Q-register memcpy new 0f6278a879 AArch64: Rename IS_ARES to IS_NEOVERSE_N1

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Summary of changes: sysdeps/aarch64/multiarch/Makefile | 2 +- sysdeps/aarch64/multiarch/ifunc-impl-list.c | 2 + sysdeps/aarch64/multiarch/memcpy.c | 7 +- .../{memcpy.S => multiarch/memcpy_advsimd.S} | 205 +++++++++------------ sysdeps/aarch64/multiarch/memmove.c | 5 +- sysdeps/aarch64/sysdep.h | 2 +- sysdeps/unix/sysv/linux/aarch64/cpu-features.h | 4 +- 7 files changed, 99 insertions(+), 128 deletions(-) copy sysdeps/aarch64/{memcpy.S => multiarch/memcpy_advsimd.S} (54%)