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from 51fd69ec2d5 RISC-V: Refactor the framework of RVV auto-vectorization new b0ad9159a5a md: Allow <FOO> to refer to the value of int iterator FOO new b096a6ebe9d aarch64: Provide FPR alternatives for some bit insertions [ [...]

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Summary of changes: gcc/config/aarch64/aarch64.cc | 12 ++ gcc/config/aarch64/aarch64.md | 62 +++++++++ gcc/config/aarch64/iterators.md | 4 + gcc/doc/md.texi | 15 ++- gcc/read-rtl.cc | 26 ++++ gcc/testsuite/gcc.target/aarch64/ins_bitfield_1.c | 142 ++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/ins_bitfield_2.c | 142 ++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/ins_bitfield_3.c | 156 ++++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/ins_bitfield_4.c | 156 ++++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/ins_bitfield_5.c | 139 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/ins_bitfield_6.c | 139 +++++++++++++++++++ 11 files changed, 987 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_6.c