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from dee55cf59ce RISC-V: Support movmisalign of RVV VLA modes new f8498436d6d RISC-V: Add initial pipeline description for an out-of-order core. new 79e6ea48b7b RISC-V Regression test: Adapt SLP tests like ARM SVE new db20b83cfff RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV

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Summary of changes: gcc/config/riscv/generic-ooo.md | 284 ++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-cores.def | 1 + gcc/config/riscv/riscv-opts.h | 3 +- gcc/config/riscv/riscv.cc | 87 ++++++++++ gcc/config/riscv/riscv.md | 5 +- gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/vector.md | 3 +- gcc/testsuite/gcc.dg/vect/slp-23.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-perm-10.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-reduc-4.c | 2 +- 10 files changed, 385 insertions(+), 7 deletions(-) create mode 100644 gcc/config/riscv/generic-ooo.md