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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allyesconfig in repository toolchain/ci/linux.

from 36487907f341 Merge branch 'akpm' (patches from Andrew) adds ac51e005fe14 riscv: mm: use __pa_symbol for kernel symbols adds 0da310e82d3a riscv: gcov: enable gcov for RISC-V adds cfda8617e22a riscv: dts: Add DT support for SiFive L2 cache controller adds 1d8f65798240 riscv: ftrace: correct the condition logic in function gra [...] adds 9d05c18e8d7d clocksource: riscv: add notrace to riscv_sched_clock adds 2f3035da4019 riscv: prefix IRQ_ macro names with an RV_ namespace adds 0e194d9da198 Documentation: riscv: add patch acceptance guidelines adds 768fc661d125 Merge tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub [...] adds c79f46a28239 Linux 5.5-rc5

No new revisions were added by this update.

Summary of changes: .../debug/gcov-profile-all/arch-support.txt | 2 +- Documentation/process/index.rst | 1 + Documentation/riscv/index.rst | 1 + Documentation/riscv/patch-acceptance.rst | 35 ++++++++++++++++++++++ MAINTAINERS | 1 + Makefile | 2 +- arch/riscv/Kconfig | 1 + arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 ++++++++++ arch/riscv/include/asm/csr.h | 18 +++++------ arch/riscv/kernel/ftrace.c | 2 +- arch/riscv/kernel/irq.c | 6 ++-- arch/riscv/mm/init.c | 12 ++++---- drivers/clocksource/timer-riscv.c | 2 +- drivers/irqchip/irq-sifive-plic.c | 2 +- 14 files changed, 77 insertions(+), 23 deletions(-) create mode 100644 Documentation/riscv/patch-acceptance.rst